target/linux/mpc85xx/patches-3.10/150-dts-p1010rdb-pa.patch

   1 From 41ec72d74b9453cd0d4b60d188ae894b8bdc4ca6 Mon Sep 17 00:00:00 2001
   2 From: Heiner Kallweit <hkallweit1@gmail.com>
   3 Date: Thu, 20 Nov 2014 18:33:47 +0100
   4 Subject: [PATCH] create dts target p1010rdb-pa
   5  With kernel 3.14 dts target p1010rdb was renamed to p1010rdb-pa.
   6  Create a copy of p1010rdb.dts to maintain compatibility.
   7
   8 ---
   9  arch/powerpc/boot/dts/p1010rdb-pa.dts | 66 +++++++++++++++++++++++++++++++++++
  10  1 file changed, 66 insertions(+)
  11  create mode 100644 arch/powerpc/boot/dts/p1010rdb-pa.dts
  12
  13 diff --git a/arch/powerpc/boot/dts/p1010rdb-pa.dts b/arch/powerpc/boot/dts/p1010rdb-pa.dts
  14 new file mode 100644
  15 index 0000000..b868d22
  16 --- /dev/null
  17 +++ b/arch/powerpc/boot/dts/p1010rdb-pa.dts
  18 @@ -0,0 +1,66 @@
  19 +/*
  20 + * P1010 RDB Device Tree Source
  21 + *
  22 + * Copyright 2011 Freescale Semiconductor Inc.
  23 + *
  24 + * This program is free software; you can redistribute  it and/or modify it
  25 + * under  the terms of  the GNU General  Public License as published by the
  26 + * Free Software Foundation;  either version 2 of the  License, or (at your
  27 + * option) any later version.
  28 + */
  29 +
  30 +/include/ "fsl/p1010si-pre.dtsi"
  31 +
  32 +/ {
  33 +       model = "fsl,P1010RDB";
  34 +       compatible = "fsl,P1010RDB";
  35 +
  36 +       memory {
  37 +               device_type = "memory";
  38 +       };
  39 +
  40 +       board_ifc: ifc: ifc@ffe1e000 {
  41 +               /* NOR, NAND Flashes and CPLD on board */
  42 +               ranges = <0x0 0x0 0x0 0xee000000 0x02000000
  43 +                         0x1 0x0 0x0 0xff800000 0x00010000
  44 +                         0x3 0x0 0x0 0xffb00000 0x00000020>;
  45 +               reg = <0x0 0xffe1e000 0 0x2000>;
  46 +       };
  47 +
  48 +       board_soc: soc: soc@ffe00000 {
  49 +               ranges = <0x0 0x0 0xffe00000 0x100000>;
  50 +       };
  51 +
  52 +       pci0: pcie@ffe09000 {
  53 +               reg = <0 0xffe09000 0 0x1000>;
  54 +               ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  55 +                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  56 +               pcie@0 {
  57 +                       ranges = <0x2000000 0x0 0xa0000000
  58 +                                 0x2000000 0x0 0xa0000000
  59 +                                 0x0 0x20000000
  60 +
  61 +                                 0x1000000 0x0 0x0
  62 +                                 0x1000000 0x0 0x0
  63 +                                 0x0 0x100000>;
  64 +               };
  65 +       };
  66 +
  67 +       pci1: pcie@ffe0a000 {
  68 +               reg = <0 0xffe0a000 0 0x1000>;
  69 +               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  70 +                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  71 +               pcie@0 {
  72 +                       ranges = <0x2000000 0x0 0x80000000
  73 +                                 0x2000000 0x0 0x80000000
  74 +                                 0x0 0x20000000
  75 +
  76 +                                 0x1000000 0x0 0x0
  77 +                                 0x1000000 0x0 0x0
  78 +                                 0x0 0x100000>;
  79 +               };
  80 +       };
  81 +};
  82 +
  83 +/include/ "p1010rdb.dtsi"
  84 +/include/ "fsl/p1010si-post.dtsi"
  85 --
  86 2.1.3
  87