target/linux/mediatek/patches-4.4/0074-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch

   1 From 5e1c00983efeca4522ac2e8574e3e3997d26a203 Mon Sep 17 00:00:00 2001
   2 From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
   3 Date: Fri, 29 Apr 2016 12:17:21 -0400
   4 Subject: [PATCH 074/102] mtd: mediatek: device tree docs for MTK Smart Device
   5  Gen1 NAND
   6
   7 This patch adds documentation support for Smart Device Gen1 type of
   8 NAND controllers.
   9
  10 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  11 ---
  12  Documentation/devicetree/bindings/mtd/mtk-nand.txt |  161 ++++++++++++++++++++
  13  1 file changed, 161 insertions(+)
  14  create mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt
  15
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
  18 @@ -0,0 +1,161 @@
  19 +MTK SoCs NAND FLASH controller (NFC) DT binding
  20 +
  21 +This file documents the device tree bindings for MTK SoCs NAND controllers.
  22 +The functional split of the controller requires two drivers to operate:
  23 +the nand controller interface driver and the ECC engine driver.
  24 +
  25 +The hardware description for both devices must be captured as device
  26 +tree nodes.
  27 +
  28 +1) NFC NAND Controller Interface (NFI):
  29 +=======================================
  30 +
  31 +The first part of NFC is NAND Controller Interface (NFI) HW.
  32 +Required NFI properties:
  33 +- compatible:                  Should be "mediatek,mtxxxx-nfc".
  34 +- reg:                         Base physical address and size of NFI.
  35 +- interrupts:                  Interrupts of NFI.
  36 +- clocks:                      NFI required clocks.
  37 +- clock-names:                 NFI clocks internal name.
  38 +- status:                      Disabled default. Then set "okay" by platform.
  39 +- ecc-engine:                  Required ECC Engine node.
  40 +- #address-cells:              NAND chip index, should be 1.
  41 +- #size-cells:                 Should be 0.
  42 +
  43 +Example:
  44 +
  45 +       nandc: nfi@1100d000 {
  46 +               compatible = "mediatek,mt2701-nfc";
  47 +               reg = <0 0x1100d000 0 0x1000>;
  48 +               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
  49 +               clocks = <&pericfg CLK_PERI_NFI>,
  50 +                        <&pericfg CLK_PERI_NFI_PAD>;
  51 +               clock-names = "nfi_clk", "pad_clk";
  52 +               status = "disabled";
  53 +               ecc-engine = <&bch>;
  54 +               #address-cells = <1>;
  55 +               #size-cells = <0>;
  56 +        };
  57 +
  58 +Platform related properties, should be set in {platform_name}.dts:
  59 +- children nodes:      NAND chips.
  60 +
  61 +Children nodes properties:
  62 +- reg:                 Chip Select Signal, default 0.
  63 +                       Set as reg = <0>, <1> when need 2 CS.
  64 +Optional:
  65 +- nand-on-flash-bbt:   Store BBT on NAND Flash.
  66 +- nand-ecc-mode:       the NAND ecc mode (check driver for supported modes)
  67 +- nand-ecc-step-size:  Number of data bytes covered by a single ECC step.
  68 +                       The controller only supports 512 and 1024.
  69 +                       For large page NANDs ther recommended value is 1024.
  70 +- nand-ecc-strength:   Number of bits to correct per ECC step.
  71 +                       The valid values that the controller supports are: 4, 6,
  72 +                       8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
  73 +                       48, 52, 56, 60.
  74 +                       The strength should be calculated as follows:
  75 +                       E = (S - F) * 8 / 14
  76 +                       S = O / (P / Q)
  77 +                               E :nand-ecc-strength;
  78 +                               S :spare size per sector;
  79 +                               F : FDM size, should be in the range [1,8].
  80 +                                   It is used to store free oob data.
  81 +                               O : oob size;
  82 +                               P : page size;
  83 +                               Q :nand-ecc-step-size
  84 +                       If the result does not match any one of the listed
  85 +                       choices above, please select the smaller valid value from
  86 +                       the list.
  87 +                       (otherwise the driver will do the clamping at runtime).
  88 +- vmch-supply:         NAND power supply.
  89 +- pinctrl-names:       Default NAND pin GPIO setting name.
  90 +- pinctrl-0:           GPIO setting node.
  91 +
  92 +Example:
  93 +       &pio {
  94 +               nand_pins_default: nanddefault {
  95 +                       pins_dat {
  96 +                               pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
  97 +                                        <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
  98 +                                        <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
  99 +                                        <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
 100 +                                        <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
 101 +                                        <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
 102 +                                        <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
 103 +                                        <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
 104 +                                        <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
 105 +                               input-enable;
 106 +                               drive-strength = <MTK_DRIVE_8mA>;
 107 +                               bias-pull-up;
 108 +                       };
 109 +
 110 +                       pins_we {
 111 +                               pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
 112 +                               drive-strength = <MTK_DRIVE_8mA>;
 113 +                               bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 114 +                       };
 115 +
 116 +                       pins_ale {
 117 +                               pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
 118 +                               drive-strength = <MTK_DRIVE_8mA>;
 119 +                               bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 120 +                       };
 121 +               };
 122 +       };
 123 +
 124 +       &nandc {
 125 +               status = "okay";
 126 +               pinctrl-names = "default";
 127 +               pinctrl-0 = <&nand_pins_default>;
 128 +               nand@0 {
 129 +                       reg = <0>;
 130 +                       nand-on-flash-bbt;
 131 +                       nand-ecc-mode = "hw";
 132 +                       nand-ecc-strength = <24>;
 133 +                       nand-ecc-step-size = <1024>;
 134 +               };
 135 +       };
 136 +
 137 +NAND chip optional subnodes:
 138 +- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
 139 +
 140 +Example:
 141 +       nand@0 {
 142 +               partitions {
 143 +                       compatible = "fixed-partitions";
 144 +                       #address-cells = <1>;
 145 +                       #size-cells = <1>;
 146 +
 147 +                       preloader@0 {
 148 +                               label = "pl";
 149 +                               read-only;
 150 +                               reg = <0x00000000 0x00400000>;
 151 +                       };
 152 +                       android@0x00400000 {
 153 +                               label = "android";
 154 +                               reg = <0x00400000 0x12c00000>;
 155 +                       };
 156 +               };
 157 +       };
 158 +
 159 +2) ECC Engine:
 160 +==============
 161 +
 162 +Required BCH properties:
 163 +- compatible:  Should be "mediatek,mtxxxx-ecc".
 164 +- reg:         Base physical address and size of ECC.
 165 +- interrupts:  Interrupts of ECC.
 166 +- clocks:      ECC required clocks.
 167 +- clock-names: ECC clocks internal name.
 168 +- status:      Disabled default. Then set "okay" by platform.
 169 +
 170 +Example:
 171 +
 172 +       bch: ecc@1100e000 {
 173 +               compatible = "mediatek,mt2701-ecc";
 174 +               reg = <0 0x1100e000 0 0x1000>;
 175 +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 176 +               clocks = <&pericfg CLK_PERI_NFI_ECC>;
 177 +               clock-names = "nfiecc_clk";
 178 +               status = "disabled";
 179 +       };