target/linux/mediatek/patches-4.4/0071-pwm-add-pwm-mediatek.patch

   1 From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Fri, 6 May 2016 02:55:48 +0200
   4 Subject: [PATCH 071/102] pwm: add pwm-mediatek
   5
   6 Signed-off-by: John Crispin <john@phrozen.org>
   7 ---
   8  arch/arm/boot/dts/mt7623-evb.dts |   17 +++
   9  arch/arm/boot/dts/mt7623.dtsi    |   22 ++++
  10  drivers/pwm/Kconfig              |    9 ++
  11  drivers/pwm/Makefile             |    1 +
  12  drivers/pwm/pwm-mediatek.c       |  230 ++++++++++++++++++++++++++++++++++++++
  13  5 files changed, 279 insertions(+)
  14  create mode 100644 drivers/pwm/pwm-mediatek.c
  15
  16 --- a/arch/arm/boot/dts/mt7623-evb.dts
  17 +++ b/arch/arm/boot/dts/mt7623-evb.dts
  18 @@ -341,6 +341,17 @@
  19                         output-low;
  20                 };
  21         };
  22 +
  23 +       pwm_pins: pwm {
  24 +               pins_pwm1 {
  25 +                       pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
  26 +               };
  27 +
  28 +               pins_pwm2 {
  29 +                       pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
  30 +               };
  31 +       };
  32 +
  33  };
  34
  35  &nandc {
  36 @@ -419,3 +430,9 @@
  37         mediatek,reset-pin = <&pio 15 0>;
  38         status = "okay";
  39  };
  40 +
  41 +&pwm {
  42 +       pinctrl-names = "default";
  43 +       pinctrl-0 = <&pwm_pins>;
  44 +       status = "okay";
  45 +};
  46 --- a/arch/arm/boot/dts/mt7623.dtsi
  47 +++ b/arch/arm/boot/dts/mt7623.dtsi
  48 @@ -324,6 +324,28 @@
  49                 status = "disabled";
  50         };
  51
  52 +       pwm: pwm@11006000 {
  53 +               compatible = "mediatek,mt7623-pwm";
  54 +
  55 +               reg = <0 0x11006000 0 0x1000>;
  56 +
  57 +               resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
  58 +               reset-names = "pwm";
  59 +
  60 +               #pwm-cells = <2>;
  61 +               clocks = <&topckgen CLK_TOP_PWM_SEL>,
  62 +                        <&pericfg CLK_PERI_PWM>,
  63 +                        <&pericfg CLK_PERI_PWM1>,
  64 +                        <&pericfg CLK_PERI_PWM2>,
  65 +                        <&pericfg CLK_PERI_PWM3>,
  66 +                        <&pericfg CLK_PERI_PWM4>,
  67 +                        <&pericfg CLK_PERI_PWM5>;
  68 +               clock-names = "top", "main", "pwm1", "pwm2",
  69 +                             "pwm3", "pwm4", "pwm5";
  70 +
  71 +               status = "disabled";
  72 +       };
  73 +
  74         spi: spi@1100a000 {
  75                 compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
  76                 reg = <0 0x1100a000 0 0x1000>;
  77 --- a/drivers/pwm/Kconfig
  78 +++ b/drivers/pwm/Kconfig
  79 @@ -260,6 +260,15 @@ config PWM_MTK_DISP
  80           To compile this driver as a module, choose M here: the module
  81           will be called pwm-mtk-disp.
  82
  83 +config PWM_MEDIATEK
  84 +       tristate "MediaTek PWM support"
  85 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  86 +       help
  87 +         Generic PWM framework driver for Mediatek ARM SoC.
  88 +
  89 +         To compile this driver as a module, choose M here: the module
  90 +         will be called pwm-mxs.
  91 +
  92  config PWM_MXS
  93         tristate "Freescale MXS PWM support"
  94         depends on ARCH_MXS && OF
  95 --- a/drivers/pwm/Makefile
  96 +++ b/drivers/pwm/Makefile
  97 @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_LPC32XX)     += pwm-lpc32xx
  98  obj-$(CONFIG_PWM_LPSS)         += pwm-lpss.o
  99  obj-$(CONFIG_PWM_LPSS_PCI)     += pwm-lpss-pci.o
 100  obj-$(CONFIG_PWM_LPSS_PLATFORM)        += pwm-lpss-platform.o
 101 +obj-$(CONFIG_PWM_MEDIATEK)     += pwm-mediatek.o
 102  obj-$(CONFIG_PWM_MTK_DISP)     += pwm-mtk-disp.o
 103  obj-$(CONFIG_PWM_MXS)          += pwm-mxs.o
 104  obj-$(CONFIG_PWM_PCA9685)      += pwm-pca9685.o
 105 --- /dev/null
 106 +++ b/drivers/pwm/pwm-mediatek.c
 107 @@ -0,0 +1,230 @@
 108 +/*
 109 + * Mediatek Pulse Width Modulator driver
 110 + *
 111 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
 112 + *
 113 + * This file is licensed under the terms of the GNU General Public
 114 + * License version 2. This program is licensed "as is" without any
 115 + * warranty of any kind, whether express or implied.
 116 + */
 117 +
 118 +#include <linux/err.h>
 119 +#include <linux/io.h>
 120 +#include <linux/ioport.h>
 121 +#include <linux/kernel.h>
 122 +#include <linux/module.h>
 123 +#include <linux/clk.h>
 124 +#include <linux/of.h>
 125 +#include <linux/platform_device.h>
 126 +#include <linux/pwm.h>
 127 +#include <linux/slab.h>
 128 +#include <linux/types.h>
 129 +
 130 +#define NUM_PWM                5
 131 +
 132 +/* PWM registers and bits definitions */
 133 +#define PWMCON                 0x00
 134 +#define PWMHDUR                        0x04
 135 +#define PWMLDUR                        0x08
 136 +#define PWMGDUR                        0x0c
 137 +#define PWMWAVENUM             0x28
 138 +#define PWMDWIDTH              0x2c
 139 +#define PWMTHRES               0x30
 140 +
 141 +/**
 142 + * struct mtk_pwm_chip - struct representing pwm chip
 143 + *
 144 + * @mmio_base: base address of pwm chip
 145 + * @chip: linux pwm chip representation
 146 + */
 147 +struct mtk_pwm_chip {
 148 +       void __iomem *mmio_base;
 149 +       struct pwm_chip chip;
 150 +       struct clk *clk_top;
 151 +       struct clk *clk_main;
 152 +       struct clk *clk_pwm[NUM_PWM];
 153 +};
 154 +
 155 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
 156 +{
 157 +       return container_of(chip, struct mtk_pwm_chip, chip);
 158 +}
 159 +
 160 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
 161 +                                 unsigned long offset)
 162 +{
 163 +       return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
 164 +}
 165 +
 166 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
 167 +                                   unsigned int num, unsigned long offset,
 168 +                                   unsigned long val)
 169 +{
 170 +       iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
 171 +}
 172 +
 173 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 174 +                           int duty_ns, int period_ns)
 175 +{
 176 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 177 +       u32 resolution = 100 / 4;
 178 +       u32 clkdiv = 0;
 179 +
 180 +       resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
 181 +
 182 +       while (period_ns / resolution  > 8191) {
 183 +               clkdiv++;
 184 +               resolution *= 2;
 185 +       }
 186 +
 187 +       if (clkdiv > 7)
 188 +               return -1;
 189 +
 190 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
 191 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 192 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
 193 +       return 0;
 194 +}
 195 +
 196 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 197 +{
 198 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 199 +       u32 val;
 200 +       int ret;
 201 +
 202 +       ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
 203 +       if (ret < 0)
 204 +               return ret;
 205 +
 206 +       val = ioread32(pc->mmio_base);
 207 +       val |= BIT(pwm->hwpwm);
 208 +       iowrite32(val, pc->mmio_base);
 209 +
 210 +       return 0;
 211 +}
 212 +
 213 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 214 +{
 215 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 216 +       u32 val;
 217 +
 218 +       val = ioread32(pc->mmio_base);
 219 +       val &= ~BIT(pwm->hwpwm);
 220 +       iowrite32(val, pc->mmio_base);
 221 +        clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
 222 +}
 223 +
 224 +static const struct pwm_ops mtk_pwm_ops = {
 225 +       .config = mtk_pwm_config,
 226 +       .enable = mtk_pwm_enable,
 227 +       .disable = mtk_pwm_disable,
 228 +       .owner = THIS_MODULE,
 229 +};
 230 +
 231 +static int mtk_pwm_probe(struct platform_device *pdev)
 232 +{
 233 +       struct mtk_pwm_chip *pc;
 234 +       struct resource *r;
 235 +       int ret;
 236 +
 237 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 238 +       if (!pc)
 239 +               return -ENOMEM;
 240 +
 241 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 242 +       pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 243 +       if (IS_ERR(pc->mmio_base))
 244 +               return PTR_ERR(pc->mmio_base);
 245 +
 246 +       pc->clk_main = devm_clk_get(&pdev->dev, "main");
 247 +        if (IS_ERR(pc->clk_main))
 248 +               return PTR_ERR(pc->clk_main);
 249 +
 250 +       pc->clk_top = devm_clk_get(&pdev->dev, "top");
 251 +        if (IS_ERR(pc->clk_top))
 252 +               return PTR_ERR(pc->clk_top);
 253 +
 254 +       pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
 255 +        if (IS_ERR(pc->clk_pwm[0]))
 256 +               return PTR_ERR(pc->clk_pwm[0]);
 257 +
 258 +       pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
 259 +        if (IS_ERR(pc->clk_pwm[1]))
 260 +               return PTR_ERR(pc->clk_pwm[1]);
 261 +
 262 +       pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
 263 +        if (IS_ERR(pc->clk_pwm[2]))
 264 +               return PTR_ERR(pc->clk_pwm[2]);
 265 +
 266 +       pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
 267 +        if (IS_ERR(pc->clk_pwm[3]))
 268 +               return PTR_ERR(pc->clk_pwm[3]);
 269 +
 270 +       pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
 271 +        if (IS_ERR(pc->clk_pwm[4]))
 272 +               return PTR_ERR(pc->clk_pwm[4]);
 273 +
 274 +       ret = clk_prepare(pc->clk_top);
 275 +        if (ret < 0)
 276 +               return ret;
 277 +
 278 +       ret = clk_prepare(pc->clk_main);
 279 +       if (ret < 0)
 280 +               goto disable_clk_top;
 281 +
 282 +       platform_set_drvdata(pdev, pc);
 283 +
 284 +       pc->chip.dev = &pdev->dev;
 285 +       pc->chip.ops = &mtk_pwm_ops;
 286 +       pc->chip.base = -1;
 287 +       pc->chip.npwm = NUM_PWM;
 288 +
 289 +       ret = pwmchip_add(&pc->chip);
 290 +       if (ret < 0) {
 291 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 292 +               goto disable_clk_main;
 293 +       }
 294 +
 295 +       return 0;
 296 +
 297 +disable_clk_main:
 298 +       clk_unprepare(pc->clk_main);
 299 +disable_clk_top:
 300 +       clk_unprepare(pc->clk_top);
 301 +
 302 +       return ret;
 303 +}
 304 +
 305 +static int mtk_pwm_remove(struct platform_device *pdev)
 306 +{
 307 +       struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
 308 +       int i;
 309 +
 310 +       for (i = 0; i < NUM_PWM; i++)
 311 +               pwm_disable(&pc->chip.pwms[i]);
 312 +
 313 +       return pwmchip_remove(&pc->chip);
 314 +}
 315 +
 316 +static const struct of_device_id mtk_pwm_of_match[] = {
 317 +       { .compatible = "mediatek,mt7623-pwm" },
 318 +       { }
 319 +};
 320 +
 321 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
 322 +
 323 +static struct platform_driver mtk_pwm_driver = {
 324 +       .driver = {
 325 +               .name = "mtk-pwm",
 326 +               .owner = THIS_MODULE,
 327 +               .of_match_table = mtk_pwm_of_match,
 328 +       },
 329 +       .probe = mtk_pwm_probe,
 330 +       .remove = mtk_pwm_remove,
 331 +};
 332 +
 333 +module_platform_driver(mtk_pwm_driver);
 334 +
 335 +MODULE_LICENSE("GPL");
 336 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 337 +MODULE_ALIAS("platform:mtk-pwm");