target/linux/mediatek/patches-4.4/0053-clk-mediatek-enable-critical-clocks.patch

   1 From c8fd103d6c07af5db47f061b70759b7c69169656 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 31 Mar 2016 06:46:51 +0200
   4 Subject: [PATCH 053/102] clk: mediatek: enable critical clocks
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/clk/mediatek/clk-mt2701.c |   22 ++++++++++++++++++++--
   9  1 file changed, 20 insertions(+), 2 deletions(-)
  10
  11 --- a/drivers/clk/mediatek/clk-mt2701.c
  12 +++ b/drivers/clk/mediatek/clk-mt2701.c
  13 @@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[]
  14         GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
  15  };
  16
  17 +static struct clk_onecell_data *mt7623_top_clk_data __initdata;
  18 +static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
  19 +
  20 +static void __init mtk_clk_enable_critical(void)
  21 +{
  22 +       if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
  23 +               return;
  24 +
  25 +       clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
  26 +       clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
  27 +       clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
  28 +       clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
  29 +}
  30 +
  31  static void __init mtk_topckgen_init(struct device_node *node)
  32  {
  33         struct clk_onecell_data *clk_data;
  34 @@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(str
  35                 return;
  36         }
  37
  38 -       clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
  39 +       mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
  40
  41         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  42                                                                 clk_data);
  43 @@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(str
  44         if (r)
  45                 pr_err("%s(): could not register clock provider: %d\n",
  46                         __func__, r);
  47 +
  48 +       mtk_clk_enable_critical();
  49  }
  50  CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
  51
  52 @@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(s
  53         struct clk_onecell_data *clk_data;
  54         int r;
  55
  56 -       clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
  57 +       mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
  58         if (!clk_data)
  59                 return;
  60
  61 @@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(s
  62         if (r)
  63                 pr_err("%s(): could not register clock provider: %d\n",
  64                         __func__, r);
  65 +
  66 +       mtk_clk_enable_critical();
  67  }
  68  CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
  69                                                         mtk_apmixedsys_init);