target/linux/mediatek/patches-4.4/0041-soc-mediatek-PMIC-wrap-add-MT2701-7623-support.patch

   1 From 7736d97fe2c6c71c9009a1b45a94de06bfc94a37 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 20 Jan 2016 12:09:14 +0100
   4 Subject: [PATCH 041/102] soc: mediatek: PMIC wrap: add MT2701/7623 support
   5
   6 Add the registers, callbacks and data structures required to make the
   7 wrapper work on MT2701 and MT7623.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/soc/mediatek/mtk-pmic-wrap.c |  154 ++++++++++++++++++++++++++++++++++
  12  1 file changed, 154 insertions(+)
  13
  14 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
  15 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
  16 @@ -52,6 +52,7 @@
  17  #define PWRAP_DEW_WRITE_TEST_VAL       0xa55a
  18
  19  /* macro for manual command */
  20 +#define PWRAP_MAN_CMD_SPI_WRITE_NEW    (1 << 14)
  21  #define PWRAP_MAN_CMD_SPI_WRITE                (1 << 13)
  22  #define PWRAP_MAN_CMD_OP_CSH           (0x0 << 8)
  23  #define PWRAP_MAN_CMD_OP_CSL           (0x1 << 8)
  24 @@ -200,6 +201,13 @@ enum pwrap_regs {
  25         PWRAP_DCM_EN,
  26         PWRAP_DCM_DBC_PRD,
  27
  28 +       /* MT2701 only regs */
  29 +       PWRAP_ADC_CMD_ADDR,
  30 +       PWRAP_PWRAP_ADC_CMD,
  31 +       PWRAP_ADC_RDY_ADDR,
  32 +       PWRAP_ADC_RDATA_ADDR1,
  33 +       PWRAP_ADC_RDATA_ADDR2,
  34 +
  35         /* MT8135 only regs */
  36         PWRAP_CSHEXT,
  37         PWRAP_EVENT_IN_EN,
  38 @@ -236,6 +244,92 @@ enum pwrap_regs {
  39         PWRAP_CIPHER_EN,
  40  };
  41
  42 +static int mt2701_regs[] = {
  43 +       [PWRAP_MUX_SEL] =               0x0,
  44 +       [PWRAP_WRAP_EN] =               0x4,
  45 +       [PWRAP_DIO_EN] =                0x8,
  46 +       [PWRAP_SIDLY] =                 0xc,
  47 +       [PWRAP_RDDMY] =                 0x18,
  48 +       [PWRAP_SI_CK_CON] =             0x1c,
  49 +       [PWRAP_CSHEXT_WRITE] =          0x20,
  50 +       [PWRAP_CSHEXT_READ] =           0x24,
  51 +       [PWRAP_CSLEXT_START] =          0x28,
  52 +       [PWRAP_CSLEXT_END] =            0x2c,
  53 +       [PWRAP_STAUPD_PRD] =            0x30,
  54 +       [PWRAP_STAUPD_GRPEN] =          0x34,
  55 +       [PWRAP_STAUPD_MAN_TRIG] =       0x38,
  56 +       [PWRAP_STAUPD_STA] =            0x3c,
  57 +       [PWRAP_WRAP_STA] =              0x44,
  58 +       [PWRAP_HARB_INIT] =             0x48,
  59 +       [PWRAP_HARB_HPRIO] =            0x4c,
  60 +       [PWRAP_HIPRIO_ARB_EN] =         0x50,
  61 +       [PWRAP_HARB_STA0] =             0x54,
  62 +       [PWRAP_HARB_STA1] =             0x58,
  63 +       [PWRAP_MAN_EN] =                0x5c,
  64 +       [PWRAP_MAN_CMD] =               0x60,
  65 +       [PWRAP_MAN_RDATA] =             0x64,
  66 +       [PWRAP_MAN_VLDCLR] =            0x68,
  67 +       [PWRAP_WACS0_EN] =              0x6c,
  68 +       [PWRAP_INIT_DONE0] =            0x70,
  69 +       [PWRAP_WACS0_CMD] =             0x74,
  70 +       [PWRAP_WACS0_RDATA] =           0x78,
  71 +       [PWRAP_WACS0_VLDCLR] =          0x7c,
  72 +       [PWRAP_WACS1_EN] =              0x80,
  73 +       [PWRAP_INIT_DONE1] =            0x84,
  74 +       [PWRAP_WACS1_CMD] =             0x88,
  75 +       [PWRAP_WACS1_RDATA] =           0x8c,
  76 +       [PWRAP_WACS1_VLDCLR] =          0x90,
  77 +       [PWRAP_WACS2_EN] =              0x94,
  78 +       [PWRAP_INIT_DONE2] =            0x98,
  79 +       [PWRAP_WACS2_CMD] =             0x9c,
  80 +       [PWRAP_WACS2_RDATA] =           0xa0,
  81 +       [PWRAP_WACS2_VLDCLR] =          0xa4,
  82 +       [PWRAP_INT_EN] =                0xa8,
  83 +       [PWRAP_INT_FLG_RAW] =           0xac,
  84 +       [PWRAP_INT_FLG] =               0xb0,
  85 +       [PWRAP_INT_CLR] =               0xb4,
  86 +       [PWRAP_SIG_ADR] =               0xb8,
  87 +       [PWRAP_SIG_MODE] =              0xbc,
  88 +       [PWRAP_SIG_VALUE] =             0xc0,
  89 +       [PWRAP_SIG_ERRVAL] =            0xc4,
  90 +       [PWRAP_CRC_EN] =                0xc8,
  91 +       [PWRAP_TIMER_EN] =              0xcc,
  92 +       [PWRAP_TIMER_STA] =             0xd0,
  93 +       [PWRAP_WDT_UNIT] =              0xd4,
  94 +       [PWRAP_WDT_SRC_EN] =            0xd8,
  95 +       [PWRAP_WDT_FLG] =               0xdc,
  96 +       [PWRAP_DEBUG_INT_SEL] =         0xe0,
  97 +       [PWRAP_DVFS_ADR0] =             0xe4,
  98 +       [PWRAP_DVFS_WDATA0] =           0xe8,
  99 +       [PWRAP_DVFS_ADR1] =             0xec,
 100 +       [PWRAP_DVFS_WDATA1] =           0xf0,
 101 +       [PWRAP_DVFS_ADR2] =             0xf4,
 102 +       [PWRAP_DVFS_WDATA2] =           0xf8,
 103 +       [PWRAP_DVFS_ADR3] =             0xfc,
 104 +       [PWRAP_DVFS_WDATA3] =           0x100,
 105 +       [PWRAP_DVFS_ADR4] =             0x104,
 106 +       [PWRAP_DVFS_WDATA4] =           0x108,
 107 +       [PWRAP_DVFS_ADR5] =             0x10c,
 108 +       [PWRAP_DVFS_WDATA5] =           0x110,
 109 +       [PWRAP_DVFS_ADR6] =             0x114,
 110 +       [PWRAP_DVFS_WDATA6] =           0x118,
 111 +       [PWRAP_DVFS_ADR7] =             0x11c,
 112 +       [PWRAP_DVFS_WDATA7] =           0x120,
 113 +       [PWRAP_CIPHER_KEY_SEL] =        0x124,
 114 +       [PWRAP_CIPHER_IV_SEL] =         0x128,
 115 +       [PWRAP_CIPHER_EN] =             0x12c,
 116 +       [PWRAP_CIPHER_RDY] =            0x130,
 117 +       [PWRAP_CIPHER_MODE] =           0x134,
 118 +       [PWRAP_CIPHER_SWRST] =          0x138,
 119 +       [PWRAP_DCM_EN] =                0x13c,
 120 +       [PWRAP_DCM_DBC_PRD] =           0x140,
 121 +       [PWRAP_ADC_CMD_ADDR] =          0x144,
 122 +       [PWRAP_PWRAP_ADC_CMD] =         0x148,
 123 +       [PWRAP_ADC_RDY_ADDR] =          0x14c,
 124 +       [PWRAP_ADC_RDATA_ADDR1] =       0x150,
 125 +       [PWRAP_ADC_RDATA_ADDR2] =       0x154,
 126 +};
 127 +
 128  static int mt8173_regs[] = {
 129         [PWRAP_MUX_SEL] =               0x0,
 130         [PWRAP_WRAP_EN] =               0x4,
 131 @@ -397,6 +491,7 @@ enum pmic_type {
 132  };
 133
 134  enum pwrap_type {
 135 +       PWRAP_MT2701,
 136         PWRAP_MT8135,
 137         PWRAP_MT8173,
 138  };
 139 @@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(s
 140         return 0;
 141  }
 142
 143 +static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
 144 +{
 145 +       switch (wrp->slave->type) {
 146 +       case PMIC_MT6397:
 147 +               pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
 148 +               pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
 149 +               pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
 150 +               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
 151 +               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
 152 +               break;
 153 +
 154 +       case PMIC_MT6323:
 155 +               pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
 156 +               pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
 157 +                           0x8);
 158 +               pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
 159 +               pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
 160 +               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
 161 +               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
 162 +               break;
 163 +       }
 164 +
 165 +       return 0;
 166 +}
 167 +
 168  static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
 169  {
 170         return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
 171 @@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic
 172                 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
 173                 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
 174                 break;
 175 +       case PWRAP_MT2701:
 176         case PWRAP_MT8173:
 177                 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
 178                 break;
 179 @@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specifi
 180         return 0;
 181  }
 182
 183 +static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
 184 +{
 185 +       /* GPS_INTF initialization */
 186 +       switch (wrp->slave->type) {
 187 +       case PMIC_MT6323:
 188 +               pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
 189 +               pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
 190 +               pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
 191 +               pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
 192 +               pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
 193 +               break;
 194 +       default:
 195 +               break;
 196 +       }
 197 +
 198 +       return 0;
 199 +}
 200 +
 201  static int pwrap_init(struct pmic_wrapper *wrp)
 202  {
 203         int ret;
 204 @@ -916,6 +1055,18 @@ static const struct of_device_id of_slav
 205  };
 206  MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
 207
 208 +static const struct pmic_wrapper_type pwrap_mt2701 = {
 209 +       .regs = mt2701_regs,
 210 +       .type = PWRAP_MT2701,
 211 +       .arb_en_all = 0x3f,
 212 +       .int_en_all = ~(BIT(31) | BIT(2)),
 213 +       .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
 214 +       .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
 215 +       .has_bridge = 0,
 216 +       .init_reg_clock = pwrap_mt2701_init_reg_clock,
 217 +       .init_soc_specific = pwrap_mt2701_init_soc_specific,
 218 +};
 219 +
 220  static struct pmic_wrapper_type pwrap_mt8135 = {
 221         .regs = mt8135_regs,
 222         .type = PWRAP_MT8135,
 223 @@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt
 224
 225  static struct of_device_id of_pwrap_match_tbl[] = {
 226         {
 227 +               .compatible = "mediatek,mt2701-pwrap",
 228 +               .data = &pwrap_mt2701,
 229 +       }, {
 230                 .compatible = "mediatek,mt8135-pwrap",
 231                 .data = &pwrap_mt8135,
 232         }, {