target/linux/mediatek/patches-4.4/0026-scpsys-various-fixes.patch

   1 From 59aafd667d2880c90776931b6102b8252214d93c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 21 Feb 2016 13:52:12 +0100
   4 Subject: [PATCH 026/102] scpsys: various fixes
   5
   6 ---
   7  drivers/clk/mediatek/clk-mt2701.c        |    2 ++
   8  drivers/soc/mediatek/mtk-scpsys-mt2701.c |    8 --------
   9  include/dt-bindings/power/mt2701-power.h |    4 ++--
  10  3 files changed, 4 insertions(+), 10 deletions(-)
  11
  12 --- a/drivers/clk/mediatek/clk-mt2701.c
  13 +++ b/drivers/clk/mediatek/clk-mt2701.c
  14 @@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struc
  15         if (r)
  16                 pr_err("%s(): could not register clock provider: %d\n",
  17                         __func__, r);
  18 +
  19 +       mtk_register_reset_controller(node, 1, 0x34);
  20  }
  21  CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt2701-ethsys", mtk_ethsys_init);
  22
  23 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
  24 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
  25 @@ -61,14 +61,6 @@ static const struct scp_domain_data scp_
  26                 .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
  27                 .active_wakeup = true,
  28         },
  29 -       [MT2701_POWER_DOMAIN_MFG] = {
  30 -               .name = "mfg",
  31 -               .sta_mask = MFG_PWR_STA_MASK,
  32 -               .ctl_offs = SPM_MFG_PWR_CON,
  33 -               .sram_pdn_bits = GENMASK(11, 8),
  34 -               .sram_pdn_ack_bits = GENMASK(12, 12),
  35 -               .active_wakeup = true,
  36 -       },
  37         [MT2701_POWER_DOMAIN_VDEC] = {
  38                 .name = "vdec",
  39                 .sta_mask = VDE_PWR_STA_MASK,
  40 --- a/include/dt-bindings/power/mt2701-power.h
  41 +++ b/include/dt-bindings/power/mt2701-power.h
  42 @@ -16,12 +16,12 @@
  43
  44  #define MT2701_POWER_DOMAIN_CONN       0
  45  #define MT2701_POWER_DOMAIN_DISP       1
  46 -#define MT2701_POWER_DOMAIN_MFG                2
  47 +//#define MT2701_POWER_DOMAIN_MFG              2
  48  #define MT2701_POWER_DOMAIN_VDEC       3
  49  #define MT2701_POWER_DOMAIN_ISP                4
  50  #define MT2701_POWER_DOMAIN_BDP                5
  51  #define MT2701_POWER_DOMAIN_ETH                6
  52  #define MT2701_POWER_DOMAIN_HIF                7
  53 -#define MT2701_POWER_DOMAIN_IFR_MSC    8
  54 +#define MT2701_POWER_DOMAIN_IFR_MSC    2
  55
  56  #endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */