1 From 28ec0b7e48bb27435a8b3134019b88628faf497f Mon Sep 17 00:00:00 2001
2 From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
3 Date: Tue, 11 Dec 2018 17:37:28 +0800
4 Subject: [PATCH 4/6] dt-bindings: ARM: MediaTek: Document devicetree bindings
7 Change-Id: I9ece142055ae27100da95826fb3ea1960c2994e6
8 Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
10 .../devicetree/bindings/spi/spi-mtk-snfi.txt | 44 +++++++++++++++++++
11 1 file changed, 44 insertions(+)
12 create mode 100644 Documentation/devicetree/bindings/spi/spi-mtk-snfi.txt
15 +++ b/Documentation/devicetree/bindings/spi/spi-mtk-snfi.txt
17 +MediaTek SoCs SPI NAND FLASH interface (SNFI) DT binding
19 +This file documents the device tree bindings for MTK SoCs SPI NAND controller.
20 +Note that Parallel Nand and SPI NAND is alternative on MTK SoCs.
23 +- compatible: should be "mediatek,mt7622-snfi"
24 +- reg: base physical address and size of SNFI.
25 +- interrupts: interrupts of SNFI.
26 +- clocks: SNFI required clocks.
27 +- clock-names: SNFI clocks internal names.
28 +- #address-cells: NAND chip index, should be 1.
29 +- #size-cells: Should be 0.
32 + snfi: spi@1100d000 {
33 + compatible = "mediatek,mt7622-snfi";
34 + reg = <0 0x1100d000 0 0x1000>;
35 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
36 + clocks = <&pericfg CLK_PERI_NFI_PD>,
37 + <&pericfg CLK_PERI_SNFI_PD>;
38 + clock-names = "nfi_clk", "spi_clk";
39 + ecc-engine = <&bch>;
40 + #address-cells = <1>;
45 +- Should use spi-nand framework, see Documentation/devicetree/bindings/mtd/spi-nand.txt
49 + pinctrl-names = "default";
50 + pinctrl-0 = <&serial_nand_pins>;
54 + #address-cells = <1>;
56 + compatible = "spi-nand";
57 + spi-max-frequency = <104000000>;