target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch

   1 From d41d41bfcbd8ad4bcbb1b433f7d5c3b613c58419 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Mon, 22 Jan 2018 16:58:36 +0800
   4 Subject: [PATCH 223/224] arm64: dts: mt7622: add mmc related device nodes
   5
   6 add mmc device nodes and proper setup for used pins
   7
   8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
   9 Signed-off-by: Jimin Wang <jimin.wang@mediatek.com>
  10 ---
  11  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 106 +++++++++++++++++++++++++++
  12  arch/arm64/boot/dts/mediatek/mt7622.dtsi     |  20 +++++
  13  2 files changed, 126 insertions(+)
  14
  15 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  16 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  17 @@ -8,6 +8,7 @@
  18
  19  /dts-v1/;
  20  #include <dt-bindings/input/input.h>
  21 +#include <dt-bindings/gpio/gpio.h>
  22
  23  #include "mt7622.dtsi"
  24  #include "mt6380.dtsi"
  25 @@ -53,6 +54,14 @@
  26                 reg = <0 0x40000000 0 0x3F000000>;
  27         };
  28
  29 +       reg_1p8v: regulator-1p8v {
  30 +               compatible = "regulator-fixed";
  31 +               regulator-name = "fixed-1.8V";
  32 +               regulator-min-microvolt = <1800000>;
  33 +               regulator-max-microvolt = <1800000>;
  34 +               regulator-always-on;
  35 +       };
  36 +
  37         reg_3p3v: regulator-3p3v {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "fixed-3.3V";
  40 @@ -89,6 +98,23 @@
  41                         function = "emmc", "emmc_rst";
  42                         groups = "emmc";
  43                 };
  44 +
  45 +               /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
  46 +                * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
  47 +                * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
  48 +                */
  49 +               conf-cmd-dat {
  50 +                       pins = "NDL0", "NDL1", "NDL2",
  51 +                              "NDL3", "NDL4", "NDL5",
  52 +                              "NDL6", "NDL7", "NRB";
  53 +                       input-enable;
  54 +                       bias-pull-up;
  55 +               };
  56 +
  57 +               conf-clk {
  58 +                       pins = "NCLE";
  59 +                       bias-pull-down;
  60 +               };
  61         };
  62
  63         emmc_pins_uhs: emmc-pins-uhs {
  64 @@ -96,6 +122,21 @@
  65                         function = "emmc";
  66                         groups = "emmc";
  67                 };
  68 +
  69 +               conf-cmd-dat {
  70 +                       pins = "NDL0", "NDL1", "NDL2",
  71 +                              "NDL3", "NDL4", "NDL5",
  72 +                              "NDL6", "NDL7", "NRB";
  73 +                       input-enable;
  74 +                       drive-strength = <4>;
  75 +                       bias-pull-up;
  76 +               };
  77 +
  78 +               conf-clk {
  79 +                       pins = "NCLE";
  80 +                       drive-strength = <4>;
  81 +                       bias-pull-down;
  82 +               };
  83         };
  84
  85         eth_pins: eth-pins {
  86 @@ -194,6 +235,27 @@
  87                         function = "sd";
  88                         groups = "sd_0";
  89                 };
  90 +
  91 +               /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
  92 +                *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
  93 +                *  DAT2, DAT3, CMD, CLK for SD respectively.
  94 +                */
  95 +               conf-cmd-data {
  96 +                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
  97 +                              "I2S2_IN","I2S4_OUT";
  98 +                       input-enable;
  99 +                       drive-strength = <8>;
 100 +                       bias-pull-up;
 101 +               };
 102 +               conf-clk {
 103 +                       pins = "I2S3_OUT";
 104 +                       drive-strength = <12>;
 105 +                       bias-pull-down;
 106 +               };
 107 +               conf-cd {
 108 +                       pins = "TXD3";
 109 +                       bias-pull-up;
 110 +               };
 111         };
 112
 113         sd0_pins_uhs: sd0-pins-uhs {
 114 @@ -201,6 +263,18 @@
 115                         function = "sd";
 116                         groups = "sd_0";
 117                 };
 118 +
 119 +               conf-cmd-data {
 120 +                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 121 +                              "I2S2_IN","I2S4_OUT";
 122 +                       input-enable;
 123 +                       bias-pull-up;
 124 +               };
 125 +
 126 +               conf-clk {
 127 +                       pins = "I2S3_OUT";
 128 +                       bias-pull-down;
 129 +               };
 130         };
 131
 132         /* Serial NAND is shared pin with SPI-NOR */
 133 @@ -311,6 +385,38 @@
 134         status = "okay";
 135  };
 136
 137 +&mmc0 {
 138 +       pinctrl-names = "default", "state_uhs";
 139 +       pinctrl-0 = <&emmc_pins_default>;
 140 +       pinctrl-1 = <&emmc_pins_uhs>;
 141 +       status = "okay";
 142 +       bus-width = <8>;
 143 +       max-frequency = <50000000>;
 144 +       cap-mmc-highspeed;
 145 +       mmc-hs200-1_8v;
 146 +       vmmc-supply = <&reg_3p3v>;
 147 +       vqmmc-supply = <&reg_1p8v>;
 148 +       assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 149 +       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 150 +       non-removable;
 151 +};
 152 +
 153 +&mmc1 {
 154 +       pinctrl-names = "default", "state_uhs";
 155 +       pinctrl-0 = <&sd0_pins_default>;
 156 +       pinctrl-1 = <&sd0_pins_uhs>;
 157 +       status = "okay";
 158 +       bus-width = <4>;
 159 +       max-frequency = <50000000>;
 160 +       cap-sd-highspeed;
 161 +       r_smpl = <1>;
 162 +       cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 163 +       vmmc-supply = <&reg_3p3v>;
 164 +       vqmmc-supply = <&reg_3p3v>;
 165 +       assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 166 +       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 167 +};
 168 +
 169  &nandc {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&parallel_nand_pins>;
 172 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 173 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 174 @@ -527,6 +527,26 @@
 175                 status = "disabled";
 176         };
 177
 178 +       mmc0: mmc@11230000 {
 179 +               compatible = "mediatek,mt7622-mmc";
 180 +               reg = <0 0x11230000 0 0x1000>;
 181 +               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 182 +               clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 183 +                        <&topckgen CLK_TOP_MSDC50_0_SEL>;
 184 +               clock-names = "source", "hclk";
 185 +               status = "disabled";
 186 +       };
 187 +
 188 +       mmc1: mmc@11240000 {
 189 +               compatible = "mediatek,mt7622-mmc";
 190 +               reg = <0 0x11240000 0 0x1000>;
 191 +               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 192 +               clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 193 +                        <&topckgen CLK_TOP_AXI_SEL>;
 194 +               clock-names = "source", "hclk";
 195 +               status = "disabled";
 196 +       };
 197 +
 198         ssusbsys: ssusbsys@1a000000 {
 199                 compatible = "mediatek,mt7622-ssusbsys",
 200                              "syscon";