target/linux/mediatek/patches-4.14/0215-arm64-dts-mt7622-turn-uart0-clock-to-real-ones.patch

   1 From 84b3092b3773777de1ba1ad142e53247fb881ddd Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 28 Dec 2017 18:00:11 +0800
   4 Subject: [PATCH 215/224] arm64: dts: mt7622: turn uart0 clock to real ones
   5
   6 This patch also cleans up two oscillators that provide clocks for MT7623.
   7 Switch the uart clocks to the real ones while at it.
   8
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Cc: Matthias Brugger <matthias.bgg@gmail.com>
  11 ---
  12  arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 ++-------------
  13  1 file changed, 2 insertions(+), 13 deletions(-)
  14
  15 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  16 index 7256879de4c9..d8a17d10e2ff 100644
  17 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  18 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  19 @@ -91,18 +91,6 @@
  20                 };
  21         };
  22
  23 -       uart_clk: dummy25m {
  24 -               compatible = "fixed-clock";
  25 -               #clock-cells = <0>;
  26 -               clock-frequency = <25000000>;
  27 -       };
  28 -
  29 -       bus_clk: dummy280m {
  30 -               compatible = "fixed-clock";
  31 -               #clock-cells = <0>;
  32 -               clock-frequency = <280000000>;
  33 -       };
  34 -
  35         pwrap_clk: dummy40m {
  36                 compatible = "fixed-clock";
  37                 clock-frequency = <40000000>;
  38 @@ -234,7 +222,8 @@
  39                              "mediatek,mt6577-uart";
  40                 reg = <0 0x11002000 0 0x400>;
  41                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
  42 -               clocks = <&uart_clk>, <&bus_clk>;
  43 +               clocks = <&topckgen CLK_TOP_UART_SEL>,
  44 +                        <&pericfg CLK_PERI_UART1_PD>;
  45                 clock-names = "baud", "bus";
  46                 status = "disabled";
  47         };
  48 --
  49 2.11.0
  50