1 From 19fc79333af0d3733d4987bc1e554ae7e8a8cb0d Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Thu, 28 Dec 2017 16:26:10 +0800
4 Subject: [PATCH 214/224] arm64: dts: mt7622: add cpufreq related device nodes
6 Add clocks, regulators and opp information into cpu nodes.
7 In addition, the power supply for cpu nodes is deployed on
10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
11 Cc: Viresh Kumar <viresh.kumar@linaro.org>
13 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++
14 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 52 ++++++++++++++++++++++++++++
15 2 files changed, 64 insertions(+)
17 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
18 index 42bd3a4c9a93..b3878656475c 100644
19 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
20 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
22 bootargs = "console=ttyS0,115200n1";
27 + proc-supply = <&mt6380_vcpu_reg>;
28 + sram-supply = <&mt6380_vm_reg>;
32 + proc-supply = <&mt6380_vcpu_reg>;
33 + sram-supply = <&mt6380_vm_reg>;
38 compatible = "gpio-keys-polled";
39 poll-interval = <100>;
40 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
41 index c387c4cb7d3e..7256879de4c9 100644
42 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
43 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
48 + cpu_opp_table: opp-table {
49 + compatible = "operating-points-v2";
52 + opp-hz = /bits/ 64 <30000000>;
53 + opp-microvolt = <950000>;
57 + opp-hz = /bits/ 64 <437500000>;
58 + opp-microvolt = <1000000>;
62 + opp-hz = /bits/ 64 <600000000>;
63 + opp-microvolt = <1050000>;
67 + opp-hz = /bits/ 64 <812500000>;
68 + opp-microvolt = <1100000>;
72 + opp-hz = /bits/ 64 <1025000000>;
73 + opp-microvolt = <1150000>;
77 + opp-hz = /bits/ 64 <1137500000>;
78 + opp-microvolt = <1200000>;
82 + opp-hz = /bits/ 64 <1262500000>;
83 + opp-microvolt = <1250000>;
87 + opp-hz = /bits/ 64 <1350000000>;
88 + opp-microvolt = <1310000>;
97 compatible = "arm,cortex-a53", "arm,armv8";
99 + clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
100 + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
101 + clock-names = "cpu", "intermediate";
102 + operating-points-v2 = <&cpu_opp_table>;
103 enable-method = "psci";
104 clock-frequency = <1300000000>;
108 compatible = "arm,cortex-a53", "arm,armv8";
110 + clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
111 + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
112 + clock-names = "cpu", "intermediate";
113 + operating-points-v2 = <&cpu_opp_table>;
114 enable-method = "psci";
115 clock-frequency = <1300000000>;