target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch

   1 From 79d0293e8f35e87b1f068fc0b7963a86ba56800e Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 28 Dec 2017 15:46:42 +0800
   4 Subject: [PATCH 211/224] arm64: dts: mt7622: add power domain controller
   5  device nodes
   6
   7 add power domain controller nodes
   8
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Cc: Matthias Brugger <matthias.bgg@gmail.com>
  11 ---
  12  arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 +++++++++++++++
  13  1 file changed, 15 insertions(+)
  14
  15 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  16 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  17 @@ -9,6 +9,7 @@
  18  #include <dt-bindings/interrupt-controller/irq.h>
  19  #include <dt-bindings/interrupt-controller/arm-gic.h>
  20  #include <dt-bindings/clock/mt7622-clk.h>
  21 +#include <dt-bindings/power/mt7622-power.h>
  22  #include <dt-bindings/reset/mt7622-reset.h>
  23
  24  / {
  25 @@ -109,6 +110,20 @@
  26                 #reset-cells = <1>;
  27         };
  28
  29 +       scpsys: scpsys@10006000 {
  30 +               compatible = "mediatek,mt7622-scpsys",
  31 +                            "syscon";
  32 +               #power-domain-cells = <1>;
  33 +               reg = <0 0x10006000 0 0x1000>;
  34 +               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
  35 +                            <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
  36 +                            <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
  37 +                            <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
  38 +               infracfg = <&infracfg>;
  39 +               clocks = <&topckgen CLK_TOP_HIF_SEL>;
  40 +               clock-names = "hif_sel";
  41 +       };
  42 +
  43         sysirq: interrupt-controller@10200620 {
  44                 compatible = "mediatek,mt7622-sysirq",
  45                              "mediatek,mt6577-sysirq";