target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch

   1 From 9c76dd09d27dff05207241aa67a2c6054d057b32 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 28 Dec 2017 10:30:32 +0800
   4 Subject: [PATCH 210/224] arm64: dts: mt7622: add clock controller device nodes
   5
   6 Add clock controller nodes for MT7622 and include header for topckgen,
   7 infracfg, pericfg, apmixedsys, ethsys, sgmiisys, pciesys and ssusbsys
   8 for those devices nodes to be added afterwards.
   9
  10 In addition, provides an oscillator node for the source of PLLs and dummy
  11 clock for PWARP to complement missing support of clock gate for the
  12 wrapper circuit in the driver.
  13
  14 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  15 Cc: Stephen Boyd <sboyd@codeaurora.org>
  16 ---
  17  arch/arm64/boot/dts/mediatek/mt7622.dtsi | 76 ++++++++++++++++++++++++++++++++
  18  1 file changed, 76 insertions(+)
  19
  20 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  21 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  22 @@ -8,6 +8,8 @@
  23
  24  #include <dt-bindings/interrupt-controller/irq.h>
  25  #include <dt-bindings/interrupt-controller/arm-gic.h>
  26 +#include <dt-bindings/clock/mt7622-clk.h>
  27 +#include <dt-bindings/reset/mt7622-reset.h>
  28
  29  / {
  30         compatible = "mediatek,mt7622";
  31 @@ -48,6 +50,19 @@
  32                 clock-frequency = <280000000>;
  33         };
  34
  35 +       pwrap_clk: dummy40m {
  36 +               compatible = "fixed-clock";
  37 +               clock-frequency = <40000000>;
  38 +               #clock-cells = <0>;
  39 +       };
  40 +
  41 +       clk25m: oscillator {
  42 +               compatible = "fixed-clock";
  43 +               #clock-cells = <0>;
  44 +               clock-frequency = <25000000>;
  45 +               clock-output-names = "clkxtal";
  46 +       };
  47 +
  48         psci {
  49                 compatible  = "arm,psci-0.2";
  50                 method      = "smc";
  51 @@ -78,6 +93,22 @@
  52                               IRQ_TYPE_LEVEL_HIGH)>;
  53         };
  54
  55 +       infracfg: infracfg@10000000 {
  56 +               compatible = "mediatek,mt7622-infracfg",
  57 +                            "syscon";
  58 +               reg = <0 0x10000000 0 0x1000>;
  59 +               #clock-cells = <1>;
  60 +               #reset-cells = <1>;
  61 +       };
  62 +
  63 +       pericfg: pericfg@10002000 {
  64 +               compatible = "mediatek,mt7622-pericfg",
  65 +                            "syscon";
  66 +               reg = <0 0x10002000 0 0x1000>;
  67 +               #clock-cells = <1>;
  68 +               #reset-cells = <1>;
  69 +       };
  70 +
  71         sysirq: interrupt-controller@10200620 {
  72                 compatible = "mediatek,mt7622-sysirq",
  73                              "mediatek,mt6577-sysirq";
  74 @@ -87,6 +118,20 @@
  75                 reg = <0 0x10200620 0 0x20>;
  76         };
  77
  78 +       apmixedsys: apmixedsys@10209000 {
  79 +               compatible = "mediatek,mt7622-apmixedsys",
  80 +                            "syscon";
  81 +               reg = <0 0x10209000 0 0x1000>;
  82 +               #clock-cells = <1>;
  83 +       };
  84 +
  85 +       topckgen: topckgen@10210000 {
  86 +               compatible = "mediatek,mt7622-topckgen",
  87 +                            "syscon";
  88 +               reg = <0 0x10210000 0 0x1000>;
  89 +               #clock-cells = <1>;
  90 +       };
  91 +
  92         gic: interrupt-controller@10300000 {
  93                 compatible = "arm,gic-400";
  94                 interrupt-controller;
  95 @@ -107,4 +152,35 @@
  96                 clock-names = "baud", "bus";
  97                 status = "disabled";
  98         };
  99 +
 100 +       ssusbsys: ssusbsys@1a000000 {
 101 +               compatible = "mediatek,mt7622-ssusbsys",
 102 +                            "syscon";
 103 +               reg = <0 0x1a000000 0 0x1000>;
 104 +               #clock-cells = <1>;
 105 +               #reset-cells = <1>;
 106 +       };
 107 +
 108 +       pciesys: pciesys@1a100800 {
 109 +               compatible = "mediatek,mt7622-pciesys",
 110 +                            "syscon";
 111 +               reg = <0 0x1a100800 0 0x1000>;
 112 +               #clock-cells = <1>;
 113 +               #reset-cells = <1>;
 114 +       };
 115 +
 116 +       ethsys: syscon@1b000000 {
 117 +               compatible = "mediatek,mt7622-ethsys",
 118 +                            "syscon";
 119 +               reg = <0 0x1b000000 0 0x1000>;
 120 +               #clock-cells = <1>;
 121 +               #reset-cells = <1>;
 122 +       };
 123 +
 124 +       sgmiisys: sgmiisys@1b128000 {
 125 +               compatible = "mediatek,mt7622-sgmiisys",
 126 +                            "syscon";
 127 +               reg = <0 0x1b128000 0 0x1000>;
 128 +               #clock-cells = <1>;
 129 +       };
 130  };