target/linux/mediatek/patches-4.14/0204-dt-bindings-dmaengine-Add-MediaTek-High-Speed-DMA-co.patch

   1 From 71198859668501ef57450be07da77e9544f59f1e Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Sat, 13 May 2017 15:16:58 +0800
   4 Subject: [PATCH 204/224] dt-bindings: dmaengine: Add MediaTek High-Speed DMA
   5  controller bindings
   6
   7 Document the devicetree bindings for MediaTek High-Speed DMA controller
   8 which could be found on MT7623 SoC or other similar Mediatek SoCs.
   9
  10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  11 ---
  12  .../devicetree/bindings/dma/mtk-hsdma.txt          | 33 ++++++++++++++++++++++
  13  1 file changed, 33 insertions(+)
  14  create mode 100644 Documentation/devicetree/bindings/dma/mtk-hsdma.txt
  15
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt
  18 @@ -0,0 +1,33 @@
  19 +MediaTek High-Speed DMA Controller
  20 +==================================
  21 +
  22 +This device follows the generic DMA bindings defined in dma/dma.txt.
  23 +
  24 +Required properties:
  25 +
  26 +- compatible:  Must be one of
  27 +                 "mediatek,mt7622-hsdma": for MT7622 SoC
  28 +                 "mediatek,mt7623-hsdma": for MT7623 SoC
  29 +- reg:         Should contain the register's base address and length.
  30 +- interrupts:  Should contain a reference to the interrupt used by this
  31 +               device.
  32 +- clocks:      Should be the clock specifiers corresponding to the entry in
  33 +               clock-names property.
  34 +- clock-names: Should contain "hsdma" entries.
  35 +- power-domains: Phandle to the power domain that the device is part of
  36 +- #dma-cells:  The length of the DMA specifier, must be <1>. This one cell
  37 +               in dmas property of a client device represents the channel
  38 +               number.
  39 +Example:
  40 +
  41 +        hsdma: dma-controller@1b007000 {
  42 +               compatible = "mediatek,mt7623-hsdma";
  43 +               reg = <0 0x1b007000 0 0x1000>;
  44 +               interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
  45 +               clocks = <&ethsys CLK_ETHSYS_HSDMA>;
  46 +               clock-names = "hsdma";
  47 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  48 +               #dma-cells = <1>;
  49 +       };
  50 +
  51 +DMA clients must use the format described in dma/dma.txt file.