target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch

   1 From e0e3768b73daae674c69db1f71718894274b7bfc Mon Sep 17 00:00:00 2001
   2 From: Ryder Lee <ryder.lee@mediatek.com>
   3 Date: Thu, 4 Jan 2018 15:44:07 +0800
   4 Subject: [PATCH 184/224] ASoC: mediatek: add some core clocks for MT2701 AFE
   5
   6 Add three core clocks for MT2701 AFE.
   7
   8 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
   9 Signed-off-by: Mark Brown <broonie@kernel.org>
  10 ---
  11  sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 30 ++++++++++++++++++++++-
  12  sound/soc/mediatek/mt2701/mt2701-afe-common.h     |  3 +++
  13  2 files changed, 32 insertions(+), 1 deletion(-)
  14
  15 diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  16 index 56a057c78c9a..949fc3a1d025 100644
  17 --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  18 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  19 @@ -18,8 +18,11 @@
  20  #include "mt2701-afe-clock-ctrl.h"
  21
  22  static const char *const base_clks[] = {
  23 +       [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
  24         [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
  25         [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
  26 +       [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
  27 +       [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
  28         [MT2701_AUDSYS_AFE] = "audio_afe_pd",
  29         [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
  30         [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
  31 @@ -169,10 +172,26 @@ static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
  32         struct mt2701_afe_private *afe_priv = afe->platform_priv;
  33         int ret;
  34
  35 -       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  36 +       /* Enable infra clock gate */
  37 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  38         if (ret)
  39                 return ret;
  40
  41 +       /* Enable top a1sys clock gate */
  42 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  43 +       if (ret)
  44 +               goto err_a1sys;
  45 +
  46 +       /* Enable top a2sys clock gate */
  47 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  48 +       if (ret)
  49 +               goto err_a2sys;
  50 +
  51 +       /* Internal clock gates */
  52 +       ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  53 +       if (ret)
  54 +               goto err_afe;
  55 +
  56         ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  57         if (ret)
  58                 goto err_audio_a1sys;
  59 @@ -193,6 +212,12 @@ static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
  60         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  61  err_audio_a1sys:
  62         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  63 +err_afe:
  64 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  65 +err_a2sys:
  66 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  67 +err_a1sys:
  68 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  69
  70         return ret;
  71  }
  72 @@ -205,6 +230,9 @@ static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
  73         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
  74         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  75         clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  76 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  77 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  78 +       clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  79  }
  80
  81  int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
  82 diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-common.h b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  83 index 9a2b301a4c21..ae8ddeacfbfe 100644
  84 --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  85 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  86 @@ -61,8 +61,11 @@ enum {
  87  };
  88
  89  enum audio_base_clock {
  90 +       MT2701_INFRA_SYS_AUDIO,
  91         MT2701_TOP_AUD_MCLK_SRC0,
  92         MT2701_TOP_AUD_MCLK_SRC1,
  93 +       MT2701_TOP_AUD_A1SYS,
  94 +       MT2701_TOP_AUD_A2SYS,
  95         MT2701_AUDSYS_AFE,
  96         MT2701_AUDSYS_AFE_CONN,
  97         MT2701_AUDSYS_A1SYS,
  98 --
  99 2.11.0
 100