target/linux/mediatek/patches-4.14/0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch

   1 From 4087c924ec899881951b2170a7bb8888747ec532 Mon Sep 17 00:00:00 2001
   2 From: Ryder Lee <ryder.lee@mediatek.com>
   3 Date: Tue, 2 Jan 2018 19:47:20 +0800
   4 Subject: [PATCH 182/224] ASoC: mediatek: cleanup audio driver for MT2701
   5
   6 Cleanup unused code such as 'i2s_num' guard, headers, indentation
   7 and some defines.
   8
   9 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
  10 Signed-off-by: Mark Brown <broonie@kernel.org>
  11 ---
  12  sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 14 +---
  13  sound/soc/mediatek/mt2701/mt2701-afe-common.h     | 20 +----
  14  sound/soc/mediatek/mt2701/mt2701-afe-pcm.c        | 94 ++++-------------------
  15  sound/soc/mediatek/mt2701/mt2701-reg.h            | 41 +---------
  16  4 files changed, 24 insertions(+), 145 deletions(-)
  17
  18 --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  19 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  20 @@ -14,10 +14,6 @@
  21   * GNU General Public License for more details.
  22   */
  23
  24 -#include <sound/soc.h>
  25 -#include <linux/regmap.h>
  26 -#include <linux/pm_runtime.h>
  27 -
  28  #include "mt2701-afe-common.h"
  29  #include "mt2701-afe-clock-ctrl.h"
  30
  31 @@ -223,8 +219,8 @@ int mt2701_afe_enable_clock(struct mtk_b
  32         }
  33
  34         regmap_update_bits(afe->regmap, ASYS_TOP_CON,
  35 -                          AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
  36 -                          AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
  37 +                          ASYS_TOP_CON_ASYS_TIMING_ON,
  38 +                          ASYS_TOP_CON_ASYS_TIMING_ON);
  39         regmap_update_bits(afe->regmap, AFE_DAC_CON0,
  40                            AFE_DAC_CON0_AFE_ON,
  41                            AFE_DAC_CON0_AFE_ON);
  42 @@ -239,7 +235,7 @@ int mt2701_afe_enable_clock(struct mtk_b
  43  int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
  44  {
  45         regmap_update_bits(afe->regmap, ASYS_TOP_CON,
  46 -                          AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
  47 +                          ASYS_TOP_CON_ASYS_TIMING_ON, 0);
  48         regmap_update_bits(afe->regmap, AFE_DAC_CON0,
  49                            AFE_DAC_CON0_AFE_ON, 0);
  50
  51 @@ -272,7 +268,3 @@ void mt2701_mclk_configuration(struct mt
  52         if (ret)
  53                 dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
  54  }
  55 -
  56 -MODULE_DESCRIPTION("MT2701 afe clock control");
  57 -MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
  58 -MODULE_LICENSE("GPL v2");
  59 --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  60 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  61 @@ -16,6 +16,7 @@
  62
  63  #ifndef _MT_2701_AFE_COMMON_H_
  64  #define _MT_2701_AFE_COMMON_H_
  65 +
  66  #include <sound/soc.h>
  67  #include <linux/clk.h>
  68  #include <linux/regmap.h>
  69 @@ -25,16 +26,7 @@
  70  #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
  71  #define MT2701_PLL_DOMAIN_0_RATE       98304000
  72  #define MT2701_PLL_DOMAIN_1_RATE       90316800
  73 -#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2)
  74 -#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
  75 -
  76 -enum {
  77 -       MT2701_I2S_1,
  78 -       MT2701_I2S_2,
  79 -       MT2701_I2S_3,
  80 -       MT2701_I2S_4,
  81 -       MT2701_I2S_NUM,
  82 -};
  83 +#define MT2701_I2S_NUM 4
  84
  85  enum {
  86         MT2701_MEMIF_DL1,
  87 @@ -62,8 +54,7 @@ enum {
  88  };
  89
  90  enum {
  91 -       MT2701_IRQ_ASYS_START,
  92 -       MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
  93 +       MT2701_IRQ_ASYS_IRQ1,
  94         MT2701_IRQ_ASYS_IRQ2,
  95         MT2701_IRQ_ASYS_IRQ3,
  96         MT2701_IRQ_ASYS_END,
  97 @@ -100,9 +91,6 @@ static const unsigned int mt2701_afe_bac
  98         AFE_MEMIF_PBUF_SIZE,
  99  };
 100
 101 -struct snd_pcm_substream;
 102 -struct mtk_base_irq_data;
 103 -
 104  struct mt2701_i2s_data {
 105         int i2s_ctrl_reg;
 106         int i2s_asrc_fs_shift;
 107 @@ -120,7 +108,7 @@ struct mt2701_i2s_path {
 108         int mclk_rate;
 109         int on[I2S_DIR_NUM];
 110         int occupied[I2S_DIR_NUM];
 111 -       const struct mt2701_i2s_data *i2s_data[2];
 112 +       const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
 113         struct clk *hop_ck[I2S_DIR_NUM];
 114         struct clk *sel_ck;
 115         struct clk *div_ck;
 116 --- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
 117 +++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
 118 @@ -20,16 +20,12 @@
 119  #include <linux/of.h>
 120  #include <linux/of_address.h>
 121  #include <linux/pm_runtime.h>
 122 -#include <sound/soc.h>
 123
 124  #include "mt2701-afe-common.h"
 125 -
 126  #include "mt2701-afe-clock-ctrl.h"
 127  #include "../common/mtk-afe-platform-driver.h"
 128  #include "../common/mtk-afe-fe-dai.h"
 129
 130 -#define AFE_IRQ_STATUS_BITS    0xff
 131 -
 132  static const struct snd_pcm_hardware mt2701_afe_hardware = {
 133         .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
 134                 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
 135 @@ -107,21 +103,16 @@ static int mt2701_afe_i2s_startup(struct
 136
 137  static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
 138                                         struct snd_soc_dai *dai,
 139 +                                       int i2s_num,
 140                                         int dir_invert)
 141  {
 142         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 143         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 144         struct mt2701_afe_private *afe_priv = afe->platform_priv;
 145 -       int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
 146 -       struct mt2701_i2s_path *i2s_path;
 147 +       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
 148         const struct mt2701_i2s_data *i2s_data;
 149         int stream_dir = substream->stream;
 150
 151 -       if (i2s_num < 0)
 152 -               return i2s_num;
 153 -
 154 -       i2s_path = &afe_priv->i2s_path[i2s_num];
 155 -
 156         if (dir_invert) {
 157                 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
 158                         stream_dir = SNDRV_PCM_STREAM_CAPTURE;
 159 @@ -167,11 +158,11 @@ static void mt2701_afe_i2s_shutdown(stru
 160         else
 161                 goto I2S_UNSTART;
 162
 163 -       mt2701_afe_i2s_path_shutdown(substream, dai, 0);
 164 +       mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
 165
 166         /* need to disable i2s-out path when disable i2s-in */
 167         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 168 -               mt2701_afe_i2s_path_shutdown(substream, dai, 1);
 169 +               mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
 170
 171  I2S_UNSTART:
 172         /* disable mclk */
 173 @@ -180,24 +171,19 @@ I2S_UNSTART:
 174
 175  static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
 176                                           struct snd_soc_dai *dai,
 177 +                                         int i2s_num,
 178                                           int dir_invert)
 179  {
 180         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 181         struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
 182         struct mt2701_afe_private *afe_priv = afe->platform_priv;
 183 -       int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
 184 -       struct mt2701_i2s_path *i2s_path;
 185 +       struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
 186         const struct mt2701_i2s_data *i2s_data;
 187         struct snd_pcm_runtime * const runtime = substream->runtime;
 188         int reg, fs, w_len = 1; /* now we support bck 64bits only */
 189         int stream_dir = substream->stream;
 190         unsigned int mask = 0, val = 0;
 191
 192 -       if (i2s_num < 0)
 193 -               return i2s_num;
 194 -
 195 -       i2s_path = &afe_priv->i2s_path[i2s_num];
 196 -
 197         if (dir_invert) {
 198                 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
 199                         stream_dir = SNDRV_PCM_STREAM_CAPTURE;
 200 @@ -288,13 +274,13 @@ static int mt2701_afe_i2s_prepare(struct
 201         mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
 202
 203         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 204 -               mt2701_i2s_path_prepare_enable(substream, dai, 0);
 205 +               mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
 206         } else {
 207                 /* need to enable i2s-out path when enable i2s-in */
 208                 /* prepare for another direction "out" */
 209 -               mt2701_i2s_path_prepare_enable(substream, dai, 1);
 210 +               mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
 211                 /* prepare for "in" */
 212 -               mt2701_i2s_path_prepare_enable(substream, dai, 0);
 213 +               mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
 214         }
 215
 216         return 0;
 217 @@ -562,7 +548,6 @@ static const struct snd_soc_dai_ops mt27
 218         .hw_free        = mtk_afe_fe_hw_free,
 219         .prepare        = mtk_afe_fe_prepare,
 220         .trigger        = mtk_afe_fe_trigger,
 221 -
 222  };
 223
 224  static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
 225 @@ -903,31 +888,6 @@ static const struct snd_kcontrol_new mt2
 226                                     PWR2_TOP_CON, 19, 1, 0),
 227  };
 228
 229 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = {
 230 -       SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1,
 231 -                                   1),
 232 -};
 233 -
 234 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = {
 235 -       SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1,
 236 -                                   1),
 237 -};
 238 -
 239 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = {
 240 -       SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1,
 241 -                                   1),
 242 -};
 243 -
 244 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = {
 245 -       SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1,
 246 -                                   1),
 247 -};
 248 -
 249 -static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = {
 250 -       SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1,
 251 -                                   1),
 252 -};
 253 -
 254  static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
 255         /* inter-connections */
 256         SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
 257 @@ -987,19 +947,6 @@ static const struct snd_soc_dapm_widget
 258         SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
 259                            mt2701_afe_multi_ch_out_i2s3,
 260                            ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
 261 -
 262 -       SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0,
 263 -                          mt2701_afe_multi_ch_out_asrc0,
 264 -                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)),
 265 -       SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0,
 266 -                          mt2701_afe_multi_ch_out_asrc1,
 267 -                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)),
 268 -       SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0,
 269 -                          mt2701_afe_multi_ch_out_asrc2,
 270 -                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)),
 271 -       SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0,
 272 -                          mt2701_afe_multi_ch_out_asrc3,
 273 -                          ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)),
 274  };
 275
 276  static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
 277 @@ -1009,7 +956,6 @@ static const struct snd_soc_dapm_route m
 278
 279         {"I2S0 Playback", NULL, "O15"},
 280         {"I2S0 Playback", NULL, "O16"},
 281 -
 282         {"I2S1 Playback", NULL, "O17"},
 283         {"I2S1 Playback", NULL, "O18"},
 284         {"I2S2 Playback", NULL, "O19"},
 285 @@ -1026,7 +972,6 @@ static const struct snd_soc_dapm_route m
 286
 287         {"I00", NULL, "I2S0 Capture"},
 288         {"I01", NULL, "I2S0 Capture"},
 289 -
 290         {"I02", NULL, "I2S1 Capture"},
 291         {"I03", NULL, "I2S1 Capture"},
 292         /* I02,03 link to UL2, also need to open I2S0 */
 293 @@ -1034,15 +979,10 @@ static const struct snd_soc_dapm_route m
 294
 295         {"I26", NULL, "BT Capture"},
 296
 297 -       {"ASRC_O0", "Asrc0 out Switch", "DLM"},
 298 -       {"ASRC_O1", "Asrc1 out Switch", "DLM"},
 299 -       {"ASRC_O2", "Asrc2 out Switch", "DLM"},
 300 -       {"ASRC_O3", "Asrc3 out Switch", "DLM"},
 301 -
 302 -       {"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"},
 303 -       {"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"},
 304 -       {"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"},
 305 -       {"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"},
 306 +       {"I12I13", "Multich I2S0 Out Switch", "DLM"},
 307 +       {"I14I15", "Multich I2S1 Out Switch", "DLM"},
 308 +       {"I16I17", "Multich I2S2 Out Switch", "DLM"},
 309 +       {"I18I19", "Multich I2S3 Out Switch", "DLM"},
 310
 311         { "I12", NULL, "I12I13" },
 312         { "I13", NULL, "I12I13" },
 313 @@ -1067,7 +1007,6 @@ static const struct snd_soc_dapm_route m
 314         { "O21", "I18 Switch", "I18" },
 315         { "O22", "I19 Switch", "I19" },
 316         { "O31", "I35 Switch", "I35" },
 317 -
 318  };
 319
 320  static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
 321 @@ -1484,12 +1423,13 @@ static int mt2701_afe_pcm_dev_probe(stru
 322         afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
 323         if (!afe)
 324                 return -ENOMEM;
 325 +
 326         afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
 327                                           GFP_KERNEL);
 328         if (!afe->platform_priv)
 329                 return -ENOMEM;
 330 -       afe_priv = afe->platform_priv;
 331
 332 +       afe_priv = afe->platform_priv;
 333         afe->dev = &pdev->dev;
 334         dev = afe->dev;
 335
 336 @@ -1524,7 +1464,6 @@ static int mt2701_afe_pcm_dev_probe(stru
 337         afe->memif_size = MT2701_MEMIF_NUM;
 338         afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
 339                                   GFP_KERNEL);
 340 -
 341         if (!afe->memif)
 342                 return -ENOMEM;
 343
 344 @@ -1537,7 +1476,6 @@ static int mt2701_afe_pcm_dev_probe(stru
 345         afe->irqs_size = MT2701_IRQ_ASYS_END;
 346         afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
 347                                  GFP_KERNEL);
 348 -
 349         if (!afe->irqs)
 350                 return -ENOMEM;
 351
 352 @@ -1555,7 +1493,6 @@ static int mt2701_afe_pcm_dev_probe(stru
 353         afe->mtk_afe_hardware = &mt2701_afe_hardware;
 354         afe->memif_fs = mt2701_memif_fs;
 355         afe->irq_fs = mt2701_irq_fs;
 356 -
 357         afe->reg_back_up_list = mt2701_afe_backup_list;
 358         afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
 359         afe->runtime_resume = mt2701_afe_runtime_resume;
 360 @@ -1646,4 +1583,3 @@ module_platform_driver(mt2701_afe_pcm_dr
 361  MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
 362  MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
 363  MODULE_LICENSE("GPL v2");
 364 -
 365 --- a/sound/soc/mediatek/mt2701/mt2701-reg.h
 366 +++ b/sound/soc/mediatek/mt2701/mt2701-reg.h
 367 @@ -17,17 +17,6 @@
 368  #ifndef _MT2701_REG_H_
 369  #define _MT2701_REG_H_
 370
 371 -#include <linux/delay.h>
 372 -#include <linux/module.h>
 373 -#include <linux/of.h>
 374 -#include <linux/of_address.h>
 375 -#include <linux/pm_runtime.h>
 376 -#include <sound/soc.h>
 377 -#include "mt2701-afe-common.h"
 378 -
 379 -/*****************************************************************************
 380 - *                  R E G I S T E R       D E F I N I T I O N
 381 - *****************************************************************************/
 382  #define AUDIO_TOP_CON0 0x0000
 383  #define AUDIO_TOP_CON4 0x0010
 384  #define AUDIO_TOP_CON5 0x0014
 385 @@ -109,18 +98,6 @@
 386  #define AFE_DAI_BASE 0x1370
 387  #define AFE_DAI_CUR 0x137c
 388
 389 -/* AUDIO_TOP_CON0 (0x0000) */
 390 -#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON  (0x3 << 0)
 391 -#define AUDIO_TOP_CON0_PDN_AFE         (0x1 << 2)
 392 -#define AUDIO_TOP_CON0_PDN_APLL_CK     (0x1 << 23)
 393 -
 394 -/* AUDIO_TOP_CON4 (0x0010) */
 395 -#define AUDIO_TOP_CON4_I2SO1_PWN       (0x1 << 6)
 396 -#define AUDIO_TOP_CON4_PDN_A1SYS       (0x1 << 21)
 397 -#define AUDIO_TOP_CON4_PDN_A2SYS       (0x1 << 22)
 398 -#define AUDIO_TOP_CON4_PDN_AFE_CONN    (0x1 << 23)
 399 -#define AUDIO_TOP_CON4_PDN_MRGIF       (0x1 << 25)
 400 -
 401  /* AFE_DAIBT_CON0 (0x001c) */
 402  #define AFE_DAIBT_CON0_DAIBT_EN                (0x1 << 0)
 403  #define AFE_DAIBT_CON0_BT_FUNC_EN      (0x1 << 1)
 404 @@ -137,22 +114,8 @@
 405  #define AFE_MRGIF_CON_I2S_MODE_MASK    (0xf << 20)
 406  #define AFE_MRGIF_CON_I2S_MODE_32K     (0x4 << 20)
 407
 408 -/* ASYS_I2SO1_CON (0x061c) */
 409 -#define ASYS_I2SO1_CON_FS              (0x1f << 8)
 410 -#define ASYS_I2SO1_CON_FS_SET(x)       ((x) << 8)
 411 -#define ASYS_I2SO1_CON_MULTI_CH                (0x1 << 16)
 412 -#define ASYS_I2SO1_CON_SIDEGEN         (0x1 << 30)
 413 -#define ASYS_I2SO1_CON_I2S_EN          (0x1 << 0)
 414 -/* 0:EIAJ 1:I2S */
 415 -#define ASYS_I2SO1_CON_I2S_MODE                (0x1 << 3)
 416 -#define ASYS_I2SO1_CON_WIDE_MODE       (0x1 << 1)
 417 -#define ASYS_I2SO1_CON_WIDE_MODE_SET(x)        ((x) << 1)
 418 -
 419 -/* PWR2_TOP_CON (0x0634) */
 420 -#define PWR2_TOP_CON_INIT_VAL          (0xffe1ffff)
 421 -
 422 -/* ASYS_IRQ_CLR (0x07c0) */
 423 -#define ASYS_IRQ_CLR_ALL               (0xffffffff)
 424 +/* ASYS_TOP_CON (0x0600) */
 425 +#define ASYS_TOP_CON_ASYS_TIMING_ON            (0x3 << 0)
 426
 427  /* PWR2_ASM_CON1 (0x1070) */
 428  #define PWR2_ASM_CON1_INIT_VAL         (0x492492)