target/linux/mediatek/patches-4.14/0169-dt-bindings-pinctrl-add-bindings-for-MediaTek-MT7622.patch

   1 From 4e4c2d695a5daf6dc55b8713af720ef15b52c0e7 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Tue, 12 Dec 2017 14:24:18 +0800
   4 Subject: [PATCH 169/224] dt-bindings: pinctrl: add bindings for MediaTek
   5  MT7622 SoC
   6
   7 Add devicetree bindings for MediaTek MT7622 pinctrl driver.
   8
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Reviewed-by: Biao Huang <biao.huang@mediatek.com>
  11 Acked-by: Rob Herring <robh@kernel.org>
  12 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  13 ---
  14  .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 351 +++++++++++++++++++++
  15  1 file changed, 351 insertions(+)
  16  create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
  17
  18 --- /dev/null
  19 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
  20 @@ -0,0 +1,351 @@
  21 +== MediaTek MT7622 pinctrl controller ==
  22 +
  23 +Required properties for the root node:
  24 + - compatible: Should be one of the following
  25 +              "mediatek,mt7622-pinctrl" for MT7622 SoC
  26 + - reg: offset and length of the pinctrl space
  27 +
  28 + - gpio-controller: Marks the device node as a GPIO controller.
  29 + - #gpio-cells: Should be two. The first cell is the pin number and the
  30 +   second is the GPIO flags.
  31 +
  32 +Please refer to pinctrl-bindings.txt in this directory for details of the
  33 +common pinctrl bindings used by client devices, including the meaning of the
  34 +phrase "pin configuration node".
  35 +
  36 +MT7622 pin configuration nodes act as a container for an arbitrary number of
  37 +subnodes. Each of these subnodes represents some desired configuration for a
  38 +pin, a group, or a list of pins or groups. This configuration can include the
  39 +mux function to select on those pin(s)/group(s), and various pin configuration
  40 +parameters, such as pull-up, slew rate, etc.
  41 +
  42 +We support 2 types of configuration nodes. Those nodes can be either pinmux
  43 +nodes or pinconf nodes. Each configuration node can consist of multiple nodes
  44 +describing the pinmux and pinconf options.
  45 +
  46 +The name of each subnode doesn't matter as long as it is unique; all subnodes
  47 +should be enumerated and processed purely based on their content.
  48 +
  49 +== pinmux nodes content ==
  50 +
  51 +The following generic properties as defined in pinctrl-bindings.txt are valid
  52 +to specify in a pinmux subnode:
  53 +
  54 +Required properties are:
  55 + - groups: An array of strings. Each string contains the name of a group.
  56 +  Valid values for these names are listed below.
  57 + - function: A string containing the name of the function to mux to the
  58 +  group. Valid values for function names are listed below.
  59 +
  60 +== pinconf nodes content ==
  61 +
  62 +The following generic properties as defined in pinctrl-bindings.txt are valid
  63 +to specify in a pinconf subnode:
  64 +
  65 +Required properties are:
  66 + - pins: An array of strings. Each string contains the name of a pin.
  67 +  Valid values for these names are listed below.
  68 + - groups: An array of strings. Each string contains the name of a group.
  69 +  Valid values for these names are listed below.
  70 +
  71 +Optional properies are:
  72 + bias-disable, bias-pull, bias-pull-down, input-enable,
  73 + input-schmitt-enable, input-schmitt-disable, output-enable
  74 + output-low, output-high, drive-strength, slew-rate
  75 +
  76 + Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
  77 + slower slew rate respectively.
  78 + Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
  79 +
  80 +The following specific properties as defined are valid to specify in a pinconf
  81 +subnode:
  82 +
  83 +Optional properties are:
  84 + - mediatek,tdsel: An integer describing the steps for output level shifter duty
  85 +   cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  86 +   to 15.
  87 + - mediatek,rdsel: An integer describing the steps for input level shifter duty
  88 +   cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  89 +   to 63.
  90 +
  91 +== Valid values for pins, function and groups on MT7622 ==
  92 +
  93 +Valid values for pins are:
  94 +pins can be referenced via the pin names as the below table shown and the
  95 +related physical number is also put ahead of those names which helps cross
  96 +references to pins between groups to know whether pins assignment conflict
  97 +happens among devices try to acquire those available pins.
  98 +
  99 +       Pin #:  Valid values for pins
 100 +       -----------------------------
 101 +       PIN 0: "GPIO_A"
 102 +       PIN 1: "I2S1_IN"
 103 +       PIN 2: "I2S1_OUT"
 104 +       PIN 3: "I2S_BCLK"
 105 +       PIN 4: "I2S_WS"
 106 +       PIN 5: "I2S_MCLK"
 107 +       PIN 6: "TXD0"
 108 +       PIN 7: "RXD0"
 109 +       PIN 8: "SPI_WP"
 110 +       PIN 9: "SPI_HOLD"
 111 +       PIN 10: "SPI_CLK"
 112 +       PIN 11: "SPI_MOSI"
 113 +       PIN 12: "SPI_MISO"
 114 +       PIN 13: "SPI_CS"
 115 +       PIN 14: "I2C_SDA"
 116 +       PIN 15: "I2C_SCL"
 117 +       PIN 16: "I2S2_IN"
 118 +       PIN 17: "I2S3_IN"
 119 +       PIN 18: "I2S4_IN"
 120 +       PIN 19: "I2S2_OUT"
 121 +       PIN 20: "I2S3_OUT"
 122 +       PIN 21: "I2S4_OUT"
 123 +       PIN 22: "GPIO_B"
 124 +       PIN 23: "MDC"
 125 +       PIN 24: "MDIO"
 126 +       PIN 25: "G2_TXD0"
 127 +       PIN 26: "G2_TXD1"
 128 +       PIN 27: "G2_TXD2"
 129 +       PIN 28: "G2_TXD3"
 130 +       PIN 29: "G2_TXEN"
 131 +       PIN 30: "G2_TXC"
 132 +       PIN 31: "G2_RXD0"
 133 +       PIN 32: "G2_RXD1"
 134 +       PIN 33: "G2_RXD2"
 135 +       PIN 34: "G2_RXD3"
 136 +       PIN 35: "G2_RXDV"
 137 +       PIN 36: "G2_RXC"
 138 +       PIN 37: "NCEB"
 139 +       PIN 38: "NWEB"
 140 +       PIN 39: "NREB"
 141 +       PIN 40: "NDL4"
 142 +       PIN 41: "NDL5"
 143 +       PIN 42: "NDL6"
 144 +       PIN 43: "NDL7"
 145 +       PIN 44: "NRB"
 146 +       PIN 45: "NCLE"
 147 +       PIN 46: "NALE"
 148 +       PIN 47: "NDL0"
 149 +       PIN 48: "NDL1"
 150 +       PIN 49: "NDL2"
 151 +       PIN 50: "NDL3"
 152 +       PIN 51: "MDI_TP_P0"
 153 +       PIN 52: "MDI_TN_P0"
 154 +       PIN 53: "MDI_RP_P0"
 155 +       PIN 54: "MDI_RN_P0"
 156 +       PIN 55: "MDI_TP_P1"
 157 +       PIN 56: "MDI_TN_P1"
 158 +       PIN 57: "MDI_RP_P1"
 159 +       PIN 58: "MDI_RN_P1"
 160 +       PIN 59: "MDI_RP_P2"
 161 +       PIN 60: "MDI_RN_P2"
 162 +       PIN 61: "MDI_TP_P2"
 163 +       PIN 62: "MDI_TN_P2"
 164 +       PIN 63: "MDI_TP_P3"
 165 +       PIN 64: "MDI_TN_P3"
 166 +       PIN 65: "MDI_RP_P3"
 167 +       PIN 66: "MDI_RN_P3"
 168 +       PIN 67: "MDI_RP_P4"
 169 +       PIN 68: "MDI_RN_P4"
 170 +       PIN 69: "MDI_TP_P4"
 171 +       PIN 70: "MDI_TN_P4"
 172 +       PIN 71: "PMIC_SCL"
 173 +       PIN 72: "PMIC_SDA"
 174 +       PIN 73: "SPIC1_CLK"
 175 +       PIN 74: "SPIC1_MOSI"
 176 +       PIN 75: "SPIC1_MISO"
 177 +       PIN 76: "SPIC1_CS"
 178 +       PIN 77: "GPIO_D"
 179 +       PIN 78: "WATCHDOG"
 180 +       PIN 79: "RTS3_N"
 181 +       PIN 80: "CTS3_N"
 182 +       PIN 81: "TXD3"
 183 +       PIN 82: "RXD3"
 184 +       PIN 83: "PERST0_N"
 185 +       PIN 84: "PERST1_N"
 186 +       PIN 85: "WLED_N"
 187 +       PIN 86: "EPHY_LED0_N"
 188 +       PIN 87: "AUXIN0"
 189 +       PIN 88: "AUXIN1"
 190 +       PIN 89: "AUXIN2"
 191 +       PIN 90: "AUXIN3"
 192 +       PIN 91: "TXD4"
 193 +       PIN 92: "RXD4"
 194 +       PIN 93: "RTS4_N"
 195 +       PIN 94: "CST4_N"
 196 +       PIN 95: "PWM1"
 197 +       PIN 96: "PWM2"
 198 +       PIN 97: "PWM3"
 199 +       PIN 98: "PWM4"
 200 +       PIN 99: "PWM5"
 201 +       PIN 100: "PWM6"
 202 +       PIN 101: "PWM7"
 203 +       PIN 102: "GPIO_E"
 204 +
 205 +Valid values for function are:
 206 +       "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
 207 +       "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
 208 +
 209 +Valid values for groups are:
 210 +additional data is put followingly with valid value allowing us to know which
 211 +applicable function and which relevant pins (in pin#) are able applied for that
 212 +group.
 213 +
 214 +       Valid value                     function        pins (in pin#)
 215 +       -------------------------------------------------------------------------
 216 +       "emmc"                          "emmc"          40, 41, 42, 43, 44, 45,
 217 +                                                       47, 48, 49, 50
 218 +       "emmc_rst"                      "emmc"          37
 219 +       "esw"                           "eth"           51, 52, 53, 54, 55, 56,
 220 +                                                       57, 58, 59, 60, 61, 62,
 221 +                                                       63, 64, 65, 66, 67, 68,
 222 +                                                       69, 70
 223 +       "esw_p0_p1"                     "eth"           51, 52, 53, 54, 55, 56,
 224 +                                                       57, 58
 225 +       "esw_p2_p3_p4"                  "eth"           59, 60, 61, 62, 63, 64,
 226 +                                                       65, 66, 67, 68, 69, 70
 227 +       "rgmii_via_esw"                 "eth"           59, 60, 61, 62, 63, 64,
 228 +                                                       65, 66, 67, 68, 69, 70
 229 +       "rgmii_via_gmac1"               "eth"           59, 60, 61, 62, 63, 64,
 230 +                                                       65, 66, 67, 68, 69, 70
 231 +       "rgmii_via_gmac2"               "eth"           25, 26, 27, 28, 29, 30,
 232 +                                                       31, 32, 33, 34, 35, 36
 233 +       "mdc_mdio"                      "eth"           23, 24
 234 +       "i2c0"                          "i2c"           14, 15
 235 +       "i2c1_0"                        "i2c"           55, 56
 236 +       "i2c1_1"                        "i2c"           73, 74
 237 +       "i2c1_2"                        "i2c"           87, 88
 238 +       "i2c2_0"                        "i2c"           57, 58
 239 +       "i2c2_1"                        "i2c"           75, 76
 240 +       "i2c2_2"                        "i2c"           89, 90
 241 +       "i2s_in_mclk_bclk_ws"           "i2s"           3, 4, 5
 242 +       "i2s1_in_data"                  "i2s"           1
 243 +       "i2s2_in_data"                  "i2s"           16
 244 +       "i2s3_in_data"                  "i2s"           17
 245 +       "i2s4_in_data"                  "i2s"           18
 246 +       "i2s_out_mclk_bclk_ws"          "i2s"           3, 4, 5
 247 +       "i2s1_out_data"                 "i2s"           2
 248 +       "i2s2_out_data"                 "i2s"           19
 249 +       "i2s3_out_data"                 "i2s"           20
 250 +       "i2s4_out_data"                 "i2s"           21
 251 +       "ir_0_tx"                       "ir"            16
 252 +       "ir_1_tx"                       "ir"            59
 253 +       "ir_2_tx"                       "ir"            99
 254 +       "ir_0_rx"                       "ir"            17
 255 +       "ir_1_rx"                       "ir"            60
 256 +       "ir_2_rx"                       "ir"            100
 257 +       "ephy_leds"                     "led"           86, 91, 92, 93, 94
 258 +       "ephy0_led"                     "led"           86
 259 +       "ephy1_led"                     "led"           91
 260 +       "ephy2_led"                     "led"           92
 261 +       "ephy3_led"                     "led"           93
 262 +       "ephy4_led"                     "led"           94
 263 +       "wled"                          "led"           85
 264 +       "par_nand"                      "flash"         37, 38, 39, 40, 41, 42,
 265 +                                                       43, 44, 45, 46, 47, 48,
 266 +                                                       49, 50
 267 +       "snfi"                          "flash"         8, 9, 10, 11, 12, 13
 268 +       "spi_nor"                       "flash"         8, 9, 10, 11, 12, 13
 269 +       "pcie0_0_waken"                 "pcie"          14
 270 +       "pcie0_1_waken"                 "pcie"          79
 271 +       "pcie1_0_waken"                 "pcie"          14
 272 +       "pcie0_0_clkreq"                "pcie"          15
 273 +       "pcie0_1_clkreq"                "pcie"          80
 274 +       "pcie1_0_clkreq"                "pcie"          15
 275 +       "pcie0_pad_perst"               "pcie"          83
 276 +       "pcie1_pad_perst"               "pcie"          84
 277 +       "pmic_bus"                      "pmic"          71, 72
 278 +       "pwm_ch1_0"                     "pwm"           51
 279 +       "pwm_ch1_1"                     "pwm"           73
 280 +       "pwm_ch1_2"                     "pwm"           95
 281 +       "pwm_ch2_0"                     "pwm"           52
 282 +       "pwm_ch2_1"                     "pwm"           74
 283 +       "pwm_ch2_2"                     "pwm"           96
 284 +       "pwm_ch3_0"                     "pwm"           53
 285 +       "pwm_ch3_1"                     "pwm"           75
 286 +       "pwm_ch3_2"                     "pwm"           97
 287 +       "pwm_ch4_0"                     "pwm"           54
 288 +       "pwm_ch4_1"                     "pwm"           67
 289 +       "pwm_ch4_2"                     "pwm"           76
 290 +       "pwm_ch4_3"                     "pwm"           98
 291 +       "pwm_ch5_0"                     "pwm"           68
 292 +       "pwm_ch5_1"                     "pwm"           77
 293 +       "pwm_ch5_2"                     "pwm"           99
 294 +       "pwm_ch6_0"                     "pwm"           69
 295 +       "pwm_ch6_1"                     "pwm"           78
 296 +       "pwm_ch6_2"                     "pwm"           81
 297 +       "pwm_ch6_3"                     "pwm"           100
 298 +       "pwm_ch7_0"                     "pwm"           70
 299 +       "pwm_ch7_1"                     "pwm"           82
 300 +       "pwm_ch7_2"                     "pwm"           101
 301 +       "sd_0"                          "sd"            16, 17, 18, 19, 20, 21
 302 +       "sd_1"                          "sd"            25, 26, 27, 28, 29, 30
 303 +       "spic0_0"                       "spi"           63, 64, 65, 66
 304 +       "spic0_1"                       "spi"           79, 80, 81, 82
 305 +       "spic1_0"                       "spi"           67, 68, 69, 70
 306 +       "spic1_1"                       "spi"           73, 74, 75, 76
 307 +       "spic2_0_wp_hold"               "spi"           8, 9
 308 +       "spic2_0"                       "spi"           10, 11, 12, 13
 309 +       "tdm_0_out_mclk_bclk_ws"        "tdm"           8, 9, 10
 310 +       "tdm_0_in_mclk_bclk_ws"         "tdm"           11, 12, 13
 311 +       "tdm_0_out_data"                "tdm"           20
 312 +       "tdm_0_in_data"                 "tdm"           21
 313 +       "tdm_1_out_mclk_bclk_ws"        "tdm"           57, 58, 59
 314 +       "tdm_1_in_mclk_bclk_ws"         "tdm"           60, 61, 62
 315 +       "tdm_1_out_data"                "tdm"           55
 316 +       "tdm_1_in_data"                 "tdm"           56
 317 +       "uart0_0_tx_rx"                 "uart"          6, 7
 318 +       "uart1_0_tx_rx"                 "uart"          55, 56
 319 +       "uart1_0_rts_cts"               "uart"          57, 58
 320 +       "uart1_1_tx_rx"                 "uart"          73, 74
 321 +       "uart1_1_rts_cts"               "uart"          75, 76
 322 +       "uart2_0_tx_rx"                 "uart"          3, 4
 323 +       "uart2_0_rts_cts"               "uart"          1, 2
 324 +       "uart2_1_tx_rx"                 "uart"          51, 52
 325 +       "uart2_1_rts_cts"               "uart"          53, 54
 326 +       "uart2_2_tx_rx"                 "uart"          59, 60
 327 +       "uart2_2_rts_cts"               "uart"          61, 62
 328 +       "uart2_3_tx_rx"                 "uart"          95, 96
 329 +       "uart3_0_tx_rx"                 "uart"          57, 58
 330 +       "uart3_1_tx_rx"                 "uart"          81, 82
 331 +       "uart3_1_rts_cts"               "uart"          79, 80
 332 +       "uart4_0_tx_rx"                 "uart"          61, 62
 333 +       "uart4_1_tx_rx"                 "uart"          91, 92
 334 +       "uart4_1_rts_cts"               "uart"          93, 94
 335 +       "uart4_2_tx_rx"                 "uart"          97, 98
 336 +       "uart4_2_rts_cts"               "uart"          95, 96
 337 +       "watchdog"                      "watchdog"      78
 338 +
 339 +Example:
 340 +
 341 +       pio: pinctrl@10211000 {
 342 +               compatible = "mediatek,mt7622-pinctrl";
 343 +               reg = <0 0x10211000 0 0x1000>;
 344 +               gpio-controller;
 345 +               #gpio-cells = <2>;
 346 +
 347 +               pinctrl_eth_default: eth-default {
 348 +                       mux-mdio {
 349 +                               groups = "mdc_mdio";
 350 +                               function = "eth";
 351 +                               drive-strength = <12>;
 352 +                       };
 353 +
 354 +                       mux-gmac2 {
 355 +                               groups = "gmac2";
 356 +                               function = "eth";
 357 +                               drive-strength = <12>;
 358 +                       };
 359 +
 360 +                       mux-esw {
 361 +                               groups = "esw";
 362 +                               function = "eth";
 363 +                               drive-strength = <8>;
 364 +                       };
 365 +
 366 +                       conf-mdio {
 367 +                               pins = "MDC";
 368 +                               bias-pull-up;
 369 +                       };
 370 +               };
 371 +       };