target/linux/mediatek/patches-4.14/0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch

   1 From b24e830d69f1fa637284c093410645a059b60028 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 5 Oct 2017 11:50:24 +0800
   4 Subject: [PATCH 150/224] clk: mediatek: add clock support for MT7622 SoC
   5
   6 Add all supported clocks exported from every susbystem found on MT7622 SoC
   7 such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys,
   8 ethsys and audsys.
   9
  10 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
  11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 ---
  14  drivers/clk/mediatek/Kconfig          |  30 ++
  15  drivers/clk/mediatek/Makefile         |   4 +
  16  drivers/clk/mediatek/clk-mt7622-aud.c | 195 +++++++++
  17  drivers/clk/mediatek/clk-mt7622-eth.c | 156 +++++++
  18  drivers/clk/mediatek/clk-mt7622-hif.c | 169 ++++++++
  19  drivers/clk/mediatek/clk-mt7622.c     | 780 ++++++++++++++++++++++++++++++++++
  20  6 files changed, 1334 insertions(+)
  21  create mode 100644 drivers/clk/mediatek/clk-mt7622-aud.c
  22  create mode 100644 drivers/clk/mediatek/clk-mt7622-eth.c
  23  create mode 100644 drivers/clk/mediatek/clk-mt7622-hif.c
  24  create mode 100644 drivers/clk/mediatek/clk-mt7622.c
  25
  26 diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
  27 index 300dbb551bf7..59dc0aad553c 100644
  28 --- a/drivers/clk/mediatek/Kconfig
  29 +++ b/drivers/clk/mediatek/Kconfig
  30 @@ -132,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS
  31         ---help---
  32           This driver supports Mediatek MT6797 vencsys clocks.
  33
  34 +config COMMON_CLK_MT7622
  35 +       bool "Clock driver for MediaTek MT7622"
  36 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  37 +       select COMMON_CLK_MEDIATEK
  38 +       default ARCH_MEDIATEK
  39 +       ---help---
  40 +         This driver supports MediaTek MT7622 basic clocks and clocks
  41 +         required for various periperals found on MediaTek.
  42 +
  43 +config COMMON_CLK_MT7622_ETHSYS
  44 +       bool "Clock driver for MediaTek MT7622 ETHSYS"
  45 +       depends on COMMON_CLK_MT7622
  46 +       ---help---
  47 +         This driver add support for clocks for Ethernet and SGMII
  48 +         required on MediaTek MT7622 SoC.
  49 +
  50 +config COMMON_CLK_MT7622_HIFSYS
  51 +       bool "Clock driver for MediaTek MT7622 HIFSYS"
  52 +       depends on COMMON_CLK_MT7622
  53 +       ---help---
  54 +         This driver supports MediaTek MT7622 HIFSYS clocks providing
  55 +         to PCI-E and USB.
  56 +
  57 +config COMMON_CLK_MT7622_AUDSYS
  58 +       bool "Clock driver for MediaTek MT7622 AUDSYS"
  59 +       depends on COMMON_CLK_MT7622
  60 +       ---help---
  61 +         This driver supports MediaTek MT7622 AUDSYS clocks providing
  62 +         to audio consumers such as I2S and TDM.
  63 +
  64  config COMMON_CLK_MT8135
  65         bool "Clock driver for Mediatek MT8135"
  66         depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
  67 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
  68 index a4e5c47c73a4..de8c3d0bb4ca 100644
  69 --- a/drivers/clk/mediatek/Makefile
  70 +++ b/drivers/clk/mediatek/Makefile
  71 @@ -20,5 +20,9 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
  72  obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
  73  obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
  74  obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
  75 +obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
  76 +obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
  77 +obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
  78 +obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
  79  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
  80  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
  81 diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
  82 new file mode 100644
  83 index 000000000000..fad7d9fc53ba
  84 --- /dev/null
  85 +++ b/drivers/clk/mediatek/clk-mt7622-aud.c
  86 @@ -0,0 +1,195 @@
  87 +/*
  88 + * Copyright (c) 2017 MediaTek Inc.
  89 + * Author: Chen Zhong <chen.zhong@mediatek.com>
  90 + *        Sean Wang <sean.wang@mediatek.com>
  91 + *
  92 + * This program is free software; you can redistribute it and/or modify
  93 + * it under the terms of the GNU General Public License version 2 as
  94 + * published by the Free Software Foundation.
  95 + *
  96 + * This program is distributed in the hope that it will be useful,
  97 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  98 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  99 + * GNU General Public License for more details.
 100 + */
 101 +
 102 +#include <linux/clk-provider.h>
 103 +#include <linux/of.h>
 104 +#include <linux/of_address.h>
 105 +#include <linux/of_device.h>
 106 +#include <linux/platform_device.h>
 107 +
 108 +#include "clk-mtk.h"
 109 +#include "clk-gate.h"
 110 +
 111 +#include <dt-bindings/clock/mt7622-clk.h>
 112 +
 113 +#define GATE_AUDIO0(_id, _name, _parent, _shift) {     \
 114 +               .id = _id,                              \
 115 +               .name = _name,                          \
 116 +               .parent_name = _parent,                 \
 117 +               .regs = &audio0_cg_regs,                        \
 118 +               .shift = _shift,                        \
 119 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 120 +       }
 121 +
 122 +#define GATE_AUDIO1(_id, _name, _parent, _shift) {     \
 123 +               .id = _id,                              \
 124 +               .name = _name,                          \
 125 +               .parent_name = _parent,                 \
 126 +               .regs = &audio1_cg_regs,                        \
 127 +               .shift = _shift,                        \
 128 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 129 +       }
 130 +
 131 +#define GATE_AUDIO2(_id, _name, _parent, _shift) {     \
 132 +               .id = _id,                              \
 133 +               .name = _name,                          \
 134 +               .parent_name = _parent,                 \
 135 +               .regs = &audio2_cg_regs,                        \
 136 +               .shift = _shift,                        \
 137 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 138 +       }
 139 +
 140 +#define GATE_AUDIO3(_id, _name, _parent, _shift) {     \
 141 +               .id = _id,                              \
 142 +               .name = _name,                          \
 143 +               .parent_name = _parent,                 \
 144 +               .regs = &audio3_cg_regs,                        \
 145 +               .shift = _shift,                        \
 146 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 147 +       }
 148 +
 149 +static const struct mtk_gate_regs audio0_cg_regs = {
 150 +       .set_ofs = 0x0,
 151 +       .clr_ofs = 0x0,
 152 +       .sta_ofs = 0x0,
 153 +};
 154 +
 155 +static const struct mtk_gate_regs audio1_cg_regs = {
 156 +       .set_ofs = 0x10,
 157 +       .clr_ofs = 0x10,
 158 +       .sta_ofs = 0x10,
 159 +};
 160 +
 161 +static const struct mtk_gate_regs audio2_cg_regs = {
 162 +       .set_ofs = 0x14,
 163 +       .clr_ofs = 0x14,
 164 +       .sta_ofs = 0x14,
 165 +};
 166 +
 167 +static const struct mtk_gate_regs audio3_cg_regs = {
 168 +       .set_ofs = 0x634,
 169 +       .clr_ofs = 0x634,
 170 +       .sta_ofs = 0x634,
 171 +};
 172 +
 173 +static const struct mtk_gate audio_clks[] = {
 174 +       /* AUDIO0 */
 175 +       GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
 176 +       GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
 177 +       GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
 178 +       GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
 179 +       /* AUDIO1 */
 180 +       GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
 181 +       GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
 182 +       GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
 183 +       GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
 184 +       GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
 185 +       GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
 186 +       GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
 187 +       GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
 188 +       GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
 189 +       GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
 190 +       GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
 191 +       GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
 192 +       GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
 193 +       GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
 194 +       GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
 195 +       /* AUDIO2 */
 196 +       GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
 197 +       GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
 198 +       GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
 199 +       GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
 200 +       GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
 201 +       GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
 202 +       GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
 203 +       GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
 204 +       GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
 205 +       GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
 206 +       GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
 207 +       GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
 208 +       GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
 209 +       GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
 210 +       GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
 211 +       GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
 212 +       GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
 213 +       GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
 214 +       /* AUDIO3 */
 215 +       GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
 216 +       GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
 217 +       GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
 218 +       GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
 219 +       GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
 220 +       GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
 221 +       GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
 222 +       GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
 223 +       GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
 224 +};
 225 +
 226 +static int clk_mt7622_audiosys_init(struct platform_device *pdev)
 227 +{
 228 +       struct clk_onecell_data *clk_data;
 229 +       struct device_node *node = pdev->dev.of_node;
 230 +       int r;
 231 +
 232 +       clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
 233 +
 234 +       mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
 235 +                              clk_data);
 236 +
 237 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 238 +       if (r)
 239 +               dev_err(&pdev->dev,
 240 +                       "could not register clock provider: %s: %d\n",
 241 +                       pdev->name, r);
 242 +
 243 +       return r;
 244 +}
 245 +
 246 +static const struct of_device_id of_match_clk_mt7622_aud[] = {
 247 +       {
 248 +               .compatible = "mediatek,mt7622-audsys",
 249 +               .data = clk_mt7622_audiosys_init,
 250 +       }, {
 251 +               /* sentinel */
 252 +       }
 253 +};
 254 +
 255 +static int clk_mt7622_aud_probe(struct platform_device *pdev)
 256 +{
 257 +       int (*clk_init)(struct platform_device *);
 258 +       int r;
 259 +
 260 +       clk_init = of_device_get_match_data(&pdev->dev);
 261 +       if (!clk_init)
 262 +               return -EINVAL;
 263 +
 264 +       r = clk_init(pdev);
 265 +       if (r)
 266 +               dev_err(&pdev->dev,
 267 +                       "could not register clock provider: %s: %d\n",
 268 +                       pdev->name, r);
 269 +
 270 +       return r;
 271 +}
 272 +
 273 +static struct platform_driver clk_mt7622_aud_drv = {
 274 +       .probe = clk_mt7622_aud_probe,
 275 +       .driver = {
 276 +               .name = "clk-mt7622-aud",
 277 +               .of_match_table = of_match_clk_mt7622_aud,
 278 +       },
 279 +};
 280 +
 281 +builtin_platform_driver(clk_mt7622_aud_drv);
 282 diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
 283 new file mode 100644
 284 index 000000000000..6328127bbb3c
 285 --- /dev/null
 286 +++ b/drivers/clk/mediatek/clk-mt7622-eth.c
 287 @@ -0,0 +1,156 @@
 288 +/*
 289 + * Copyright (c) 2017 MediaTek Inc.
 290 + * Author: Chen Zhong <chen.zhong@mediatek.com>
 291 + *        Sean Wang <sean.wang@mediatek.com>
 292 + *
 293 + * This program is free software; you can redistribute it and/or modify
 294 + * it under the terms of the GNU General Public License version 2 as
 295 + * published by the Free Software Foundation.
 296 + *
 297 + * This program is distributed in the hope that it will be useful,
 298 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 299 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 300 + * GNU General Public License for more details.
 301 + */
 302 +
 303 +#include <linux/clk-provider.h>
 304 +#include <linux/of.h>
 305 +#include <linux/of_address.h>
 306 +#include <linux/of_device.h>
 307 +#include <linux/platform_device.h>
 308 +
 309 +#include "clk-mtk.h"
 310 +#include "clk-gate.h"
 311 +
 312 +#include <dt-bindings/clock/mt7622-clk.h>
 313 +
 314 +#define GATE_ETH(_id, _name, _parent, _shift) {        \
 315 +               .id = _id,                              \
 316 +               .name = _name,                          \
 317 +               .parent_name = _parent,                 \
 318 +               .regs = &eth_cg_regs,                   \
 319 +               .shift = _shift,                        \
 320 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
 321 +       }
 322 +
 323 +static const struct mtk_gate_regs eth_cg_regs = {
 324 +       .set_ofs = 0x30,
 325 +       .clr_ofs = 0x30,
 326 +       .sta_ofs = 0x30,
 327 +};
 328 +
 329 +static const struct mtk_gate eth_clks[] = {
 330 +       GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
 331 +       GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
 332 +       GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
 333 +       GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
 334 +       GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
 335 +};
 336 +
 337 +static const struct mtk_gate_regs sgmii_cg_regs = {
 338 +       .set_ofs = 0xE4,
 339 +       .clr_ofs = 0xE4,
 340 +       .sta_ofs = 0xE4,
 341 +};
 342 +
 343 +#define GATE_SGMII(_id, _name, _parent, _shift) {      \
 344 +               .id = _id,                              \
 345 +               .name = _name,                          \
 346 +               .parent_name = _parent,                 \
 347 +               .regs = &sgmii_cg_regs,                 \
 348 +               .shift = _shift,                        \
 349 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
 350 +       }
 351 +
 352 +static const struct mtk_gate sgmii_clks[] = {
 353 +       GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
 354 +                  "ssusb_tx250m", 2),
 355 +       GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
 356 +                  "ssusb_eq_rx250m", 3),
 357 +       GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
 358 +                  "ssusb_cdr_ref", 4),
 359 +       GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
 360 +                  "ssusb_cdr_fb", 5),
 361 +};
 362 +
 363 +static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 364 +{
 365 +       struct clk_onecell_data *clk_data;
 366 +       struct device_node *node = pdev->dev.of_node;
 367 +       int r;
 368 +
 369 +       clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
 370 +
 371 +       mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
 372 +                              clk_data);
 373 +
 374 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 375 +       if (r)
 376 +               dev_err(&pdev->dev,
 377 +                       "could not register clock provider: %s: %d\n",
 378 +                       pdev->name, r);
 379 +
 380 +       mtk_register_reset_controller(node, 1, 0x34);
 381 +
 382 +       return r;
 383 +}
 384 +
 385 +static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
 386 +{
 387 +       struct clk_onecell_data *clk_data;
 388 +       struct device_node *node = pdev->dev.of_node;
 389 +       int r;
 390 +
 391 +       clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
 392 +
 393 +       mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
 394 +                              clk_data);
 395 +
 396 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 397 +       if (r)
 398 +               dev_err(&pdev->dev,
 399 +                       "could not register clock provider: %s: %d\n",
 400 +                       pdev->name, r);
 401 +
 402 +       return r;
 403 +}
 404 +
 405 +static const struct of_device_id of_match_clk_mt7622_eth[] = {
 406 +       {
 407 +               .compatible = "mediatek,mt7622-ethsys",
 408 +               .data = clk_mt7622_ethsys_init,
 409 +       }, {
 410 +               .compatible = "mediatek,mt7622-sgmiisys",
 411 +               .data = clk_mt7622_sgmiisys_init,
 412 +       }, {
 413 +               /* sentinel */
 414 +       }
 415 +};
 416 +
 417 +static int clk_mt7622_eth_probe(struct platform_device *pdev)
 418 +{
 419 +       int (*clk_init)(struct platform_device *);
 420 +       int r;
 421 +
 422 +       clk_init = of_device_get_match_data(&pdev->dev);
 423 +       if (!clk_init)
 424 +               return -EINVAL;
 425 +
 426 +       r = clk_init(pdev);
 427 +       if (r)
 428 +               dev_err(&pdev->dev,
 429 +                       "could not register clock provider: %s: %d\n",
 430 +                       pdev->name, r);
 431 +
 432 +       return r;
 433 +}
 434 +
 435 +static struct platform_driver clk_mt7622_eth_drv = {
 436 +       .probe = clk_mt7622_eth_probe,
 437 +       .driver = {
 438 +               .name = "clk-mt7622-eth",
 439 +               .of_match_table = of_match_clk_mt7622_eth,
 440 +       },
 441 +};
 442 +
 443 +builtin_platform_driver(clk_mt7622_eth_drv);
 444 diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
 445 new file mode 100644
 446 index 000000000000..a6e8534276c6
 447 --- /dev/null
 448 +++ b/drivers/clk/mediatek/clk-mt7622-hif.c
 449 @@ -0,0 +1,169 @@
 450 +/*
 451 + * Copyright (c) 2017 MediaTek Inc.
 452 + * Author: Chen Zhong <chen.zhong@mediatek.com>
 453 + *        Sean Wang <sean.wang@mediatek.com>
 454 + *
 455 + * This program is free software; you can redistribute it and/or modify
 456 + * it under the terms of the GNU General Public License version 2 as
 457 + * published by the Free Software Foundation.
 458 + *
 459 + * This program is distributed in the hope that it will be useful,
 460 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 461 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 462 + * GNU General Public License for more details.
 463 + */
 464 +
 465 +#include <linux/clk-provider.h>
 466 +#include <linux/of.h>
 467 +#include <linux/of_address.h>
 468 +#include <linux/of_device.h>
 469 +#include <linux/platform_device.h>
 470 +
 471 +#include "clk-mtk.h"
 472 +#include "clk-gate.h"
 473 +
 474 +#include <dt-bindings/clock/mt7622-clk.h>
 475 +
 476 +#define GATE_PCIE(_id, _name, _parent, _shift) {       \
 477 +               .id = _id,                              \
 478 +               .name = _name,                          \
 479 +               .parent_name = _parent,                 \
 480 +               .regs = &pcie_cg_regs,                  \
 481 +               .shift = _shift,                        \
 482 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
 483 +       }
 484 +
 485 +#define GATE_SSUSB(_id, _name, _parent, _shift) {      \
 486 +               .id = _id,                              \
 487 +               .name = _name,                          \
 488 +               .parent_name = _parent,                 \
 489 +               .regs = &ssusb_cg_regs,                 \
 490 +               .shift = _shift,                        \
 491 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
 492 +       }
 493 +
 494 +static const struct mtk_gate_regs pcie_cg_regs = {
 495 +       .set_ofs = 0x30,
 496 +       .clr_ofs = 0x30,
 497 +       .sta_ofs = 0x30,
 498 +};
 499 +
 500 +static const struct mtk_gate_regs ssusb_cg_regs = {
 501 +       .set_ofs = 0x30,
 502 +       .clr_ofs = 0x30,
 503 +       .sta_ofs = 0x30,
 504 +};
 505 +
 506 +static const struct mtk_gate ssusb_clks[] = {
 507 +       GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
 508 +                  "to_u2_phy_1p", 0),
 509 +       GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
 510 +       GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
 511 +       GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
 512 +       GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
 513 +       GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
 514 +};
 515 +
 516 +static const struct mtk_gate pcie_clks[] = {
 517 +       GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
 518 +       GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
 519 +       GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
 520 +       GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
 521 +       GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
 522 +       GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
 523 +       GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
 524 +       GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
 525 +       GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
 526 +       GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
 527 +       GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
 528 +       GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
 529 +       GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
 530 +       GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
 531 +       GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
 532 +       GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
 533 +       GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
 534 +};
 535 +
 536 +static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 537 +{
 538 +       struct clk_onecell_data *clk_data;
 539 +       struct device_node *node = pdev->dev.of_node;
 540 +       int r;
 541 +
 542 +       clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
 543 +
 544 +       mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
 545 +                              clk_data);
 546 +
 547 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 548 +       if (r)
 549 +               dev_err(&pdev->dev,
 550 +                       "could not register clock provider: %s: %d\n",
 551 +                       pdev->name, r);
 552 +
 553 +       mtk_register_reset_controller(node, 1, 0x34);
 554 +
 555 +       return r;
 556 +}
 557 +
 558 +static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 559 +{
 560 +       struct clk_onecell_data *clk_data;
 561 +       struct device_node *node = pdev->dev.of_node;
 562 +       int r;
 563 +
 564 +       clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 565 +
 566 +       mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
 567 +                              clk_data);
 568 +
 569 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 570 +       if (r)
 571 +               dev_err(&pdev->dev,
 572 +                       "could not register clock provider: %s: %d\n",
 573 +                       pdev->name, r);
 574 +
 575 +       mtk_register_reset_controller(node, 1, 0x34);
 576 +
 577 +       return r;
 578 +}
 579 +
 580 +static const struct of_device_id of_match_clk_mt7622_hif[] = {
 581 +       {
 582 +               .compatible = "mediatek,mt7622-pciesys",
 583 +               .data = clk_mt7622_pciesys_init,
 584 +       }, {
 585 +               .compatible = "mediatek,mt7622-ssusbsys",
 586 +               .data = clk_mt7622_ssusbsys_init,
 587 +       }, {
 588 +               /* sentinel */
 589 +       }
 590 +};
 591 +
 592 +static int clk_mt7622_hif_probe(struct platform_device *pdev)
 593 +{
 594 +       int (*clk_init)(struct platform_device *);
 595 +       int r;
 596 +
 597 +       clk_init = of_device_get_match_data(&pdev->dev);
 598 +       if (!clk_init)
 599 +               return -EINVAL;
 600 +
 601 +       r = clk_init(pdev);
 602 +       if (r)
 603 +               dev_err(&pdev->dev,
 604 +                       "could not register clock provider: %s: %d\n",
 605 +                       pdev->name, r);
 606 +
 607 +       return r;
 608 +}
 609 +
 610 +static struct platform_driver clk_mt7622_hif_drv = {
 611 +       .probe = clk_mt7622_hif_probe,
 612 +       .driver = {
 613 +               .name = "clk-mt7622-hif",
 614 +               .of_match_table = of_match_clk_mt7622_hif,
 615 +       },
 616 +};
 617 +
 618 +builtin_platform_driver(clk_mt7622_hif_drv);
 619 diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
 620 new file mode 100644
 621 index 000000000000..92f7e32770c6
 622 --- /dev/null
 623 +++ b/drivers/clk/mediatek/clk-mt7622.c
 624 @@ -0,0 +1,780 @@
 625 +/*
 626 + * Copyright (c) 2017 MediaTek Inc.
 627 + * Author: Chen Zhong <chen.zhong@mediatek.com>
 628 + *        Sean Wang <sean.wang@mediatek.com>
 629 + *
 630 + * This program is free software; you can redistribute it and/or modify
 631 + * it under the terms of the GNU General Public License version 2 as
 632 + * published by the Free Software Foundation.
 633 + *
 634 + * This program is distributed in the hope that it will be useful,
 635 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 636 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 637 + * GNU General Public License for more details.
 638 + */
 639 +
 640 +#include <linux/clk-provider.h>
 641 +#include <linux/of.h>
 642 +#include <linux/of_address.h>
 643 +#include <linux/of_device.h>
 644 +#include <linux/platform_device.h>
 645 +
 646 +#include "clk-mtk.h"
 647 +#include "clk-gate.h"
 648 +#include "clk-cpumux.h"
 649 +
 650 +#include <dt-bindings/clock/mt7622-clk.h>
 651 +#include <linux/clk.h> /* for consumer */
 652 +
 653 +#define MT7622_PLL_FMAX                (2500UL * MHZ)
 654 +#define CON0_MT7622_RST_BAR    BIT(27)
 655 +
 656 +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
 657 +                       _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
 658 +                       _pcw_shift, _div_table, _parent_name) {         \
 659 +               .id = _id,                                              \
 660 +               .name = _name,                                          \
 661 +               .reg = _reg,                                            \
 662 +               .pwr_reg = _pwr_reg,                                    \
 663 +               .en_mask = _en_mask,                                    \
 664 +               .flags = _flags,                                        \
 665 +               .rst_bar_mask = CON0_MT7622_RST_BAR,                    \
 666 +               .fmax = MT7622_PLL_FMAX,                                \
 667 +               .pcwbits = _pcwbits,                                    \
 668 +               .pd_reg = _pd_reg,                                      \
 669 +               .pd_shift = _pd_shift,                                  \
 670 +               .tuner_reg = _tuner_reg,                                \
 671 +               .pcw_reg = _pcw_reg,                                    \
 672 +               .pcw_shift = _pcw_shift,                                \
 673 +               .div_table = _div_table,                                \
 674 +               .parent_name = _parent_name,                            \
 675 +       }
 676 +
 677 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,    \
 678 +                       _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
 679 +                       _pcw_shift)                                     \
 680 +       PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
 681 +                _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,  \
 682 +                NULL, "clkxtal")
 683 +
 684 +#define GATE_APMIXED(_id, _name, _parent, _shift) {                    \
 685 +               .id = _id,                                              \
 686 +               .name = _name,                                          \
 687 +               .parent_name = _parent,                                 \
 688 +               .regs = &apmixed_cg_regs,                               \
 689 +               .shift = _shift,                                        \
 690 +               .ops = &mtk_clk_gate_ops_no_setclr_inv,                 \
 691 +       }
 692 +
 693 +#define GATE_INFRA(_id, _name, _parent, _shift) {                      \
 694 +               .id = _id,                                              \
 695 +               .name = _name,                                          \
 696 +               .parent_name = _parent,                                 \
 697 +               .regs = &infra_cg_regs,                                 \
 698 +               .shift = _shift,                                        \
 699 +               .ops = &mtk_clk_gate_ops_setclr,                        \
 700 +       }
 701 +
 702 +#define GATE_TOP0(_id, _name, _parent, _shift) {                       \
 703 +               .id = _id,                                              \
 704 +               .name = _name,                                          \
 705 +               .parent_name = _parent,                                 \
 706 +               .regs = &top0_cg_regs,                                  \
 707 +               .shift = _shift,                                        \
 708 +               .ops = &mtk_clk_gate_ops_no_setclr,                     \
 709 +       }
 710 +
 711 +#define GATE_TOP1(_id, _name, _parent, _shift) {                       \
 712 +               .id = _id,                                              \
 713 +               .name = _name,                                          \
 714 +               .parent_name = _parent,                                 \
 715 +               .regs = &top1_cg_regs,                                  \
 716 +               .shift = _shift,                                        \
 717 +               .ops = &mtk_clk_gate_ops_no_setclr,                     \
 718 +       }
 719 +
 720 +#define GATE_PERI0(_id, _name, _parent, _shift) {                      \
 721 +               .id = _id,                                              \
 722 +               .name = _name,                                          \
 723 +               .parent_name = _parent,                                 \
 724 +               .regs = &peri0_cg_regs,                                 \
 725 +               .shift = _shift,                                        \
 726 +               .ops = &mtk_clk_gate_ops_setclr,                        \
 727 +       }
 728 +
 729 +#define GATE_PERI1(_id, _name, _parent, _shift) {                      \
 730 +               .id = _id,                                              \
 731 +               .name = _name,                                          \
 732 +               .parent_name = _parent,                                 \
 733 +               .regs = &peri1_cg_regs,                                 \
 734 +               .shift = _shift,                                        \
 735 +               .ops = &mtk_clk_gate_ops_setclr,                        \
 736 +       }
 737 +
 738 +static DEFINE_SPINLOCK(mt7622_clk_lock);
 739 +
 740 +static const char * const infra_mux1_parents[] = {
 741 +       "clkxtal",
 742 +       "armpll",
 743 +       "main_core_en",
 744 +       "armpll"
 745 +};
 746 +
 747 +static const char * const axi_parents[] = {
 748 +       "clkxtal",
 749 +       "syspll1_d2",
 750 +       "syspll_d5",
 751 +       "syspll1_d4",
 752 +       "univpll_d5",
 753 +       "univpll2_d2",
 754 +       "univpll_d7"
 755 +};
 756 +
 757 +static const char * const mem_parents[] = {
 758 +       "clkxtal",
 759 +       "dmpll_ck"
 760 +};
 761 +
 762 +static const char * const ddrphycfg_parents[] = {
 763 +       "clkxtal",
 764 +       "syspll1_d8"
 765 +};
 766 +
 767 +static const char * const eth_parents[] = {
 768 +       "clkxtal",
 769 +       "syspll1_d2",
 770 +       "univpll1_d2",
 771 +       "syspll1_d4",
 772 +       "univpll_d5",
 773 +       "clk_null",
 774 +       "univpll_d7"
 775 +};
 776 +
 777 +static const char * const pwm_parents[] = {
 778 +       "clkxtal",
 779 +       "univpll2_d4"
 780 +};
 781 +
 782 +static const char * const f10m_ref_parents[] = {
 783 +       "clkxtal",
 784 +       "syspll4_d16"
 785 +};
 786 +
 787 +static const char * const nfi_infra_parents[] = {
 788 +       "clkxtal",
 789 +       "clkxtal",
 790 +       "clkxtal",
 791 +       "clkxtal",
 792 +       "clkxtal",
 793 +       "clkxtal",
 794 +       "clkxtal",
 795 +       "clkxtal",
 796 +       "univpll2_d8",
 797 +       "syspll1_d8",
 798 +       "univpll1_d8",
 799 +       "syspll4_d2",
 800 +       "univpll2_d4",
 801 +       "univpll3_d2",
 802 +       "syspll1_d4"
 803 +};
 804 +
 805 +static const char * const flash_parents[] = {
 806 +       "clkxtal",
 807 +       "univpll_d80_d4",
 808 +       "syspll2_d8",
 809 +       "syspll3_d4",
 810 +       "univpll3_d4",
 811 +       "univpll1_d8",
 812 +       "syspll2_d4",
 813 +       "univpll2_d4"
 814 +};
 815 +
 816 +static const char * const uart_parents[] = {
 817 +       "clkxtal",
 818 +       "univpll2_d8"
 819 +};
 820 +
 821 +static const char * const spi0_parents[] = {
 822 +       "clkxtal",
 823 +       "syspll3_d2",
 824 +       "clkxtal",
 825 +       "syspll2_d4",
 826 +       "syspll4_d2",
 827 +       "univpll2_d4",
 828 +       "univpll1_d8",
 829 +       "clkxtal"
 830 +};
 831 +
 832 +static const char * const spi1_parents[] = {
 833 +       "clkxtal",
 834 +       "syspll3_d2",
 835 +       "clkxtal",
 836 +       "syspll4_d4",
 837 +       "syspll4_d2",
 838 +       "univpll2_d4",
 839 +       "univpll1_d8",
 840 +       "clkxtal"
 841 +};
 842 +
 843 +static const char * const msdc30_0_parents[] = {
 844 +       "clkxtal",
 845 +       "univpll2_d16",
 846 +       "univ48m"
 847 +};
 848 +
 849 +static const char * const a1sys_hp_parents[] = {
 850 +       "clkxtal",
 851 +       "aud1pll_ck",
 852 +       "aud2pll_ck",
 853 +       "clkxtal"
 854 +};
 855 +
 856 +static const char * const intdir_parents[] = {
 857 +       "clkxtal",
 858 +       "syspll_d2",
 859 +       "univpll_d2",
 860 +       "sgmiipll_ck"
 861 +};
 862 +
 863 +static const char * const aud_intbus_parents[] = {
 864 +       "clkxtal",
 865 +       "syspll1_d4",
 866 +       "syspll4_d2",
 867 +       "syspll3_d2"
 868 +};
 869 +
 870 +static const char * const pmicspi_parents[] = {
 871 +       "clkxtal",
 872 +       "clk_null",
 873 +       "clk_null",
 874 +       "clk_null",
 875 +       "clk_null",
 876 +       "univpll2_d16"
 877 +};
 878 +
 879 +static const char * const atb_parents[] = {
 880 +       "clkxtal",
 881 +       "syspll1_d2",
 882 +       "syspll_d5"
 883 +};
 884 +
 885 +static const char * const audio_parents[] = {
 886 +       "clkxtal",
 887 +       "syspll3_d4",
 888 +       "syspll4_d4",
 889 +       "univpll1_d16"
 890 +};
 891 +
 892 +static const char * const usb20_parents[] = {
 893 +       "clkxtal",
 894 +       "univpll3_d4",
 895 +       "syspll1_d8",
 896 +       "clkxtal"
 897 +};
 898 +
 899 +static const char * const aud1_parents[] = {
 900 +       "clkxtal",
 901 +       "aud1pll_ck"
 902 +};
 903 +
 904 +static const char * const aud2_parents[] = {
 905 +       "clkxtal",
 906 +       "aud2pll_ck"
 907 +};
 908 +
 909 +static const char * const asm_l_parents[] = {
 910 +       "clkxtal",
 911 +       "syspll_d5",
 912 +       "univpll2_d2",
 913 +       "univpll2_d4"
 914 +};
 915 +
 916 +static const char * const apll1_ck_parents[] = {
 917 +       "aud1_sel",
 918 +       "aud2_sel"
 919 +};
 920 +
 921 +static const char * const peribus_ck_parents[] = {
 922 +       "syspll1_d8",
 923 +       "syspll1_d4"
 924 +};
 925 +
 926 +static const struct mtk_gate_regs apmixed_cg_regs = {
 927 +       .set_ofs = 0x8,
 928 +       .clr_ofs = 0x8,
 929 +       .sta_ofs = 0x8,
 930 +};
 931 +
 932 +static const struct mtk_gate_regs infra_cg_regs = {
 933 +       .set_ofs = 0x40,
 934 +       .clr_ofs = 0x44,
 935 +       .sta_ofs = 0x48,
 936 +};
 937 +
 938 +static const struct mtk_gate_regs top0_cg_regs = {
 939 +       .set_ofs = 0x120,
 940 +       .clr_ofs = 0x120,
 941 +       .sta_ofs = 0x120,
 942 +};
 943 +
 944 +static const struct mtk_gate_regs top1_cg_regs = {
 945 +       .set_ofs = 0x128,
 946 +       .clr_ofs = 0x128,
 947 +       .sta_ofs = 0x128,
 948 +};
 949 +
 950 +static const struct mtk_gate_regs peri0_cg_regs = {
 951 +       .set_ofs = 0x8,
 952 +       .clr_ofs = 0x10,
 953 +       .sta_ofs = 0x18,
 954 +};
 955 +
 956 +static const struct mtk_gate_regs peri1_cg_regs = {
 957 +       .set_ofs = 0xC,
 958 +       .clr_ofs = 0x14,
 959 +       .sta_ofs = 0x1C,
 960 +};
 961 +
 962 +static const struct mtk_pll_data plls[] = {
 963 +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
 964 +           PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
 965 +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
 966 +           HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
 967 +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
 968 +           HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
 969 +       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
 970 +           0, 21, 0x0300, 1, 0, 0x0304, 0),
 971 +       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
 972 +           0, 21, 0x0314, 1, 0, 0x0318, 0),
 973 +       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
 974 +           0, 31, 0x0324, 1, 0, 0x0328, 0),
 975 +       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
 976 +           0, 31, 0x0334, 1, 0, 0x0338, 0),
 977 +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
 978 +           0, 21, 0x0344, 1, 0, 0x0348, 0),
 979 +       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
 980 +           0, 21, 0x0358, 1, 0, 0x035C, 0),
 981 +};
 982 +
 983 +static const struct mtk_gate apmixed_clks[] = {
 984 +       GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
 985 +};
 986 +
 987 +static const struct mtk_gate infra_clks[] = {
 988 +       GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
 989 +       GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
 990 +       GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
 991 +       GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
 992 +       GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
 993 +       GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
 994 +};
 995 +
 996 +static const struct mtk_fixed_clk top_fixed_clks[] = {
 997 +       FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
 998 +                 31250000),
 999 +       FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
1000 +                 31250000),
1001 +       FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
1002 +                 125000000),
1003 +       FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
1004 +                 125000000),
1005 +       FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
1006 +                 250000000),
1007 +       FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
1008 +                 250000000),
1009 +       FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
1010 +                 33333333),
1011 +       FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
1012 +                 50000000),
1013 +       FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
1014 +                 50000000),
1015 +       FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
1016 +                 50000000),
1017 +};
1018 +
1019 +static const struct mtk_fixed_factor top_divs[] = {
1020 +       FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
1021 +       FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
1022 +       FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
1023 +       FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
1024 +       FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
1025 +       FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
1026 +       FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
1027 +       FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
1028 +       FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
1029 +       FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
1030 +       FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
1031 +       FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
1032 +       FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
1033 +       FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
1034 +       FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
1035 +       FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
1036 +       FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
1037 +       FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
1038 +       FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
1039 +       FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
1040 +       FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
1041 +       FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
1042 +       FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
1043 +       FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
1044 +       FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
1045 +       FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
1046 +       FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
1047 +       FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
1048 +       FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
1049 +       FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
1050 +       FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
1051 +       FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
1052 +       FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
1053 +       FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
1054 +       FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
1055 +       FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
1056 +       FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
1057 +       FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
1058 +       FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
1059 +       FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
1060 +       FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
1061 +       FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
1062 +       FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
1063 +       FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
1064 +       FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
1065 +       FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
1066 +};
1067 +
1068 +static const struct mtk_gate top_clks[] = {
1069 +       /* TOP0 */
1070 +       GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
1071 +       GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
1072 +       GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
1073 +                 2),
1074 +       GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
1075 +                 3),
1076 +       GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
1077 +                 4),
1078 +       GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
1079 +                 5),
1080 +
1081 +       /* TOP1 */
1082 +       GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
1083 +       GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
1084 +};
1085 +
1086 +static const struct mtk_clk_divider top_adj_divs[] = {
1087 +       DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
1088 +               0x120, 24, 3),
1089 +       DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
1090 +               0x120, 28, 3),
1091 +       DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
1092 +               0x124, 0, 7),
1093 +       DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
1094 +               0x124, 8, 7),
1095 +       DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
1096 +               0x124, 16, 7),
1097 +       DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
1098 +               0x124, 24, 7),
1099 +       DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
1100 +               0x128, 8, 7),
1101 +       DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
1102 +               0x128, 24, 7),
1103 +};
1104 +
1105 +static const struct mtk_gate peri_clks[] = {
1106 +       /* PERI0 */
1107 +       GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
1108 +       GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
1109 +       GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
1110 +       GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
1111 +       GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
1112 +       GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
1113 +       GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
1114 +       GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
1115 +       GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
1116 +       GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
1117 +       GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
1118 +       GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
1119 +       GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
1120 +       GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
1121 +       GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
1122 +       GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
1123 +       GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
1124 +       GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
1125 +       GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
1126 +       GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
1127 +       GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
1128 +       GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
1129 +       GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
1130 +       GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
1131 +       GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
1132 +       GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
1133 +       GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
1134 +
1135 +       /* PERI1 */
1136 +       GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
1137 +       GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
1138 +};
1139 +
1140 +static struct mtk_composite infra_muxes[] __initdata = {
1141 +       MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
1142 +           0x000, 2, 2),
1143 +};
1144 +
1145 +static struct mtk_composite top_muxes[] = {
1146 +       /* CLK_CFG_0 */
1147 +       MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
1148 +                0x040, 0, 3, 7),
1149 +       MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
1150 +                0x040, 8, 1, 15),
1151 +       MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
1152 +                0x040, 16, 1, 23),
1153 +       MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
1154 +                0x040, 24, 3, 31),
1155 +
1156 +       /* CLK_CFG_1 */
1157 +       MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
1158 +                0x050, 0, 2, 7),
1159 +       MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
1160 +                0x050, 8, 1, 15),
1161 +       MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
1162 +                0x050, 16, 4, 23),
1163 +       MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
1164 +                0x050, 24, 3, 31),
1165 +
1166 +       /* CLK_CFG_2 */
1167 +       MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
1168 +                0x060, 0, 1, 7),
1169 +       MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
1170 +                0x060, 8, 3, 15),
1171 +       MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
1172 +                0x060, 16, 3, 23),
1173 +       MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
1174 +                0x060, 24, 3, 31),
1175 +
1176 +       /* CLK_CFG_3 */
1177 +       MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
1178 +                0x070, 0, 3, 7),
1179 +       MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
1180 +                0x070, 8, 3, 15),
1181 +       MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
1182 +                0x070, 16, 2, 23),
1183 +       MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
1184 +                0x070, 24, 2, 31),
1185 +
1186 +       /* CLK_CFG_4 */
1187 +       MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
1188 +                0x080, 0, 2, 7),
1189 +       MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
1190 +                0x080, 8, 2, 15),
1191 +       MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
1192 +                0x080, 16, 3, 23),
1193 +       MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
1194 +                0x080, 24, 2, 31),
1195 +
1196 +       /* CLK_CFG_5 */
1197 +       MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
1198 +                0x090, 0, 2, 7),
1199 +       MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
1200 +                0x090, 8, 3, 15),
1201 +       MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
1202 +                0x090, 16, 2, 23),
1203 +       MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
1204 +                0x090, 24, 2, 31),
1205 +
1206 +       /* CLK_CFG_6 */
1207 +       MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
1208 +                0x0A0, 0, 1, 7),
1209 +       MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
1210 +                0x0A0, 8, 1, 15),
1211 +       MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
1212 +                0x0A0, 16, 1, 23),
1213 +       MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
1214 +                0x0A0, 24, 1, 31),
1215 +
1216 +       /* CLK_CFG_7 */
1217 +       MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
1218 +                0x0B0, 0, 2, 7),
1219 +       MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
1220 +                0x0B0, 8, 2, 15),
1221 +       MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
1222 +                0x0B0, 16, 2, 23),
1223 +
1224 +       /* CLK_AUDDIV_0 */
1225 +       MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
1226 +           0x120, 6, 1),
1227 +       MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
1228 +           0x120, 7, 1),
1229 +       MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
1230 +           0x120, 8, 1),
1231 +       MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
1232 +           0x120, 9, 1),
1233 +       MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
1234 +           0x120, 10, 1),
1235 +       MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
1236 +           0x120, 11, 1),
1237 +};
1238 +
1239 +static struct mtk_composite peri_muxes[] = {
1240 +       /* PERI_GLOBALCON_CKSEL */
1241 +       MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
1242 +};
1243 +
1244 +static int mtk_topckgen_init(struct platform_device *pdev)
1245 +{
1246 +       struct clk_onecell_data *clk_data;
1247 +       void __iomem *base;
1248 +       struct device_node *node = pdev->dev.of_node;
1249 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 +
1251 +       base = devm_ioremap_resource(&pdev->dev, res);
1252 +       if (IS_ERR(base))
1253 +               return PTR_ERR(base);
1254 +
1255 +       clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1256 +
1257 +       mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1258 +                                   clk_data);
1259 +
1260 +       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
1261 +                                clk_data);
1262 +
1263 +       mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
1264 +                                   base, &mt7622_clk_lock, clk_data);
1265 +
1266 +       mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
1267 +                                 base, &mt7622_clk_lock, clk_data);
1268 +
1269 +       mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1270 +                              clk_data);
1271 +
1272 +       clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
1273 +       clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
1274 +       clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
1275 +
1276 +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1277 +}
1278 +
1279 +static int __init mtk_infrasys_init(struct platform_device *pdev)
1280 +{
1281 +       struct device_node *node = pdev->dev.of_node;
1282 +       struct clk_onecell_data *clk_data;
1283 +       int r;
1284 +
1285 +       clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1286 +
1287 +       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1288 +                              clk_data);
1289 +
1290 +       mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
1291 +                                 clk_data);
1292 +
1293 +       r = of_clk_add_provider(node, of_clk_src_onecell_get,
1294 +                               clk_data);
1295 +       if (r)
1296 +               return r;
1297 +
1298 +       mtk_register_reset_controller(node, 1, 0x30);
1299 +
1300 +       return 0;
1301 +}
1302 +
1303 +static int mtk_apmixedsys_init(struct platform_device *pdev)
1304 +{
1305 +       struct clk_onecell_data *clk_data;
1306 +       struct device_node *node = pdev->dev.of_node;
1307 +
1308 +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1309 +       if (!clk_data)
1310 +               return -ENOMEM;
1311 +
1312 +       mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
1313 +                             clk_data);
1314 +
1315 +       mtk_clk_register_gates(node, apmixed_clks,
1316 +                              ARRAY_SIZE(apmixed_clks), clk_data);
1317 +
1318 +       clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
1319 +       clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
1320 +
1321 +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1322 +}
1323 +
1324 +static int mtk_pericfg_init(struct platform_device *pdev)
1325 +{
1326 +       struct clk_onecell_data *clk_data;
1327 +       void __iomem *base;
1328 +       int r;
1329 +       struct device_node *node = pdev->dev.of_node;
1330 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 +
1332 +       base = devm_ioremap_resource(&pdev->dev, res);
1333 +       if (IS_ERR(base))
1334 +               return PTR_ERR(base);
1335 +
1336 +       clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1337 +
1338 +       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1339 +                              clk_data);
1340 +
1341 +       mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
1342 +                                   &mt7622_clk_lock, clk_data);
1343 +
1344 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1345 +       if (r)
1346 +               return r;
1347 +
1348 +       clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
1349 +
1350 +       mtk_register_reset_controller(node, 2, 0x0);
1351 +
1352 +       return 0;
1353 +}
1354 +
1355 +static const struct of_device_id of_match_clk_mt7622[] = {
1356 +       {
1357 +               .compatible = "mediatek,mt7622-apmixedsys",
1358 +               .data = mtk_apmixedsys_init,
1359 +       }, {
1360 +               .compatible = "mediatek,mt7622-infracfg",
1361 +               .data = mtk_infrasys_init,
1362 +       }, {
1363 +               .compatible = "mediatek,mt7622-topckgen",
1364 +               .data = mtk_topckgen_init,
1365 +       }, {
1366 +               .compatible = "mediatek,mt7622-pericfg",
1367 +               .data = mtk_pericfg_init,
1368 +       }, {
1369 +               /* sentinel */
1370 +       }
1371 +};
1372 +
1373 +static int clk_mt7622_probe(struct platform_device *pdev)
1374 +{
1375 +       int (*clk_init)(struct platform_device *);
1376 +       int r;
1377 +
1378 +       clk_init = of_device_get_match_data(&pdev->dev);
1379 +       if (!clk_init)
1380 +               return -EINVAL;
1381 +
1382 +       r = clk_init(pdev);
1383 +       if (r)
1384 +               dev_err(&pdev->dev,
1385 +                       "could not register clock provider: %s: %d\n",
1386 +                       pdev->name, r);
1387 +
1388 +       return r;
1389 +}
1390 +
1391 +static struct platform_driver clk_mt7622_drv = {
1392 +       .probe = clk_mt7622_probe,
1393 +       .driver = {
1394 +               .name = "clk-mt7622",
1395 +               .of_match_table = of_match_clk_mt7622,
1396 +       },
1397 +};
1398 +
1399 +static int clk_mt7622_init(void)
1400 +{
1401 +       return platform_driver_register(&clk_mt7622_drv);
1402 +}
1403 +
1404 +arch_initcall(clk_mt7622_init);
1405 --
1406 2.11.0
1407