target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch

   1 From acfa4eba7a4391d443b33a3d90a07eae0ef2ebca Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 5 Oct 2017 11:50:22 +0800
   4 Subject: [PATCH 147/224] dt-bindings: clock: mediatek: document clk bindings
   5  for MediaTek MT7622 SoC
   6
   7 This patch adds the binding documentation for apmixedsys, ethsys, hifsys,
   8 infracfg, pericfg, topckgen and audsys for MT7622.
   9
  10 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
  11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  12 Acked-by: Rob Herring <robh@kernel.org>
  13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  14 ---
  15  .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
  16  .../bindings/arm/mediatek/mediatek,audsys.txt      | 22 ++++++++++++++++++++++
  17  .../bindings/arm/mediatek/mediatek,ethsys.txt      |  1 +
  18  .../bindings/arm/mediatek/mediatek,hifsys.txt      |  1 +
  19  .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
  20  .../bindings/arm/mediatek/mediatek,pciesys.txt     | 22 ++++++++++++++++++++++
  21  .../bindings/arm/mediatek/mediatek,pericfg.txt     |  1 +
  22  .../bindings/arm/mediatek/mediatek,sgmiisys.txt    | 22 ++++++++++++++++++++++
  23  .../bindings/arm/mediatek/mediatek,ssusbsys.txt    | 22 ++++++++++++++++++++++
  24  .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
  25  10 files changed, 94 insertions(+)
  26  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
  27  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
  28  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
  29  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
  30
  31 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  32 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  33 @@ -9,6 +9,7 @@ Required Properties:
  34         - "mediatek,mt2701-apmixedsys"
  35         - "mediatek,mt2712-apmixedsys", "syscon"
  36         - "mediatek,mt6797-apmixedsys"
  37 +       - "mediatek,mt7622-apmixedsys"
  38         - "mediatek,mt8135-apmixedsys"
  39         - "mediatek,mt8173-apmixedsys"
  40  - #clock-cells: Must be 1
  41 --- /dev/null
  42 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
  43 @@ -0,0 +1,22 @@
  44 +MediaTek AUDSYS controller
  45 +============================
  46 +
  47 +The MediaTek AUDSYS controller provides various clocks to the system.
  48 +
  49 +Required Properties:
  50 +
  51 +- compatible: Should be one of:
  52 +       - "mediatek,mt7622-audsys", "syscon"
  53 +- #clock-cells: Must be 1
  54 +
  55 +The AUDSYS controller uses the common clk binding from
  56 +Documentation/devicetree/bindings/clock/clock-bindings.txt
  57 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  58 +
  59 +Example:
  60 +
  61 +audsys: audsys@11220000 {
  62 +       compatible = "mediatek,mt7622-audsys", "syscon";
  63 +       reg = <0 0x11220000 0 0x1000>;
  64 +       #clock-cells = <1>;
  65 +};
  66 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  67 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  68 @@ -7,6 +7,7 @@ Required Properties:
  69
  70  - compatible: Should be:
  71         - "mediatek,mt2701-ethsys", "syscon"
  72 +       - "mediatek,mt7622-ethsys", "syscon"
  73  - #clock-cells: Must be 1
  74
  75  The ethsys controller uses the common clk binding from
  76 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
  77 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
  78 @@ -8,6 +8,7 @@ Required Properties:
  79
  80  - compatible: Should be:
  81         - "mediatek,mt2701-hifsys", "syscon"
  82 +       - "mediatek,mt7622-hifsys", "syscon"
  83  - #clock-cells: Must be 1
  84
  85  The hifsys controller uses the common clk binding from
  86 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  87 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  88 @@ -10,6 +10,7 @@ Required Properties:
  89         - "mediatek,mt2701-infracfg", "syscon"
  90         - "mediatek,mt2712-infracfg", "syscon"
  91         - "mediatek,mt6797-infracfg", "syscon"
  92 +       - "mediatek,mt7622-infracfg", "syscon"
  93         - "mediatek,mt8135-infracfg", "syscon"
  94         - "mediatek,mt8173-infracfg", "syscon"
  95  - #clock-cells: Must be 1
  96 --- /dev/null
  97 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
  98 @@ -0,0 +1,22 @@
  99 +MediaTek PCIESYS controller
 100 +============================
 101 +
 102 +The MediaTek PCIESYS controller provides various clocks to the system.
 103 +
 104 +Required Properties:
 105 +
 106 +- compatible: Should be:
 107 +       - "mediatek,mt7622-pciesys", "syscon"
 108 +- #clock-cells: Must be 1
 109 +
 110 +The PCIESYS controller uses the common clk binding from
 111 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 112 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 113 +
 114 +Example:
 115 +
 116 +pciesys: pciesys@1a100800 {
 117 +       compatible = "mediatek,mt7622-pciesys", "syscon";
 118 +       reg = <0 0x1a100800 0 0x1000>;
 119 +       #clock-cells = <1>;
 120 +};
 121 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 122 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 123 @@ -9,6 +9,7 @@ Required Properties:
 124  - compatible: Should be one of:
 125         - "mediatek,mt2701-pericfg", "syscon"
 126         - "mediatek,mt2712-pericfg", "syscon"
 127 +       - "mediatek,mt7622-pericfg", "syscon"
 128         - "mediatek,mt8135-pericfg", "syscon"
 129         - "mediatek,mt8173-pericfg", "syscon"
 130  - #clock-cells: Must be 1
 131 --- /dev/null
 132 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
 133 @@ -0,0 +1,22 @@
 134 +MediaTek SGMIISYS controller
 135 +============================
 136 +
 137 +The MediaTek SGMIISYS controller provides various clocks to the system.
 138 +
 139 +Required Properties:
 140 +
 141 +- compatible: Should be:
 142 +       - "mediatek,mt7622-sgmiisys", "syscon"
 143 +- #clock-cells: Must be 1
 144 +
 145 +The SGMIISYS controller uses the common clk binding from
 146 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 147 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 148 +
 149 +Example:
 150 +
 151 +sgmiisys: sgmiisys@1b128000 {
 152 +       compatible = "mediatek,mt7622-sgmiisys", "syscon";
 153 +       reg = <0 0x1b128000 0 0x1000>;
 154 +       #clock-cells = <1>;
 155 +};
 156 --- /dev/null
 157 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
 158 @@ -0,0 +1,22 @@
 159 +MediaTek SSUSBSYS controller
 160 +============================
 161 +
 162 +The MediaTek SSUSBSYS controller provides various clocks to the system.
 163 +
 164 +Required Properties:
 165 +
 166 +- compatible: Should be:
 167 +       - "mediatek,mt7622-ssusbsys", "syscon"
 168 +- #clock-cells: Must be 1
 169 +
 170 +The SSUSBSYS controller uses the common clk binding from
 171 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 172 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 173 +
 174 +Example:
 175 +
 176 +ssusbsys: ssusbsys@1a000000 {
 177 +       compatible = "mediatek,mt7622-ssusbsys", "syscon";
 178 +       reg = <0 0x1a000000 0 0x1000>;
 179 +       #clock-cells = <1>;
 180 +};
 181 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 182 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 183 @@ -9,6 +9,7 @@ Required Properties:
 184         - "mediatek,mt2701-topckgen"
 185         - "mediatek,mt2712-topckgen", "syscon"
 186         - "mediatek,mt6797-topckgen"
 187 +       - "mediatek,mt7622-topckgen"
 188         - "mediatek,mt8135-topckgen"
 189         - "mediatek,mt8173-topckgen"
 190  - #clock-cells: Must be 1