1 From 8a64bf0c04a4b7670cf56be5b0ae63fe9d6ecd56 Mon Sep 17 00:00:00 2001
2 From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
3 Date: Mon, 23 Oct 2017 12:10:33 +0800
4 Subject: [PATCH 145/224] clk: mediatek: Add dt-bindings for MT2712 clocks
6 Add MT2712 clock dt-bindings, include topckgen, apmixedsys,
7 infracfg, pericfg, mcucfg and subsystem clocks.
9 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
10 Acked-by: Rob Herring <robh@kernel.org>
11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
13 include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++
14 1 file changed, 427 insertions(+)
15 create mode 100644 include/dt-bindings/clock/mt2712-clk.h
18 +++ b/include/dt-bindings/clock/mt2712-clk.h
21 + * Copyright (c) 2017 MediaTek Inc.
22 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
24 + * This program is free software; you can redistribute it and/or modify
25 + * it under the terms of the GNU General Public License version 2 as
26 + * published by the Free Software Foundation.
28 + * This program is distributed in the hope that it will be useful,
29 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 + * GNU General Public License for more details.
34 +#ifndef _DT_BINDINGS_CLK_MT2712_H
35 +#define _DT_BINDINGS_CLK_MT2712_H
39 +#define CLK_APMIXED_MAINPLL 0
40 +#define CLK_APMIXED_UNIVPLL 1
41 +#define CLK_APMIXED_VCODECPLL 2
42 +#define CLK_APMIXED_VENCPLL 3
43 +#define CLK_APMIXED_APLL1 4
44 +#define CLK_APMIXED_APLL2 5
45 +#define CLK_APMIXED_LVDSPLL 6
46 +#define CLK_APMIXED_LVDSPLL2 7
47 +#define CLK_APMIXED_MSDCPLL 8
48 +#define CLK_APMIXED_MSDCPLL2 9
49 +#define CLK_APMIXED_TVDPLL 10
50 +#define CLK_APMIXED_MMPLL 11
51 +#define CLK_APMIXED_ARMCA35PLL 12
52 +#define CLK_APMIXED_ARMCA72PLL 13
53 +#define CLK_APMIXED_ETHERPLL 14
54 +#define CLK_APMIXED_NR_CLK 15
58 +#define CLK_TOP_ARMCA35PLL 0
59 +#define CLK_TOP_ARMCA35PLL_600M 1
60 +#define CLK_TOP_ARMCA35PLL_400M 2
61 +#define CLK_TOP_ARMCA72PLL 3
62 +#define CLK_TOP_SYSPLL 4
63 +#define CLK_TOP_SYSPLL_D2 5
64 +#define CLK_TOP_SYSPLL1_D2 6
65 +#define CLK_TOP_SYSPLL1_D4 7
66 +#define CLK_TOP_SYSPLL1_D8 8
67 +#define CLK_TOP_SYSPLL1_D16 9
68 +#define CLK_TOP_SYSPLL_D3 10
69 +#define CLK_TOP_SYSPLL2_D2 11
70 +#define CLK_TOP_SYSPLL2_D4 12
71 +#define CLK_TOP_SYSPLL_D5 13
72 +#define CLK_TOP_SYSPLL3_D2 14
73 +#define CLK_TOP_SYSPLL3_D4 15
74 +#define CLK_TOP_SYSPLL_D7 16
75 +#define CLK_TOP_SYSPLL4_D2 17
76 +#define CLK_TOP_SYSPLL4_D4 18
77 +#define CLK_TOP_UNIVPLL 19
78 +#define CLK_TOP_UNIVPLL_D7 20
79 +#define CLK_TOP_UNIVPLL_D26 21
80 +#define CLK_TOP_UNIVPLL_D52 22
81 +#define CLK_TOP_UNIVPLL_D104 23
82 +#define CLK_TOP_UNIVPLL_D208 24
83 +#define CLK_TOP_UNIVPLL_D2 25
84 +#define CLK_TOP_UNIVPLL1_D2 26
85 +#define CLK_TOP_UNIVPLL1_D4 27
86 +#define CLK_TOP_UNIVPLL1_D8 28
87 +#define CLK_TOP_UNIVPLL_D3 29
88 +#define CLK_TOP_UNIVPLL2_D2 30
89 +#define CLK_TOP_UNIVPLL2_D4 31
90 +#define CLK_TOP_UNIVPLL2_D8 32
91 +#define CLK_TOP_UNIVPLL_D5 33
92 +#define CLK_TOP_UNIVPLL3_D2 34
93 +#define CLK_TOP_UNIVPLL3_D4 35
94 +#define CLK_TOP_UNIVPLL3_D8 36
95 +#define CLK_TOP_F_MP0_PLL1 37
96 +#define CLK_TOP_F_MP0_PLL2 38
97 +#define CLK_TOP_F_BIG_PLL1 39
98 +#define CLK_TOP_F_BIG_PLL2 40
99 +#define CLK_TOP_F_BUS_PLL1 41
100 +#define CLK_TOP_F_BUS_PLL2 42
101 +#define CLK_TOP_APLL1 43
102 +#define CLK_TOP_APLL1_D2 44
103 +#define CLK_TOP_APLL1_D4 45
104 +#define CLK_TOP_APLL1_D8 46
105 +#define CLK_TOP_APLL1_D16 47
106 +#define CLK_TOP_APLL2 48
107 +#define CLK_TOP_APLL2_D2 49
108 +#define CLK_TOP_APLL2_D4 50
109 +#define CLK_TOP_APLL2_D8 51
110 +#define CLK_TOP_APLL2_D16 52
111 +#define CLK_TOP_LVDSPLL 53
112 +#define CLK_TOP_LVDSPLL_D2 54
113 +#define CLK_TOP_LVDSPLL_D4 55
114 +#define CLK_TOP_LVDSPLL_D8 56
115 +#define CLK_TOP_LVDSPLL2 57
116 +#define CLK_TOP_LVDSPLL2_D2 58
117 +#define CLK_TOP_LVDSPLL2_D4 59
118 +#define CLK_TOP_LVDSPLL2_D8 60
119 +#define CLK_TOP_ETHERPLL_125M 61
120 +#define CLK_TOP_ETHERPLL_50M 62
121 +#define CLK_TOP_CVBS 63
122 +#define CLK_TOP_CVBS_D2 64
123 +#define CLK_TOP_SYS_26M 65
124 +#define CLK_TOP_MMPLL 66
125 +#define CLK_TOP_MMPLL_D2 67
126 +#define CLK_TOP_VENCPLL 68
127 +#define CLK_TOP_VENCPLL_D2 69
128 +#define CLK_TOP_VCODECPLL 70
129 +#define CLK_TOP_VCODECPLL_D2 71
130 +#define CLK_TOP_TVDPLL 72
131 +#define CLK_TOP_TVDPLL_D2 73
132 +#define CLK_TOP_TVDPLL_D4 74
133 +#define CLK_TOP_TVDPLL_D8 75
134 +#define CLK_TOP_TVDPLL_429M 76
135 +#define CLK_TOP_TVDPLL_429M_D2 77
136 +#define CLK_TOP_TVDPLL_429M_D4 78
137 +#define CLK_TOP_MSDCPLL 79
138 +#define CLK_TOP_MSDCPLL_D2 80
139 +#define CLK_TOP_MSDCPLL_D4 81
140 +#define CLK_TOP_MSDCPLL2 82
141 +#define CLK_TOP_MSDCPLL2_D2 83
142 +#define CLK_TOP_MSDCPLL2_D4 84
143 +#define CLK_TOP_CLK26M_D2 85
144 +#define CLK_TOP_D2A_ULCLK_6P5M 86
145 +#define CLK_TOP_VPLL3_DPIX 87
146 +#define CLK_TOP_VPLL_DPIX 88
147 +#define CLK_TOP_LTEPLL_FS26M 89
148 +#define CLK_TOP_DMPLL 90
149 +#define CLK_TOP_DSI0_LNTC 91
150 +#define CLK_TOP_DSI1_LNTC 92
151 +#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
152 +#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
153 +#define CLK_TOP_CLKRTC_EXT 95
154 +#define CLK_TOP_CLKRTC_INT 96
155 +#define CLK_TOP_CSI0 97
156 +#define CLK_TOP_CVBSPLL 98
157 +#define CLK_TOP_AXI_SEL 99
158 +#define CLK_TOP_MEM_SEL 100
159 +#define CLK_TOP_MM_SEL 101
160 +#define CLK_TOP_PWM_SEL 102
161 +#define CLK_TOP_VDEC_SEL 103
162 +#define CLK_TOP_VENC_SEL 104
163 +#define CLK_TOP_MFG_SEL 105
164 +#define CLK_TOP_CAMTG_SEL 106
165 +#define CLK_TOP_UART_SEL 107
166 +#define CLK_TOP_SPI_SEL 108
167 +#define CLK_TOP_USB20_SEL 109
168 +#define CLK_TOP_USB30_SEL 110
169 +#define CLK_TOP_MSDC50_0_HCLK_SEL 111
170 +#define CLK_TOP_MSDC50_0_SEL 112
171 +#define CLK_TOP_MSDC30_1_SEL 113
172 +#define CLK_TOP_MSDC30_2_SEL 114
173 +#define CLK_TOP_MSDC30_3_SEL 115
174 +#define CLK_TOP_AUDIO_SEL 116
175 +#define CLK_TOP_AUD_INTBUS_SEL 117
176 +#define CLK_TOP_PMICSPI_SEL 118
177 +#define CLK_TOP_DPILVDS1_SEL 119
178 +#define CLK_TOP_ATB_SEL 120
179 +#define CLK_TOP_NR_SEL 121
180 +#define CLK_TOP_NFI2X_SEL 122
181 +#define CLK_TOP_IRDA_SEL 123
182 +#define CLK_TOP_CCI400_SEL 124
183 +#define CLK_TOP_AUD_1_SEL 125
184 +#define CLK_TOP_AUD_2_SEL 126
185 +#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
186 +#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
187 +#define CLK_TOP_SCAM_SEL 129
188 +#define CLK_TOP_NFIECC_SEL 130
189 +#define CLK_TOP_PE2_MAC_P0_SEL 131
190 +#define CLK_TOP_PE2_MAC_P1_SEL 132
191 +#define CLK_TOP_DPILVDS_SEL 133
192 +#define CLK_TOP_MSDC50_3_HCLK_SEL 134
193 +#define CLK_TOP_HDCP_SEL 135
194 +#define CLK_TOP_HDCP_24M_SEL 136
195 +#define CLK_TOP_RTC_SEL 137
196 +#define CLK_TOP_SPINOR_SEL 138
197 +#define CLK_TOP_APLL_SEL 139
198 +#define CLK_TOP_APLL2_SEL 140
199 +#define CLK_TOP_A1SYS_HP_SEL 141
200 +#define CLK_TOP_A2SYS_HP_SEL 142
201 +#define CLK_TOP_ASM_L_SEL 143
202 +#define CLK_TOP_ASM_M_SEL 144
203 +#define CLK_TOP_ASM_H_SEL 145
204 +#define CLK_TOP_I2SO1_SEL 146
205 +#define CLK_TOP_I2SO2_SEL 147
206 +#define CLK_TOP_I2SO3_SEL 148
207 +#define CLK_TOP_TDMO0_SEL 149
208 +#define CLK_TOP_TDMO1_SEL 150
209 +#define CLK_TOP_I2SI1_SEL 151
210 +#define CLK_TOP_I2SI2_SEL 152
211 +#define CLK_TOP_I2SI3_SEL 153
212 +#define CLK_TOP_ETHER_125M_SEL 154
213 +#define CLK_TOP_ETHER_50M_SEL 155
214 +#define CLK_TOP_JPGDEC_SEL 156
215 +#define CLK_TOP_SPISLV_SEL 157
216 +#define CLK_TOP_ETHER_50M_RMII_SEL 158
217 +#define CLK_TOP_CAM2TG_SEL 159
218 +#define CLK_TOP_DI_SEL 160
219 +#define CLK_TOP_TVD_SEL 161
220 +#define CLK_TOP_I2C_SEL 162
221 +#define CLK_TOP_PWM_INFRA_SEL 163
222 +#define CLK_TOP_MSDC0P_AES_SEL 164
223 +#define CLK_TOP_CMSYS_SEL 165
224 +#define CLK_TOP_GCPU_SEL 166
225 +#define CLK_TOP_AUD_APLL1_SEL 167
226 +#define CLK_TOP_AUD_APLL2_SEL 168
227 +#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
228 +#define CLK_TOP_APLL_DIV0 170
229 +#define CLK_TOP_APLL_DIV1 171
230 +#define CLK_TOP_APLL_DIV2 172
231 +#define CLK_TOP_APLL_DIV3 173
232 +#define CLK_TOP_APLL_DIV4 174
233 +#define CLK_TOP_APLL_DIV5 175
234 +#define CLK_TOP_APLL_DIV6 176
235 +#define CLK_TOP_APLL_DIV7 177
236 +#define CLK_TOP_APLL_DIV_PDN0 178
237 +#define CLK_TOP_APLL_DIV_PDN1 179
238 +#define CLK_TOP_APLL_DIV_PDN2 180
239 +#define CLK_TOP_APLL_DIV_PDN3 181
240 +#define CLK_TOP_APLL_DIV_PDN4 182
241 +#define CLK_TOP_APLL_DIV_PDN5 183
242 +#define CLK_TOP_APLL_DIV_PDN6 184
243 +#define CLK_TOP_APLL_DIV_PDN7 185
244 +#define CLK_TOP_NR_CLK 186
248 +#define CLK_INFRA_DBGCLK 0
249 +#define CLK_INFRA_GCE 1
250 +#define CLK_INFRA_M4U 2
251 +#define CLK_INFRA_KP 3
252 +#define CLK_INFRA_AO_SPI0 4
253 +#define CLK_INFRA_AO_SPI1 5
254 +#define CLK_INFRA_AO_UART5 6
255 +#define CLK_INFRA_NR_CLK 7
259 +#define CLK_PERI_NFI 0
260 +#define CLK_PERI_THERM 1
261 +#define CLK_PERI_PWM0 2
262 +#define CLK_PERI_PWM1 3
263 +#define CLK_PERI_PWM2 4
264 +#define CLK_PERI_PWM3 5
265 +#define CLK_PERI_PWM4 6
266 +#define CLK_PERI_PWM5 7
267 +#define CLK_PERI_PWM6 8
268 +#define CLK_PERI_PWM7 9
269 +#define CLK_PERI_PWM 10
270 +#define CLK_PERI_AP_DMA 11
271 +#define CLK_PERI_MSDC30_0 12
272 +#define CLK_PERI_MSDC30_1 13
273 +#define CLK_PERI_MSDC30_2 14
274 +#define CLK_PERI_MSDC30_3 15
275 +#define CLK_PERI_UART0 16
276 +#define CLK_PERI_UART1 17
277 +#define CLK_PERI_UART2 18
278 +#define CLK_PERI_UART3 19
279 +#define CLK_PERI_I2C0 20
280 +#define CLK_PERI_I2C1 21
281 +#define CLK_PERI_I2C2 22
282 +#define CLK_PERI_I2C3 23
283 +#define CLK_PERI_I2C4 24
284 +#define CLK_PERI_AUXADC 25
285 +#define CLK_PERI_SPI0 26
286 +#define CLK_PERI_SPI 27
287 +#define CLK_PERI_I2C5 28
288 +#define CLK_PERI_SPI2 29
289 +#define CLK_PERI_SPI3 30
290 +#define CLK_PERI_SPI5 31
291 +#define CLK_PERI_UART4 32
292 +#define CLK_PERI_SFLASH 33
293 +#define CLK_PERI_GMAC 34
294 +#define CLK_PERI_PCIE0 35
295 +#define CLK_PERI_PCIE1 36
296 +#define CLK_PERI_GMAC_PCLK 37
297 +#define CLK_PERI_MSDC50_0_EN 38
298 +#define CLK_PERI_MSDC30_1_EN 39
299 +#define CLK_PERI_MSDC30_2_EN 40
300 +#define CLK_PERI_MSDC30_3_EN 41
301 +#define CLK_PERI_MSDC50_0_HCLK_EN 42
302 +#define CLK_PERI_MSDC50_3_HCLK_EN 43
303 +#define CLK_PERI_NR_CLK 44
307 +#define CLK_MCU_MP0_SEL 0
308 +#define CLK_MCU_MP2_SEL 1
309 +#define CLK_MCU_BUS_SEL 2
310 +#define CLK_MCU_NR_CLK 3
314 +#define CLK_MFG_BG3D 0
315 +#define CLK_MFG_NR_CLK 1
319 +#define CLK_MM_SMI_COMMON 0
320 +#define CLK_MM_SMI_LARB0 1
321 +#define CLK_MM_CAM_MDP 2
322 +#define CLK_MM_MDP_RDMA0 3
323 +#define CLK_MM_MDP_RDMA1 4
324 +#define CLK_MM_MDP_RSZ0 5
325 +#define CLK_MM_MDP_RSZ1 6
326 +#define CLK_MM_MDP_RSZ2 7
327 +#define CLK_MM_MDP_TDSHP0 8
328 +#define CLK_MM_MDP_TDSHP1 9
329 +#define CLK_MM_MDP_CROP 10
330 +#define CLK_MM_MDP_WDMA 11
331 +#define CLK_MM_MDP_WROT0 12
332 +#define CLK_MM_MDP_WROT1 13
333 +#define CLK_MM_FAKE_ENG 14
334 +#define CLK_MM_MUTEX_32K 15
335 +#define CLK_MM_DISP_OVL0 16
336 +#define CLK_MM_DISP_OVL1 17
337 +#define CLK_MM_DISP_RDMA0 18
338 +#define CLK_MM_DISP_RDMA1 19
339 +#define CLK_MM_DISP_RDMA2 20
340 +#define CLK_MM_DISP_WDMA0 21
341 +#define CLK_MM_DISP_WDMA1 22
342 +#define CLK_MM_DISP_COLOR0 23
343 +#define CLK_MM_DISP_COLOR1 24
344 +#define CLK_MM_DISP_AAL 25
345 +#define CLK_MM_DISP_GAMMA 26
346 +#define CLK_MM_DISP_UFOE 27
347 +#define CLK_MM_DISP_SPLIT0 28
348 +#define CLK_MM_DISP_OD 29
349 +#define CLK_MM_DISP_PWM0_MM 30
350 +#define CLK_MM_DISP_PWM0_26M 31
351 +#define CLK_MM_DISP_PWM1_MM 32
352 +#define CLK_MM_DISP_PWM1_26M 33
353 +#define CLK_MM_DSI0_ENGINE 34
354 +#define CLK_MM_DSI0_DIGITAL 35
355 +#define CLK_MM_DSI1_ENGINE 36
356 +#define CLK_MM_DSI1_DIGITAL 37
357 +#define CLK_MM_DPI_PIXEL 38
358 +#define CLK_MM_DPI_ENGINE 39
359 +#define CLK_MM_DPI1_PIXEL 40
360 +#define CLK_MM_DPI1_ENGINE 41
361 +#define CLK_MM_LVDS_PIXEL 42
362 +#define CLK_MM_LVDS_CTS 43
363 +#define CLK_MM_SMI_LARB4 44
364 +#define CLK_MM_SMI_COMMON1 45
365 +#define CLK_MM_SMI_LARB5 46
366 +#define CLK_MM_MDP_RDMA2 47
367 +#define CLK_MM_MDP_TDSHP2 48
368 +#define CLK_MM_DISP_OVL2 49
369 +#define CLK_MM_DISP_WDMA2 50
370 +#define CLK_MM_DISP_COLOR2 51
371 +#define CLK_MM_DISP_AAL1 52
372 +#define CLK_MM_DISP_OD1 53
373 +#define CLK_MM_LVDS1_PIXEL 54
374 +#define CLK_MM_LVDS1_CTS 55
375 +#define CLK_MM_SMI_LARB7 56
376 +#define CLK_MM_MDP_RDMA3 57
377 +#define CLK_MM_MDP_WROT2 58
378 +#define CLK_MM_DSI2 59
379 +#define CLK_MM_DSI2_DIGITAL 60
380 +#define CLK_MM_DSI3 61
381 +#define CLK_MM_DSI3_DIGITAL 62
382 +#define CLK_MM_NR_CLK 63
386 +#define CLK_IMG_SMI_LARB2 0
387 +#define CLK_IMG_SENINF_SCAM_EN 1
388 +#define CLK_IMG_SENINF_CAM_EN 2
389 +#define CLK_IMG_CAM_SV_EN 3
390 +#define CLK_IMG_CAM_SV1_EN 4
391 +#define CLK_IMG_CAM_SV2_EN 5
392 +#define CLK_IMG_NR_CLK 6
396 +#define CLK_BDP_BRIDGE_B 0
397 +#define CLK_BDP_BRIDGE_DRAM 1
398 +#define CLK_BDP_LARB_DRAM 2
399 +#define CLK_BDP_WR_CHANNEL_VDI_PXL 3
400 +#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
401 +#define CLK_BDP_WR_CHANNEL_VDI_B 5
402 +#define CLK_BDP_MT_B 6
403 +#define CLK_BDP_DISPFMT_27M 7
404 +#define CLK_BDP_DISPFMT_27M_VDOUT 8
405 +#define CLK_BDP_DISPFMT_27_74_74 9
406 +#define CLK_BDP_DISPFMT_2FS 10
407 +#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
408 +#define CLK_BDP_DISPFMT_B 12
409 +#define CLK_BDP_VDO_DRAM 13
410 +#define CLK_BDP_VDO_2FS 14
411 +#define CLK_BDP_VDO_B 15
412 +#define CLK_BDP_WR_CHANNEL_DI_PXL 16
413 +#define CLK_BDP_WR_CHANNEL_DI_DRAM 17
414 +#define CLK_BDP_WR_CHANNEL_DI_B 18
415 +#define CLK_BDP_NR_AGENT 19
416 +#define CLK_BDP_NR_DRAM 20
417 +#define CLK_BDP_NR_B 21
418 +#define CLK_BDP_BRIDGE_RT_B 22
419 +#define CLK_BDP_BRIDGE_RT_DRAM 23
420 +#define CLK_BDP_LARB_RT_DRAM 24
421 +#define CLK_BDP_TVD_TDC 25
422 +#define CLK_BDP_TVD_54 26
423 +#define CLK_BDP_TVD_CBUS 27
424 +#define CLK_BDP_NR_CLK 28
428 +#define CLK_VDEC_CKEN 0
429 +#define CLK_VDEC_LARB1_CKEN 1
430 +#define CLK_VDEC_IMGRZ_CKEN 2
431 +#define CLK_VDEC_NR_CLK 3
435 +#define CLK_VENC_SMI_COMMON_CON 0
436 +#define CLK_VENC_VENC 1
437 +#define CLK_VENC_SMI_LARB6 2
438 +#define CLK_VENC_NR_CLK 3
442 +#define CLK_JPGDEC_JPGDEC1 0
443 +#define CLK_JPGDEC_JPGDEC 1
444 +#define CLK_JPGDEC_NR_CLK 2
446 +#endif /* _DT_BINDINGS_CLK_MT2712_H */
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