target/linux/mediatek/patches-4.14/0064-dts.patch

   1 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
   2 +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
   3 @@ -21,6 +21,10 @@
   4                 stdout-path = "serial2:115200n8";
   5         };
   6
   7 +       memory {
   8 +               reg = <0 0x80000000 0 0x20000000>;
   9 +       };
  10 +
  11         cpus {
  12                 cpu@0 {
  13                         proc-supply = <&mt6323_vproc_reg>;
  14 @@ -103,6 +107,10 @@
  15                 device_type = "memory";
  16                 reg = <0 0x80000000 0 0x40000000>;
  17         };
  18 +
  19 +       mt7530: switch@0 {
  20 +               compatible = "mediatek,mt7530";
  21 +       };
  22  };
  23
  24  &cir {
  25 @@ -130,11 +138,24 @@
  26                 };
  27         };
  28
  29 +       gmac1: mac@1 {
  30 +               compatible = "mediatek,eth-mac";
  31 +               reg = <1>;
  32 +               phy-mode = "rgmii";
  33 +
  34 +               fixed-link {
  35 +                       speed = <1000>;
  36 +                       full-duplex;
  37 +                       pause;
  38 +               };
  39 +       };
  40 +
  41         mdio: mdio-bus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44 -
  45 -               switch@0 {
  46 +       };
  47 +};
  48 +               &mt7530 {
  49                         compatible = "mediatek,mt7530";
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52 @@ -144,6 +165,8 @@
  53                         core-supply = <&mt6323_vpa_reg>;
  54                         io-supply = <&mt6323_vemc3v3_reg>;
  55
  56 +                       dsa,mii-bus = <&mdio>;
  57 +
  58                         ports {
  59                                 #address-cells = <1>;
  60                                 #size-cells = <0>;
  61 @@ -152,29 +175,46 @@
  62                                 port@0 {
  63                                         reg = <0>;
  64                                         label = "wan";
  65 +                                       cpu = <&cpu_port1>;
  66                                 };
  67
  68                                 port@1 {
  69                                         reg = <1>;
  70                                         label = "lan0";
  71 +                                       cpu = <&cpu_port0>;
  72                                 };
  73
  74                                 port@2 {
  75                                         reg = <2>;
  76                                         label = "lan1";
  77 +                                       cpu = <&cpu_port0>;
  78                                 };
  79
  80                                 port@3 {
  81                                         reg = <3>;
  82                                         label = "lan2";
  83 +                                       cpu = <&cpu_port0>;
  84                                 };
  85
  86                                 port@4 {
  87                                         reg = <4>;
  88                                         label = "lan3";
  89 +                                       cpu = <&cpu_port0>;
  90                                 };
  91
  92 -                               port@6 {
  93 +                               cpu_port1: port@5 {
  94 +                                       reg = <5>;
  95 +                                       label = "cpu";
  96 +                                       ethernet = <&gmac1>;
  97 +                                       phy-mode = "rgmii";
  98 +
  99 +                                       fixed-link {
 100 +                                               speed = <1000>;
 101 +                                               full-duplex;
 102 +                                       };
 103 +                               };
 104 +
 105 +                               cpu_port0: port@6 {
 106                                         reg = <6>;
 107                                         label = "cpu";
 108                                         ethernet = <&gmac0>;
 109 @@ -187,8 +227,6 @@
 110                                 };
 111                         };
 112                 };
 113 -       };
 114 -};
 115
 116  &i2c0 {
 117         pinctrl-names = "default";
 118 --- a/arch/arm/boot/dts/Makefile
 119 +++ b/arch/arm/boot/dts/Makefile
 120 @@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 121         mt6580-evbp1.dtb \
 122         mt6589-aquaris5.dtb \
 123         mt6592-evb.dtb \
 124 +       mt7623a-rfb-emmc.dtb \
 125         mt7623n-rfb-nand.dtb \
 126         mt7623n-bananapi-bpi-r2.dtb \
 127         mt8127-moose.dtb \
 128 --- /dev/null
 129 +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
 130 @@ -0,0 +1,449 @@
 131 +/*
 132 + * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
 133 + *
 134 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 135 + */
 136 +
 137 +/dts-v1/;
 138 +#include <dt-bindings/input/input.h>
 139 +#include "mt7623.dtsi"
 140 +#include "mt6323.dtsi"
 141 +
 142 +/ {
 143 +       model = "MediaTek MT7623N NAND reference board";
 144 +       compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
 145 +
 146 +       aliases {
 147 +               serial2 = &uart2;
 148 +       };
 149 +
 150 +       chosen {
 151 +               bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
 152 +
 153 +               stdout-path = "serial2:115200n8";
 154 +       };
 155 +
 156 +       memory {
 157 +               reg = <0 0x80000000 0 0x20000000>;
 158 +       };
 159 +
 160 +       cpus {
 161 +               cpu@0 {
 162 +                       proc-supply = <&mt6323_vproc_reg>;
 163 +               };
 164 +
 165 +               cpu@1 {
 166 +                       proc-supply = <&mt6323_vproc_reg>;
 167 +               };
 168 +
 169 +               cpu@2 {
 170 +                       proc-supply = <&mt6323_vproc_reg>;
 171 +               };
 172 +
 173 +               cpu@3 {
 174 +                       proc-supply = <&mt6323_vproc_reg>;
 175 +               };
 176 +       };
 177 +
 178 +       memory@80000000 {
 179 +               reg = <0 0x80000000 0 0x40000000>;
 180 +       };
 181 +
 182 +       mt7530: switch@0 {
 183 +               compatible = "mediatek,mt7530";
 184 +               #address-cells = <1>;
 185 +               #size-cells = <0>;
 186 +       };
 187 +};
 188 +
 189 +&crypto {
 190 +       status = "okay";
 191 +};
 192 +
 193 +&eth {
 194 +       status = "okay";
 195 +
 196 +       gmac0: mac@0 {
 197 +               compatible = "mediatek,eth-mac";
 198 +               reg = <0>;
 199 +               phy-mode = "trgmii";
 200 +
 201 +               fixed-link {
 202 +                       speed = <1000>;
 203 +                       full-duplex;
 204 +                       pause;
 205 +               };
 206 +       };
 207 +
 208 +       gmac1: mac@1 {
 209 +               compatible = "mediatek,eth-mac";
 210 +               reg = <1>;
 211 +               phy-mode = "rgmiii-rxid";
 212 +               phy-handle = <&phy5>;
 213 +       };
 214 +
 215 +       mdio: mdio-bus {
 216 +               #address-cells = <1>;
 217 +               #size-cells = <0>;
 218 +               phy5: ethernet-phy@5 {
 219 +                       reg = <5>;
 220 +                       phy-mode = "rgmii-rxid";
 221 +               };
 222 +       };
 223 +};
 224 +
 225 +&mt7530 {
 226 +       compatible = "mediatek,mt7530";
 227 +       #address-cells = <1>;
 228 +       #size-cells = <0>;
 229 +       reg = <0>;
 230 +       pinctrl-names = "default";
 231 +       mediatek,mcm;
 232 +       resets = <&ethsys 2>;
 233 +       reset-names = "mcm";
 234 +       core-supply = <&mt6323_vpa_reg>;
 235 +       io-supply = <&mt6323_vemc3v3_reg>;
 236 +
 237 +       dsa,mii-bus = <&mdio>;
 238 +
 239 +       ports {
 240 +               #address-cells = <1>;
 241 +               #size-cells = <0>;
 242 +               reg = <0>;
 243 +
 244 +               port@0 {
 245 +                       reg = <0>;
 246 +                       label = "lan0";
 247 +                       cpu = <&cpu_port0>;
 248 +               };
 249 +
 250 +               port@1 {
 251 +                       reg = <1>;
 252 +                       label = "lan1";
 253 +                       cpu = <&cpu_port0>;
 254 +               };
 255 +
 256 +               port@2 {
 257 +                       reg = <2>;
 258 +                       label = "lan2";
 259 +                       cpu = <&cpu_port0>;
 260 +               };
 261 +
 262 +               port@3 {
 263 +                       reg = <3>;
 264 +                       label = "lan3";
 265 +                       cpu = <&cpu_port0>;
 266 +               };
 267 +
 268 +               cpu_port0: port@6 {
 269 +                       reg = <6>;
 270 +                       label = "cpu";
 271 +                       ethernet = <&gmac0>;
 272 +                       phy-mode = "trgmii";
 273 +
 274 +                       fixed-link {
 275 +                               speed = <1000>;
 276 +                               full-duplex;
 277 +                       };
 278 +               };
 279 +       };
 280 +};
 281 +
 282 +&i2c0 {
 283 +       pinctrl-names = "default";
 284 +       pinctrl-0 = <&i2c0_pins_a>;
 285 +       status = "okay";
 286 +};
 287 +
 288 +&i2c1 {
 289 +       pinctrl-names = "default";
 290 +       pinctrl-0 = <&i2c1_pins_a>;
 291 +       status = "okay";
 292 +};
 293 +
 294 +&mmc0 {
 295 +       pinctrl-names = "default", "state_uhs";
 296 +       pinctrl-0 = <&mmc0_pins_default>;
 297 +       pinctrl-1 = <&mmc0_pins_uhs>;
 298 +       status = "okay";
 299 +       bus-width = <8>;
 300 +       max-frequency = <50000000>;
 301 +       cap-mmc-highspeed;
 302 +       vmmc-supply = <&mt6323_vemc3v3_reg>;
 303 +       vqmmc-supply = <&mt6323_vio18_reg>;
 304 +       non-removable;
 305 +};
 306 +
 307 +&mmc1 {
 308 +       pinctrl-names = "default", "state_uhs";
 309 +       pinctrl-0 = <&mmc1_pins_default>;
 310 +       pinctrl-1 = <&mmc1_pins_uhs>;
 311 +       status = "okay";
 312 +       bus-width = <4>;
 313 +       max-frequency = <50000000>;
 314 +       cap-sd-highspeed;
 315 +       cd-gpios = <&pio 261 0>;
 316 +       vmmc-supply = <&mt6323_vmch_reg>;
 317 +       vqmmc-supply = <&mt6323_vio18_reg>;
 318 +};
 319 +
 320 +&pio {
 321 +       cir_pins_a:cir@0 {
 322 +               pins_cir {
 323 +                       pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
 324 +                       bias-disable;
 325 +               };
 326 +       };
 327 +
 328 +       i2c0_pins_a: i2c@0 {
 329 +               pins_i2c0 {
 330 +                       pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
 331 +                                <MT7623_PIN_76_SCL0_FUNC_SCL0>;
 332 +                       bias-disable;
 333 +               };
 334 +       };
 335 +
 336 +       i2c1_pins_a: i2c@1 {
 337 +               pin_i2c1 {
 338 +                       pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
 339 +                                <MT7623_PIN_58_SCL1_FUNC_SCL1>;
 340 +                       bias-disable;
 341 +               };
 342 +       };
 343 +
 344 +       i2s0_pins_a: i2s@0 {
 345 +               pin_i2s0 {
 346 +                       pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
 347 +                                <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
 348 +                                <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
 349 +                                <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
 350 +                                <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
 351 +                       drive-strength = <MTK_DRIVE_12mA>;
 352 +                       bias-pull-down;
 353 +               };
 354 +       };
 355 +
 356 +       i2s1_pins_a: i2s@1 {
 357 +               pin_i2s1 {
 358 +                       pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
 359 +                                <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
 360 +                                <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
 361 +                                <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
 362 +                                <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
 363 +                       drive-strength = <MTK_DRIVE_12mA>;
 364 +                       bias-pull-down;
 365 +               };
 366 +       };
 367 +
 368 +       mmc0_pins_default: mmc0default {
 369 +               pins_cmd_dat {
 370 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 371 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 372 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 373 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 374 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 375 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 376 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 377 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 378 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 379 +                       input-enable;
 380 +                       bias-pull-up;
 381 +               };
 382 +
 383 +               pins_clk {
 384 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 385 +                       bias-pull-down;
 386 +               };
 387 +
 388 +               pins_rst {
 389 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 390 +                       bias-pull-up;
 391 +               };
 392 +       };
 393 +
 394 +       mmc0_pins_uhs: mmc0 {
 395 +               pins_cmd_dat {
 396 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 397 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 398 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 399 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 400 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 401 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 402 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 403 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 404 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 405 +                       input-enable;
 406 +                       drive-strength = <MTK_DRIVE_2mA>;
 407 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 408 +               };
 409 +
 410 +               pins_clk {
 411 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 412 +                       drive-strength = <MTK_DRIVE_2mA>;
 413 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 414 +               };
 415 +
 416 +               pins_rst {
 417 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 418 +                       bias-pull-up;
 419 +               };
 420 +       };
 421 +
 422 +       mmc1_pins_default: mmc1default {
 423 +               pins_cmd_dat {
 424 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 425 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 426 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 427 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 428 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 429 +                       input-enable;
 430 +                       drive-strength = <MTK_DRIVE_4mA>;
 431 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 432 +               };
 433 +
 434 +               pins_clk {
 435 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 436 +                       bias-pull-down;
 437 +                       drive-strength = <MTK_DRIVE_4mA>;
 438 +               };
 439 +
 440 +               pins_wp {
 441 +                       pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
 442 +                       input-enable;
 443 +                       bias-pull-up;
 444 +               };
 445 +
 446 +               pins_insert {
 447 +                       pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
 448 +                       bias-pull-up;
 449 +               };
 450 +       };
 451 +
 452 +       mmc1_pins_uhs: mmc1 {
 453 +               pins_cmd_dat {
 454 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 455 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 456 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 457 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 458 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 459 +                       input-enable;
 460 +                       drive-strength = <MTK_DRIVE_4mA>;
 461 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 462 +               };
 463 +
 464 +               pins_clk {
 465 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 466 +                       drive-strength = <MTK_DRIVE_4mA>;
 467 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 468 +               };
 469 +       };
 470 +
 471 +       pwm_pins_a: pwm@0 {
 472 +               pins_pwm {
 473 +                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
 474 +                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
 475 +                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
 476 +                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
 477 +                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
 478 +               };
 479 +       };
 480 +
 481 +       spi0_pins_a: spi@0 {
 482 +               pins_spi {
 483 +                       pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
 484 +                               <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
 485 +                               <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
 486 +                               <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
 487 +                       bias-disable;
 488 +               };
 489 +       };
 490 +
 491 +       uart0_pins_a: uart@0 {
 492 +               pins_dat {
 493 +                       pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
 494 +                                <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
 495 +               };
 496 +       };
 497 +
 498 +       uart1_pins_a: uart@1 {
 499 +               pins_dat {
 500 +                       pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
 501 +                                <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
 502 +               };
 503 +       };
 504 +};
 505 +
 506 +&pwm {
 507 +       pinctrl-names = "default";
 508 +       pinctrl-0 = <&pwm_pins_a>;
 509 +       status = "okay";
 510 +};
 511 +
 512 +&pwrap {
 513 +       mt6323 {
 514 +               mt6323led: led {
 515 +                       compatible = "mediatek,mt6323-led";
 516 +                       #address-cells = <1>;
 517 +                       #size-cells = <0>;
 518 +
 519 +                       led@0 {
 520 +                               reg = <0>;
 521 +                               label = "bpi-r2:isink:green";
 522 +                               default-state = "off";
 523 +                       };
 524 +
 525 +                       led@1 {
 526 +                               reg = <1>;
 527 +                               label = "bpi-r2:isink:red";
 528 +                               default-state = "off";
 529 +                       };
 530 +
 531 +                       led@2 {
 532 +                               reg = <2>;
 533 +                               label = "bpi-r2:isink:blue";
 534 +                               default-state = "off";
 535 +                       };
 536 +               };
 537 +       };
 538 +};
 539 +
 540 +&spi0 {
 541 +       pinctrl-names = "default";
 542 +       pinctrl-0 = <&spi0_pins_a>;
 543 +       status = "okay";
 544 +};
 545 +
 546 +&uart0 {
 547 +       pinctrl-names = "default";
 548 +       pinctrl-0 = <&uart0_pins_a>;
 549 +       status = "disabled";
 550 +};
 551 +
 552 +&uart1 {
 553 +       pinctrl-names = "default";
 554 +       pinctrl-0 = <&uart1_pins_a>;
 555 +       status = "disabled";
 556 +};
 557 +
 558 +&uart2 {
 559 +       status = "okay";
 560 +};
 561 +
 562 +&usb1 {
 563 +       vusb33-supply = <&mt6323_vusb_reg>;
 564 +       status = "okay";
 565 +};
 566 +
 567 +&usb2 {
 568 +       vusb33-supply = <&mt6323_vusb_reg>;
 569 +       status = "okay";
 570 +};
 571 +
 572 +&u3phy1 {
 573 +       status = "okay";
 574 +};
 575 +
 576 +&u3phy2 {
 577 +       status = "okay";
 578 +};
 579 +
 580 --- a/arch/arm/boot/dts/mt7623.dtsi
 581 +++ b/arch/arm/boot/dts/mt7623.dtsi
 582 @@ -326,6 +326,7 @@
 583                              "syscon";
 584                 reg = <0 0x10209000 0 0x1000>;
 585                 #clock-cells = <1>;
 586 +               #reset-cells = <1>;
 587         };
 588
 589         rng: rng@1020f000 {