2 * Driver for MediaTek MT753x gigabit switch
4 * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/list.h>
15 #include <linux/mutex.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_mdio.h>
18 #include <linux/workqueue.h>
19 #include <linux/gpio/consumer.h>
21 #ifdef CONFIG_SWCONFIG
22 #include <linux/switch.h>
25 #define MT753X_DFL_CPU_PORT 6
26 #define MT753X_NUM_PORTS 7
27 #define MT753X_NUM_PHYS 5
28 #define MT753X_NUM_VLANS 4095
30 #define MT753X_MAX_VID 4095
31 #define MT753X_MIN_VID 0
33 #define MT753X_DFL_SMI_ADDR 0x1f
34 #define MT753X_SMI_ADDR_MASK 0x1f
43 struct mt753x_port_entry {
47 struct mt753x_vlan_entry {
53 struct mt753x_port_cfg {
54 struct device_node *np;
63 struct gsw_mt753x *gsw;
64 struct net_device netdev;
65 struct phy_device *phydev;
72 struct mii_bus *host_bus;
73 struct mii_bus *gphy_bus;
74 struct mutex mii_lock; /* MII access lock */
77 int direct_phy_access;
79 enum mt753x_model model;
82 struct mt753x_port_cfg port5_cfg;
83 struct mt753x_port_cfg port6_cfg;
86 struct mt753x_phy phys[MT753X_NUM_PHYS];
92 struct work_struct irq_worker;
94 #ifdef CONFIG_SWCONFIG
95 struct switch_dev swdev;
97 struct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS];
98 struct mt753x_port_entry port_entries[MT753X_NUM_PORTS];
100 int global_vlan_enable;
104 int (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg);
105 void (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
107 int (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
108 void (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
111 struct list_head list;
119 struct mt753x_sw_id {
120 enum mt753x_model model;
121 int (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev);
122 int (*init)(struct gsw_mt753x *gsw);
123 int (*post_init)(struct gsw_mt753x *gsw);
126 extern struct list_head mt753x_devs;
128 struct gsw_mt753x *mt753x_get_gsw(u32 id);
129 struct gsw_mt753x *mt753x_get_first_gsw(void);
130 void mt753x_put_gsw(void);
131 void mt753x_lock_gsw(void);
133 u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg);
134 void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val);
136 int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg);
137 void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val);
139 int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
140 void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
143 int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);
144 void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,
147 void mt753x_irq_worker(struct work_struct *work);
148 void mt753x_irq_enable(struct gsw_mt753x *gsw);
150 /* MDIO Indirect Access Registers */
151 #define MII_MMD_ACC_CTL_REG 0x0d
153 #define MMD_CMD_M 0xc000
154 #define MMD_DEVAD_S 0
155 #define MMD_DEVAD_M 0x1f
157 /* MMD_CMD: MMD commands */
161 #define MII_MMD_ADDR_DATA_REG 0x0e
163 /* Procedure of MT753x Internal Register Access
165 * 1. Internal Register Address
167 * The MT753x has a 16-bit register address and each register is 32-bit.
168 * This means the lowest two bits are not used as the register address is
171 * Rest of the valid bits are divided into two parts:
172 * Bit 15..6 is the Page address
173 * Bit 5..2 is the low address
175 * -------------------------------------------------------------------
176 * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
177 * |----------------------------------------|---------------|--------|
178 * | Page Address | Address | Unused |
179 * -------------------------------------------------------------------
181 * 2. MDIO access timing
183 * The MT753x uses the following MDIO timing for a single register read
185 * Phase 1: Write Page Address
186 * -------------------------------------------------------------------
187 * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | RSVD | PAGE_ADDR |
188 * -------------------------------------------------------------------
189 * | 01 | 01 | 11111 | 1 | 1111 | xx | 00000 | REG_ADDR[15..6] |
190 * -------------------------------------------------------------------
192 * Phase 2: Write low Address & Read low word
193 * -------------------------------------------------------------------
194 * | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA |
195 * -------------------------------------------------------------------
196 * | 01 | 10 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] |
197 * -------------------------------------------------------------------
199 * Phase 3: Read high word
200 * -------------------------------------------------------------------
201 * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA |
202 * -------------------------------------------------------------------
203 * | 01 | 10 | 11111 | 1 | 0000 | xx | DATA[31..16] |
204 * -------------------------------------------------------------------
206 * The MT753x uses the following MDIO timing for a single register write
208 * Phase 1: Write Page Address (The same as read)
210 * Phase 2: Write low Address and low word
211 * -------------------------------------------------------------------
212 * | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA |
213 * -------------------------------------------------------------------
214 * | 01 | 01 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] |
215 * -------------------------------------------------------------------
217 * Phase 3: write high word
218 * -------------------------------------------------------------------
219 * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA |
220 * -------------------------------------------------------------------
221 * | 01 | 01 | 11111 | 1 | 0000 | xx | DATA[31..16] |
222 * -------------------------------------------------------------------
226 /* Internal Register Address fields */
227 #define MT753X_REG_PAGE_ADDR_S 6
228 #define MT753X_REG_PAGE_ADDR_M 0xffc0
229 #define MT753X_REG_ADDR_S 2
230 #define MT753X_REG_ADDR_M 0x3c
232 #endif /* _MT753X_H_ */