target/linux/mcs814x/files-3.3/arch/arm/boot/dts/mcs8140.dtsi

   1 /*
   2  * mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC
   3  *
   4  * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
   5  *
   6  * Licensed under GPLv2.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         model = "Moschip MCS8140 family SoC";
  13         compatible = "moschip,mcs8140";
  14         interrupt-parent = <&intc>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 eth0 = &eth0;
  19         };
  20
  21         cpus {
  22                 cpu@0 {
  23                         compatible = "arm,arm926ejs";
  24                 };
  25         };
  26
  27         ahb {
  28                 compatible = "simple-bus";
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 ranges;
  32
  33                 vci {
  34                         compatible = "simple-bus";
  35                         #address-cells = <1>;
  36                         #size-cells = <1>;
  37                         ranges;
  38
  39                         eth0: ethernet@40084000 {
  40                                 compatible = "moschip,nuport-mac";
  41                                 reg = <0x40084000 0xd8          // mac
  42                                         0x40080000 0x58>;       // dma channels
  43                                 interrupts = <4 5 29>;  /* tx, rx, link */
  44                                 nuport-mac,buffer-shifting;
  45                                 nuport-mac,link-activity = <0>;
  46                         };
  47
  48                         tso@40088000 {
  49                                 reg = <0x40088000 0x1c>;
  50                                 interrupts = <7>;
  51                         };
  52
  53                         i2s@4008c000 {
  54                                 compatible = "moschip,mcs814x-i2s";
  55                                 reg = <0x4008c000 0x18>;
  56                                 interrupts = <8>;
  57                         };
  58
  59                         ipsec@40094000 {
  60                                 compatible = "moschip,mcs814x-ipsec";
  61                                 reg = <0x40094000 0x1d8>;
  62                                 interrupts = <16>;
  63                         };
  64
  65                         rng@4009c000 {
  66                                 compatible = "moschip,mcs814x-rng";
  67                                 reg = <0x4009c000 0x8>;
  68                         };
  69
  70                         memc@400a8000 {
  71                                 reg = <0x400a8000 0x58>;
  72                         };
  73
  74                         list-proc@400ac0c0 {
  75                                 reg = <0x400ac0c0 0x38>;
  76                                 interrupts = <19 27>;           // done, error
  77                         };
  78
  79                         pci@400b0000 {
  80                                 reg = <0x400b0000 0x44          // PCI master
  81                                         0x400d8000 0xe4>;       // EEPROM emulator
  82                                 interrupts = <25>;              // abort interrupt
  83                                 status = "disabled";
  84                                 #address-cells = <3>;
  85                                 #size-cells = <2>;
  86
  87                                 ranges = <0x01000000 0 0x80000000 0x80000000 0 0x04000000   // IO
  88                                           0x42000000 0 0x90000000 0x90000000 0 0x20000000   // non-prefetch
  89                                           0x02000000 0 0xb0000000 0xb0000000 0 0x10000000>; // prefecth
  90
  91                                 #interrupt-cells = <1>;
  92                                 interrupt-map-mask = <>;
  93                                 interrupt-map = <0 0 0 1 &intc 22 0
  94                                                  0 0 0 2 &intc 23 0
  95                                                  0 0 0 3 &intc 24 0
  96                                                  0 0 0 4 &intc 26 0>;
  97                         };
  98
  99                         gpio: gpio@400d0000 {
 100                                 compatible = "moschip,mcs814x-gpio";
 101                                 reg = <0x400d0000 0x670>;
 102                                 interrupts = <10>;
 103                                 #gpio-cells = <2>;
 104                                 gpio-controller;
 105                                 num-gpios = <20>;
 106                         };
 107
 108                         eepio: gpio@400d4000 {
 109                                 compatible = "moschip,mcs814x-gpio";
 110                                 reg = <0x400d4000 0x470>;
 111                                 #gpio-cells = <2>;
 112                                 gpio-controller;
 113                                 num-gpios = <4>;
 114                         };
 115
 116                         uart0: serial@400dc000 {
 117                                 compatible = "ns16550";
 118                                 reg = <0x400dc000 0x20>;
 119                                 clock-frequency = <50000000>;
 120                                 reg-shift = <2>;
 121                                 interrupts = <21>;
 122                                 status = "okay";
 123                         };
 124
 125                         intc: interrupt-controller@400e4000 {
 126                                 #interrupt-cells = <1>;
 127                                 compatible = "moschip,mcs814x-intc";
 128                                 interrupt-controller;
 129                                 interrupt-parent;
 130                                 reg = <0x400e4000 0x48>;
 131                         };
 132
 133                         m2m@400e8000 {
 134                                 reg = <0x400e8000 0x24>;
 135                                 interrupts = <17>;
 136                         };
 137
 138                         eth-filters@400ec000 {
 139                                 reg = <0x400ec000 0x80>;
 140                         };
 141
 142                         timer: timer@400f800c {
 143                                 compatible = "moschip,mcs814x-timer";
 144                                 interrupts = <0>;
 145                                 reg = <0x400f800c 0x8>;
 146                         };
 147
 148                         watchdog@400f8014 {
 149                                 compatible = "moschip,mcs814x-wdt";
 150                                 reg = <0x400f8014 0x8>;
 151                         };
 152
 153                         adc {
 154                                 compatible = "simple-bus";
 155                                 #address-cells = <2>;
 156                                 #size-cells = <1>;
 157                                 // 8 64MB chip-selects
 158                                 ranges = <0 0 0x00000000 0x4000000      // sdram
 159                                           1 0 0x04000000 0x4000000      // sdram
 160                                           2 0 0x08000000 0x4000000      // reserved
 161                                           3 0 0x0c000000 0x4000000      // flash/localbus
 162                                           4 0 0x10000000 0x4000000      // flash/localbus
 163                                           5 0 0x14000000 0x4000000      // flash/localbus
 164                                           6 0 0x18000000 0x4000000      // flash/localbus
 165                                           7 0 0x1c000000 0x4000000>;    // flash/localbus
 166
 167                                 sdram: memory@0,0 {
 168                                         reg = <0 0 0>;
 169                                 };
 170
 171                                 nor: flash@7,0 {
 172                                         reg = <7 0 0x4000000>;
 173                                         compatible = "cfi-flash";
 174                                         bank-width = <1>;               // 8-bit external flash
 175                                         #address-cells = <1>;
 176                                         #size-cells = <1>;
 177                                 };
 178                         };
 179
 180                         usb0: ehci@400fc000 {
 181                                 compatible = "moschip,mcs814x-ehci", "usb-ehci";
 182                                 reg = <0x400fc000 0x74>;
 183                                 interrupts = <2>;
 184                         };
 185
 186                         usb1: ohci@400fd000 {
 187                                 compatible = "moschip,mcs814x-ohci", "ohci-le";
 188                                 reg = <0x400fd000 0x74>;
 189                                 interrupts = <11>;
 190                         };
 191
 192                         usb2: ohci@400fe000 {
 193                                 compatible = "moschip,mcs814x-ohci", "ohci-le";
 194                                 reg = <0x400fe000 0x74>;
 195                                 interrupts = <12>;
 196                         };
 197
 198                         usb3: otg@400ff000 {
 199                                 compatible = "moschip,msc814x-otg", "usb-otg";
 200                                 reg = <0x400ff000 0x1000>;
 201                                 interrupts = <13>;
 202                         };
 203                 };
 204
 205         };
 206 };