2 * Moschip MCS814x generic interrupt controller routines
4 * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
6 * Licensed under the GPLv2
8 #include <linux/init.h>
12 #include <linux/of_address.h>
13 #include <linux/irqdomain.h>
15 #include <asm/exception.h>
16 #include <asm/mach/irq.h>
17 #include <mach/mcs814x.h>
19 static void __iomem *mcs814x_intc_base;
21 static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start,
24 struct irq_chip_generic *gc;
25 struct irq_chip_type *ct;
27 gc = irq_alloc_generic_chip("mcs814x-intc", 1,
28 irq_start, base, handle_level_irq);
30 panic("unable to allocate generic irq chip");
33 ct->chip.irq_ack = irq_gc_unmask_enable_reg;
34 ct->chip.irq_mask = irq_gc_mask_clr_bit;
35 ct->chip.irq_unmask = irq_gc_mask_set_bit;
36 ct->regs.mask = MCS814X_IRQ_MASK;
37 ct->regs.enable = MCS814X_IRQ_ICR;
39 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
42 /* Clear all interrupts */
43 writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR);
46 asmlinkage void __exception_irq_entry mcs814x_handle_irq(struct pt_regs *regs)
51 /* read the status register */
52 status = __raw_readl(mcs814x_intc_base + MCS814X_IRQ_STS0);
56 irq = ffs(status) - 1;
58 /* clear the interrupt */
59 __raw_writel(status, mcs814x_intc_base + MCS814X_IRQ_STS0);
60 /* call the generic handler */
61 handle_IRQ(irq, regs);
66 static const struct of_device_id mcs814x_intc_ids[] = {
67 { .compatible = "moschip,mcs814x-intc" },
71 void __init mcs814x_of_irq_init(void)
73 struct device_node *np;
75 np = of_find_matching_node(NULL, mcs814x_intc_ids);
77 panic("unable to find compatible intc node in dtb\n");
79 mcs814x_intc_base = of_iomap(np, 0);
80 if (!mcs814x_intc_base)
81 panic("unable to map intc cpu registers\n");
83 irq_domain_add_simple(np, 32, 0, &irq_generic_chip_ops, NULL);
87 mcs814x_alloc_gc(mcs814x_intc_base, 0, 32);