target/linux/layerscape/patches-5.4/820-usb-0025-LF-387-4-usb-dwc3-Add-cache-type-configuration-suppo.patch

   1 From cda32ee78d8b448bcbfc8e3d55dc04d809657ce2 Mon Sep 17 00:00:00 2001
   2 From: Ran Wang <ran.wang_1@nxp.com>
   3 Date: Wed, 20 Nov 2019 14:09:23 +0800
   4 Subject: [PATCH] LF-387-4 usb: dwc3: Add cache type configuration support
   5
   6 This feature is telling how to configure cache type on 4 different
   7 transfer types: Data Read, Desc Read, Data Write and Desc write. For each
   8 treasfer type, controller has a 4-bit register field to enable different
   9 cache type. Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments:
  10 ----------------------------------------------------------------
  11 MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
  12 ----------------------------------------------------------------
  13 AHB      |Cacheable     |Bufferable   |Privilegge |Data
  14 AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
  15 AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
  16 AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
  17 Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
  18 ----------------------------------------------------------------
  19 Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain
  20 signals, which have the same meaning:
  21   Bufferable = Posted
  22   Cacheable = Modifiable = Snoop (negation of No Snoop)
  23
  24 In most cases, driver support is not required unless the default values of
  25 registers are not correct *and* DWC3 node has enabled dma-coherent. So far we
  26 have observed USB device detect failure on some Layerscape platforms if this
  27 programming was not applied.
  28
  29 Related struct:
  30 struct dwc3_cache_type {
  31         u8 transfer_type_datard;
  32         u8 transfer_type_descrd;
  33         u8 transfer_type_datawr;
  34         u8 transfer_type_descwr;
  35 };
  36
  37 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  38 Reviewed-by: Jun Li <jun.li@nxp.com>
  39 ---
  40  drivers/usb/dwc3/core.c | 67 ++++++++++++++++++++++++++++++++++++++++++++-----
  41  drivers/usb/dwc3/core.h | 15 +++++++++++
  42  2 files changed, 76 insertions(+), 6 deletions(-)
  43
  44 --- a/drivers/usb/dwc3/core.c
  45 +++ b/drivers/usb/dwc3/core.c
  46 @@ -913,6 +913,53 @@ static void dwc3_set_power_down_clk_scal
  47         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  48  }
  49
  50 +#ifdef CONFIG_OF
  51 +struct dwc3_cache_type {
  52 +       u8 transfer_type_datard;
  53 +       u8 transfer_type_descrd;
  54 +       u8 transfer_type_datawr;
  55 +       u8 transfer_type_descwr;
  56 +};
  57 +
  58 +static const struct dwc3_cache_type ls1088a_dwc3_cache_type = {
  59 +       .transfer_type_datard = 2,
  60 +       .transfer_type_descrd = 2,
  61 +       .transfer_type_datawr = 2,
  62 +       .transfer_type_descwr = 2,
  63 +};
  64 +
  65 +/**
  66 + * dwc3_set_cache_type - Configure cache type registers
  67 + * @dwc: Pointer to our controller context structure
  68 + */
  69 +static void dwc3_set_cache_type(struct dwc3 *dwc)
  70 +{
  71 +       u32 tmp, reg;
  72 +       const struct dwc3_cache_type *cache_type =
  73 +               device_get_match_data(dwc->dev);
  74 +
  75 +       if (cache_type) {
  76 +               reg = dwc3_readl(dwc->regs,  DWC3_GSBUSCFG0);
  77 +               tmp = reg;
  78 +
  79 +               reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
  80 +               reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
  81 +
  82 +               reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
  83 +               reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
  84 +
  85 +               reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
  86 +               reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
  87 +
  88 +               reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
  89 +               reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
  90 +
  91 +               if (tmp != reg)
  92 +                       dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
  93 +       }
  94 +}
  95 +#endif
  96 +
  97  /**
  98   * dwc3_core_init - Low-level initialization of DWC3 Core
  99   * @dwc: Pointer to our controller context structure
 100 @@ -973,6 +1020,10 @@ static int dwc3_core_init(struct dwc3 *d
 101
 102         dwc3_set_incr_burst_type(dwc);
 103
 104 +#ifdef CONFIG_OF
 105 +       dwc3_set_cache_type(dwc);
 106 +#endif
 107 +
 108         usb_phy_set_suspend(dwc->usb2_phy, 0);
 109         usb_phy_set_suspend(dwc->usb3_phy, 0);
 110         ret = phy_power_on(dwc->usb2_generic_phy);
 111 @@ -1890,12 +1941,16 @@ static const struct dev_pm_ops dwc3_dev_
 112
 113  #ifdef CONFIG_OF
 114  static const struct of_device_id of_dwc3_match[] = {
 115 -       {
 116 -               .compatible = "snps,dwc3"
 117 -       },
 118 -       {
 119 -               .compatible = "synopsys,dwc3"
 120 -       },
 121 +       { .compatible = "fsl,ls1012a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 122 +       { .compatible = "fsl,ls1021a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 123 +       { .compatible = "fsl,ls1028a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 124 +       { .compatible = "fsl,ls1043a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 125 +       { .compatible = "fsl,ls1046a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 126 +       { .compatible = "fsl,ls1088a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 127 +       { .compatible = "fsl,ls2088a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 128 +       { .compatible = "fsl,lx2160a-dwc3", .data = &ls1088a_dwc3_cache_type, },
 129 +       { .compatible = "snps,dwc3" },
 130 +       { .compatible = "synopsys,dwc3" },
 131         { },
 132  };
 133  MODULE_DEVICE_TABLE(of, of_dwc3_match);
 134 --- a/drivers/usb/dwc3/core.h
 135 +++ b/drivers/usb/dwc3/core.h
 136 @@ -166,6 +166,21 @@
 137  /* Bit fields */
 138
 139  /* Global SoC Bus Configuration INCRx Register 0 */
 140 +#ifdef CONFIG_OF
 141 +#define DWC3_GSBUSCFG0_DATARD_SHIFT    28
 142 +#define DWC3_GSBUSCFG0_DATARD(n)       (((n) & 0xf)            \
 143 +                       << DWC3_GSBUSCFG0_DATARD_SHIFT)
 144 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT    24
 145 +#define DWC3_GSBUSCFG0_DESCRD(n)       (((n) & 0xf)            \
 146 +                       << DWC3_GSBUSCFG0_DESCRD_SHIFT)
 147 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT    20
 148 +#define DWC3_GSBUSCFG0_DATAWR(n)       (((n) & 0xf)            \
 149 +                       << DWC3_GSBUSCFG0_DATAWR_SHIFT)
 150 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT    16
 151 +#define DWC3_GSBUSCFG0_DESCWR(n)       (((n) & 0xf)            \
 152 +                       << DWC3_GSBUSCFG0_DESCWR_SHIFT)
 153 +#endif
 154 +
 155  #define DWC3_GSBUSCFG0_INCR256BRSTENA  (1 << 7) /* INCR256 burst */
 156  #define DWC3_GSBUSCFG0_INCR128BRSTENA  (1 << 6) /* INCR128 burst */
 157  #define DWC3_GSBUSCFG0_INCR64BRSTENA   (1 << 5) /* INCR64 burst */