target/linux/layerscape/patches-5.4/820-usb-0011-usb-dwc3-Add-cache-type-configuration-support.patch

   1 From 63d47233f18ab6bb880cc4005a373a55c8364e0b Mon Sep 17 00:00:00 2001
   2 From: Ran Wang <ran.wang_1@nxp.com>
   3 Date: Fri, 22 Nov 2019 14:17:32 +0800
   4 Subject: [PATCH] usb: dwc3: Add cache type configuration support
   5
   6 This feature is telling how to configure cache type on 4 different
   7 transfer types: Data Read, Desc Read, Data Write and Desc write. For each
   8 transfer type, controller has a 4-bit register field to enable different
   9 cache type. Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments:
  10 ----------------------------------------------------------------
  11 MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
  12 ----------------------------------------------------------------
  13 AHB      |Cacheable     |Bufferable   |Privilegge |Data
  14 AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
  15 AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
  16 AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
  17 Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
  18 ----------------------------------------------------------------
  19 Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain
  20 signals, which have the same meaning:
  21   Bufferable = Posted
  22   Cacheable = Modifiable = Snoop (negation of No Snoop)
  23
  24 In most cases, driver support is not required unless the default values of
  25 registers are not correct *and* DWC3 node has enabled dma-coherent. So far we
  26 have observed USB device detect failure on some Layerscape platforms if this
  27 programming was not applied.
  28
  29 Related struct:
  30 struct dwc3_cache_type {
  31         u8 transfer_type_datard;
  32         u8 transfer_type_descrd;
  33         u8 transfer_type_datawr;
  34         u8 transfer_type_descwr;
  35 };
  36
  37 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  38 Reviewed-by: Jun Li <jun.li@nxp.com>
  39 ---
  40  drivers/usb/dwc3/core.c | 61 ++++++++++++++++++++++++++++++++++++++++++++-----
  41  drivers/usb/dwc3/core.h | 15 ++++++++++++
  42  2 files changed, 70 insertions(+), 6 deletions(-)
  43
  44 --- a/drivers/usb/dwc3/core.c
  45 +++ b/drivers/usb/dwc3/core.c
  46 @@ -913,6 +913,54 @@ static void dwc3_set_power_down_clk_scal
  47         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  48  }
  49
  50 +#ifdef CONFIG_OF
  51 +struct dwc3_cache_type {
  52 +       u8 transfer_type_datard;
  53 +       u8 transfer_type_descrd;
  54 +       u8 transfer_type_datawr;
  55 +       u8 transfer_type_descwr;
  56 +};
  57 +
  58 +static const struct dwc3_cache_type layerscape_dwc3_cache_type = {
  59 +       .transfer_type_datard = 2,
  60 +       .transfer_type_descrd = 2,
  61 +       .transfer_type_datawr = 2,
  62 +       .transfer_type_descwr = 2,
  63 +};
  64 +
  65 +/**
  66 + * dwc3_set_cache_type - Configure cache type registers
  67 + * @dwc: Pointer to our controller context structure
  68 + */
  69 +static void dwc3_set_cache_type(struct dwc3 *dwc)
  70 +{
  71 +       u32 tmp, reg;
  72 +       const struct dwc3_cache_type *cache_type =
  73 +               device_get_match_data(dwc->dev);
  74 +
  75 +       if (cache_type) {
  76 +               reg = dwc3_readl(dwc->regs,  DWC3_GSBUSCFG0);
  77 +               tmp = reg;
  78 +
  79 +               reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
  80 +               reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
  81 +
  82 +               reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
  83 +               reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
  84 +
  85 +               reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
  86 +               reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
  87 +
  88 +               reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
  89 +               reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
  90 +
  91 +               if (tmp != reg)
  92 +                       dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
  93 +       }
  94 +}
  95 +#endif
  96 +
  97 +
  98  /**
  99   * dwc3_core_init - Low-level initialization of DWC3 Core
 100   * @dwc: Pointer to our controller context structure
 101 @@ -973,6 +1021,10 @@ static int dwc3_core_init(struct dwc3 *d
 102
 103         dwc3_set_incr_burst_type(dwc);
 104
 105 +#ifdef CONFIG_OF
 106 +       dwc3_set_cache_type(dwc);
 107 +#endif
 108 +
 109         usb_phy_set_suspend(dwc->usb2_phy, 0);
 110         usb_phy_set_suspend(dwc->usb3_phy, 0);
 111         ret = phy_power_on(dwc->usb2_generic_phy);
 112 @@ -1890,12 +1942,9 @@ static const struct dev_pm_ops dwc3_dev_
 113
 114  #ifdef CONFIG_OF
 115  static const struct of_device_id of_dwc3_match[] = {
 116 -       {
 117 -               .compatible = "snps,dwc3"
 118 -       },
 119 -       {
 120 -               .compatible = "synopsys,dwc3"
 121 -       },
 122 +       { .compatible = "fsl,layerscape-dwc3", .data = &layerscape_dwc3_cache_type, },
 123 +       { .compatible = "snps,dwc3" },
 124 +       { .compatible = "synopsys,dwc3" },
 125         { },
 126  };
 127  MODULE_DEVICE_TABLE(of, of_dwc3_match);
 128 --- a/drivers/usb/dwc3/core.h
 129 +++ b/drivers/usb/dwc3/core.h
 130 @@ -166,6 +166,21 @@
 131  /* Bit fields */
 132
 133  /* Global SoC Bus Configuration INCRx Register 0 */
 134 +#ifdef CONFIG_OF
 135 +#define DWC3_GSBUSCFG0_DATARD_SHIFT    28
 136 +#define DWC3_GSBUSCFG0_DATARD(n)       (((n) & 0xf)            \
 137 +                       << DWC3_GSBUSCFG0_DATARD_SHIFT)
 138 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT    24
 139 +#define DWC3_GSBUSCFG0_DESCRD(n)       (((n) & 0xf)            \
 140 +                       << DWC3_GSBUSCFG0_DESCRD_SHIFT)
 141 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT    20
 142 +#define DWC3_GSBUSCFG0_DATAWR(n)       (((n) & 0xf)            \
 143 +                       << DWC3_GSBUSCFG0_DATAWR_SHIFT)
 144 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT    16
 145 +#define DWC3_GSBUSCFG0_DESCWR(n)       (((n) & 0xf)            \
 146 +                       << DWC3_GSBUSCFG0_DESCWR_SHIFT)
 147 +#endif
 148 +
 149  #define DWC3_GSBUSCFG0_INCR256BRSTENA  (1 << 7) /* INCR256 burst */
 150  #define DWC3_GSBUSCFG0_INCR128BRSTENA  (1 << 6) /* INCR128 burst */
 151  #define DWC3_GSBUSCFG0_INCR64BRSTENA   (1 << 5) /* INCR64 burst */