target/linux/layerscape/patches-5.4/814-qe-0004-irqchip-qeic-remove-PPCisms-for-QEIC.patch

   1 From c9e8d4b75d48f02731f25e55247017d60c59d510 Mon Sep 17 00:00:00 2001
   2 From: Zhao Qiang <qiang.zhao@nxp.com>
   3 Date: Thu, 27 Apr 2017 09:56:20 +0800
   4 Subject: [PATCH] irqchip/qeic: remove PPCisms for QEIC
   5
   6 QEIC was supported on PowerPC, and dependent on PPC,
   7 Now it is supported on other platforms, so remove PPCisms.
   8
   9 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
  10 ---
  11  drivers/irqchip/irq-qeic.c | 220 +++++++++++++++++++++++----------------------
  12  include/soc/fsl/qe/qe_ic.h | 128 --------------------------
  13  2 files changed, 112 insertions(+), 236 deletions(-)
  14  delete mode 100644 include/soc/fsl/qe/qe_ic.h
  15
  16 --- a/drivers/irqchip/irq-qeic.c
  17 +++ b/drivers/irqchip/irq-qeic.c
  18 @@ -14,7 +14,11 @@
  19  #include <linux/of_address.h>
  20  #include <linux/kernel.h>
  21  #include <linux/init.h>
  22 +#include <linux/irqdomain.h>
  23 +#include <linux/irqchip.h>
  24  #include <linux/errno.h>
  25 +#include <linux/of_address.h>
  26 +#include <linux/of_irq.h>
  27  #include <linux/reboot.h>
  28  #include <linux/slab.h>
  29  #include <linux/stddef.h>
  30 @@ -22,9 +26,8 @@
  31  #include <linux/signal.h>
  32  #include <linux/device.h>
  33  #include <linux/spinlock.h>
  34 -#include <asm/irq.h>
  35 +#include <linux/irq.h>
  36  #include <asm/io.h>
  37 -#include <soc/fsl/qe/qe_ic.h>
  38
  39  #define NR_QE_IC_INTS          64
  40
  41 @@ -82,6 +85,43 @@
  42  #define SIGNAL_HIGH            2
  43  #define SIGNAL_LOW             0
  44
  45 +#define NUM_OF_QE_IC_GROUPS    6
  46 +
  47 +/* Flags when we init the QE IC */
  48 +#define QE_IC_SPREADMODE_GRP_W                 0x00000001
  49 +#define QE_IC_SPREADMODE_GRP_X                 0x00000002
  50 +#define QE_IC_SPREADMODE_GRP_Y                 0x00000004
  51 +#define QE_IC_SPREADMODE_GRP_Z                 0x00000008
  52 +#define QE_IC_SPREADMODE_GRP_RISCA             0x00000010
  53 +#define QE_IC_SPREADMODE_GRP_RISCB             0x00000020
  54 +
  55 +#define QE_IC_LOW_SIGNAL                       0x00000100
  56 +#define QE_IC_HIGH_SIGNAL                      0x00000200
  57 +
  58 +#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH      0x00001000
  59 +#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH      0x00002000
  60 +#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH      0x00004000
  61 +#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH      0x00008000
  62 +#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH      0x00010000
  63 +#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH      0x00020000
  64 +#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH      0x00040000
  65 +#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH      0x00080000
  66 +#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH  0x00100000
  67 +#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH  0x00200000
  68 +#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH  0x00400000
  69 +#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH  0x00800000
  70 +#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT          (12)
  71 +
  72 +/* QE interrupt sources groups */
  73 +enum qe_ic_grp_id {
  74 +       QE_IC_GRP_W = 0,        /* QE interrupt controller group W */
  75 +       QE_IC_GRP_X,            /* QE interrupt controller group X */
  76 +       QE_IC_GRP_Y,            /* QE interrupt controller group Y */
  77 +       QE_IC_GRP_Z,            /* QE interrupt controller group Z */
  78 +       QE_IC_GRP_RISCA,        /* QE interrupt controller RISC group A */
  79 +       QE_IC_GRP_RISCB         /* QE interrupt controller RISC group B */
  80 +};
  81 +
  82  struct qe_ic {
  83         /* Control registers offset */
  84         u32 __iomem *regs;
  85 @@ -260,15 +300,15 @@ static struct qe_ic_info qe_ic_info[] =
  86                 },
  87  };
  88
  89 -static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
  90 +static inline u32 qe_ic_read(__be32  __iomem *base, unsigned int reg)
  91  {
  92 -       return in_be32(base + (reg >> 2));
  93 +       return ioread32be(base + (reg >> 2));
  94  }
  95
  96 -static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
  97 +static inline void qe_ic_write(__be32  __iomem *base, unsigned int reg,
  98                                u32 value)
  99  {
 100 -       out_be32(base + (reg >> 2), value);
 101 +       iowrite32be(value, base + (reg >> 2));
 102  }
 103
 104  static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
 105 @@ -370,8 +410,8 @@ static const struct irq_domain_ops qe_ic
 106         .xlate = irq_domain_xlate_onetwocell,
 107  };
 108
 109 -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 110 -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
 111 +/* Return an interrupt vector or 0 if no interrupt is pending. */
 112 +static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
 113  {
 114         int irq;
 115
 116 @@ -381,13 +421,13 @@ unsigned int qe_ic_get_low_irq(struct qe
 117         irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
 118
 119         if (irq == 0)
 120 -               return NO_IRQ;
 121 +               return 0;
 122
 123         return irq_linear_revmap(qe_ic->irqhost, irq);
 124  }
 125
 126 -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 127 -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 128 +/* Return an interrupt vector or 0 if no interrupt is pending. */
 129 +static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 130  {
 131         int irq;
 132
 133 @@ -397,11 +437,69 @@ unsigned int qe_ic_get_high_irq(struct q
 134         irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
 135
 136         if (irq == 0)
 137 -               return NO_IRQ;
 138 +               return 0;
 139
 140         return irq_linear_revmap(qe_ic->irqhost, irq);
 141  }
 142
 143 +static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
 144 +{
 145 +       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 146 +       unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
 147 +
 148 +       if (cascade_irq != 0)
 149 +               generic_handle_irq(cascade_irq);
 150 +}
 151 +
 152 +static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
 153 +{
 154 +       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 155 +       unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
 156 +
 157 +       if (cascade_irq != 0)
 158 +               generic_handle_irq(cascade_irq);
 159 +}
 160 +
 161 +static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
 162 +{
 163 +       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 164 +       unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
 165 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 166 +
 167 +       if (cascade_irq != 0)
 168 +               generic_handle_irq(cascade_irq);
 169 +
 170 +       chip->irq_eoi(&desc->irq_data);
 171 +}
 172 +
 173 +static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
 174 +{
 175 +       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 176 +       unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
 177 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 178 +
 179 +       if (cascade_irq != 0)
 180 +               generic_handle_irq(cascade_irq);
 181 +
 182 +       chip->irq_eoi(&desc->irq_data);
 183 +}
 184 +
 185 +static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
 186 +{
 187 +       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 188 +       unsigned int cascade_irq;
 189 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 190 +
 191 +       cascade_irq = qe_ic_get_high_irq(qe_ic);
 192 +       if (cascade_irq == 0)
 193 +               cascade_irq = qe_ic_get_low_irq(qe_ic);
 194 +
 195 +       if (cascade_irq != 0)
 196 +               generic_handle_irq(cascade_irq);
 197 +
 198 +       chip->irq_eoi(&desc->irq_data);
 199 +}
 200 +
 201  static int __init qe_ic_init(struct device_node *node, unsigned int flags)
 202  {
 203         struct qe_ic *qe_ic;
 204 @@ -438,7 +536,7 @@ static int __init qe_ic_init(struct devi
 205         qe_ic->virq_high = irq_of_parse_and_map(node, 0);
 206         qe_ic->virq_low = irq_of_parse_and_map(node, 1);
 207
 208 -       if (qe_ic->virq_low == NO_IRQ) {
 209 +       if (qe_ic->virq_low == 0) {
 210                 pr_err("Failed to map QE_IC low IRQ\n");
 211                 ret = -ENOMEM;
 212                 goto err_domain_remove;
 213 @@ -470,7 +568,7 @@ static int __init qe_ic_init(struct devi
 214         irq_set_handler_data(qe_ic->virq_low, qe_ic);
 215         irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
 216
 217 -       if (qe_ic->virq_high != NO_IRQ &&
 218 +       if (qe_ic->virq_high != 0 &&
 219                         qe_ic->virq_high != qe_ic->virq_low) {
 220                 irq_set_handler_data(qe_ic->virq_high, qe_ic);
 221                 irq_set_chained_handler(qe_ic->virq_high,
 222 @@ -488,100 +586,6 @@ err_put_node:
 223         return ret;
 224  }
 225
 226 -void qe_ic_set_highest_priority(unsigned int virq, int high)
 227 -{
 228 -       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 229 -       unsigned int src = virq_to_hw(virq);
 230 -       u32 temp = 0;
 231 -
 232 -       temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
 233 -
 234 -       temp &= ~CICR_HP_MASK;
 235 -       temp |= src << CICR_HP_SHIFT;
 236 -
 237 -       temp &= ~CICR_HPIT_MASK;
 238 -       temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
 239 -
 240 -       qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 241 -}
 242 -
 243 -/* Set Priority level within its group, from 1 to 8 */
 244 -int qe_ic_set_priority(unsigned int virq, unsigned int priority)
 245 -{
 246 -       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 247 -       unsigned int src = virq_to_hw(virq);
 248 -       u32 temp;
 249 -
 250 -       if (priority > 8 || priority == 0)
 251 -               return -EINVAL;
 252 -       if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
 253 -                     "%s: Invalid hw irq number for QEIC\n", __func__))
 254 -               return -EINVAL;
 255 -       if (qe_ic_info[src].pri_reg == 0)
 256 -               return -EINVAL;
 257 -
 258 -       temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
 259 -
 260 -       if (priority < 4) {
 261 -               temp &= ~(0x7 << (32 - priority * 3));
 262 -               temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
 263 -       } else {
 264 -               temp &= ~(0x7 << (24 - priority * 3));
 265 -               temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
 266 -       }
 267 -
 268 -       qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
 269 -
 270 -       return 0;
 271 -}
 272 -
 273 -/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
 274 -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
 275 -{
 276 -       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 277 -       unsigned int src = virq_to_hw(virq);
 278 -       u32 temp, control_reg = QEIC_CICNR, shift = 0;
 279 -
 280 -       if (priority > 2 || priority == 0)
 281 -               return -EINVAL;
 282 -       if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
 283 -                     "%s: Invalid hw irq number for QEIC\n", __func__))
 284 -               return -EINVAL;
 285 -
 286 -       switch (qe_ic_info[src].pri_reg) {
 287 -       case QEIC_CIPZCC:
 288 -               shift = CICNR_ZCC1T_SHIFT;
 289 -               break;
 290 -       case QEIC_CIPWCC:
 291 -               shift = CICNR_WCC1T_SHIFT;
 292 -               break;
 293 -       case QEIC_CIPYCC:
 294 -               shift = CICNR_YCC1T_SHIFT;
 295 -               break;
 296 -       case QEIC_CIPXCC:
 297 -               shift = CICNR_XCC1T_SHIFT;
 298 -               break;
 299 -       case QEIC_CIPRTA:
 300 -               shift = CRICR_RTA1T_SHIFT;
 301 -               control_reg = QEIC_CRICR;
 302 -               break;
 303 -       case QEIC_CIPRTB:
 304 -               shift = CRICR_RTB1T_SHIFT;
 305 -               control_reg = QEIC_CRICR;
 306 -               break;
 307 -       default:
 308 -               return -EINVAL;
 309 -       }
 310 -
 311 -       shift += (2 - priority) * 2;
 312 -       temp = qe_ic_read(qe_ic->regs, control_reg);
 313 -       temp &= ~(SIGNAL_MASK << shift);
 314 -       temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
 315 -       qe_ic_write(qe_ic->regs, control_reg, temp);
 316 -
 317 -       return 0;
 318 -}
 319 -
 320  static int __init init_qe_ic(struct device_node *node,
 321                              struct device_node *parent)
 322  {
 323 --- a/include/soc/fsl/qe/qe_ic.h
 324 +++ /dev/null
 325 @@ -1,128 +0,0 @@
 326 -/* SPDX-License-Identifier: GPL-2.0-or-later */
 327 -/*
 328 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
 329 - *
 330 - * Authors:    Shlomi Gridish <gridish@freescale.com>
 331 - *             Li Yang <leoli@freescale.com>
 332 - *
 333 - * Description:
 334 - * QE IC external definitions and structure.
 335 - */
 336 -#ifndef _ASM_POWERPC_QE_IC_H
 337 -#define _ASM_POWERPC_QE_IC_H
 338 -
 339 -#include <linux/irq.h>
 340 -
 341 -struct device_node;
 342 -struct qe_ic;
 343 -
 344 -#define NUM_OF_QE_IC_GROUPS    6
 345 -
 346 -/* Flags when we init the QE IC */
 347 -#define QE_IC_SPREADMODE_GRP_W                 0x00000001
 348 -#define QE_IC_SPREADMODE_GRP_X                 0x00000002
 349 -#define QE_IC_SPREADMODE_GRP_Y                 0x00000004
 350 -#define QE_IC_SPREADMODE_GRP_Z                 0x00000008
 351 -#define QE_IC_SPREADMODE_GRP_RISCA             0x00000010
 352 -#define QE_IC_SPREADMODE_GRP_RISCB             0x00000020
 353 -
 354 -#define QE_IC_LOW_SIGNAL                       0x00000100
 355 -#define QE_IC_HIGH_SIGNAL                      0x00000200
 356 -
 357 -#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH      0x00001000
 358 -#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH      0x00002000
 359 -#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH      0x00004000
 360 -#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH      0x00008000
 361 -#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH      0x00010000
 362 -#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH      0x00020000
 363 -#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH      0x00040000
 364 -#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH      0x00080000
 365 -#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH  0x00100000
 366 -#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH  0x00200000
 367 -#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH  0x00400000
 368 -#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH  0x00800000
 369 -#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT          (12)
 370 -
 371 -/* QE interrupt sources groups */
 372 -enum qe_ic_grp_id {
 373 -       QE_IC_GRP_W = 0,        /* QE interrupt controller group W */
 374 -       QE_IC_GRP_X,            /* QE interrupt controller group X */
 375 -       QE_IC_GRP_Y,            /* QE interrupt controller group Y */
 376 -       QE_IC_GRP_Z,            /* QE interrupt controller group Z */
 377 -       QE_IC_GRP_RISCA,        /* QE interrupt controller RISC group A */
 378 -       QE_IC_GRP_RISCB         /* QE interrupt controller RISC group B */
 379 -};
 380 -
 381 -#ifdef CONFIG_QUICC_ENGINE
 382 -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
 383 -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
 384 -#else
 385 -static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
 386 -{ return 0; }
 387 -static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 388 -{ return 0; }
 389 -#endif /* CONFIG_QUICC_ENGINE */
 390 -
 391 -void qe_ic_set_highest_priority(unsigned int virq, int high);
 392 -int qe_ic_set_priority(unsigned int virq, unsigned int priority);
 393 -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
 394 -
 395 -static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
 396 -{
 397 -       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 398 -       unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
 399 -
 400 -       if (cascade_irq != NO_IRQ)
 401 -               generic_handle_irq(cascade_irq);
 402 -}
 403 -
 404 -static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
 405 -{
 406 -       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 407 -       unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
 408 -
 409 -       if (cascade_irq != NO_IRQ)
 410 -               generic_handle_irq(cascade_irq);
 411 -}
 412 -
 413 -static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
 414 -{
 415 -       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 416 -       unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
 417 -       struct irq_chip *chip = irq_desc_get_chip(desc);
 418 -
 419 -       if (cascade_irq != NO_IRQ)
 420 -               generic_handle_irq(cascade_irq);
 421 -
 422 -       chip->irq_eoi(&desc->irq_data);
 423 -}
 424 -
 425 -static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
 426 -{
 427 -       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 428 -       unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
 429 -       struct irq_chip *chip = irq_desc_get_chip(desc);
 430 -
 431 -       if (cascade_irq != NO_IRQ)
 432 -               generic_handle_irq(cascade_irq);
 433 -
 434 -       chip->irq_eoi(&desc->irq_data);
 435 -}
 436 -
 437 -static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
 438 -{
 439 -       struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 440 -       unsigned int cascade_irq;
 441 -       struct irq_chip *chip = irq_desc_get_chip(desc);
 442 -
 443 -       cascade_irq = qe_ic_get_high_irq(qe_ic);
 444 -       if (cascade_irq == NO_IRQ)
 445 -               cascade_irq = qe_ic_get_low_irq(qe_ic);
 446 -
 447 -       if (cascade_irq != NO_IRQ)
 448 -               generic_handle_irq(cascade_irq);
 449 -
 450 -       chip->irq_eoi(&desc->irq_data);
 451 -}
 452 -
 453 -#endif /* _ASM_POWERPC_QE_IC_H */