target/linux/layerscape/patches-5.4/806-dma-0022-MLK-22284-1-dmaengine-fsl-edma-v3-add-power-domains-.patch

   1 From 9050c0619cdf5399d19e3683d6fb1db355dda110 Mon Sep 17 00:00:00 2001
   2 From: Robin Gong <yibin.gong@nxp.com>
   3 Date: Wed, 17 Apr 2019 17:05:42 +0800
   4 Subject: [PATCH] MLK-22284-1 dmaengine: fsl-edma-v3: add power domains for
   5  each channel
   6
   7 Add power domains for each dma channel so that edma channel could
   8 know the power state of every dma channel anytime and clear easily
   9 unexpected interrupt which triggered before the last partition reset.
  10
  11 Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  12 Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
  13 (cherry picked from commit 0b6da46b7bdb2284e24757d48466268b9feb5b7c)
  14 ---
  15  .../devicetree/bindings/dma/fsl-edma-v3.txt        | 11 +++-
  16  drivers/dma/fsl-edma-v3.c                          | 58 +++++++++++++++++++++-
  17  2 files changed, 67 insertions(+), 2 deletions(-)
  18
  19 --- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
  20 +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
  21 @@ -30,6 +30,8 @@ Required properties:
  22                 0: not dual fifo case, 1: dualfifo case.
  23         See the SoC's reference manual for all the supported request sources.
  24  - dma-channels : Number of channels supported by the controller
  25 +- power-domains: Power domains for edma channel used.
  26 +- power-domain-names: Power domains name for edma channel used.
  27
  28  Examples:
  29  edma0: dma-controller@40018000 {
  30 @@ -46,6 +48,12 @@ edma0: dma-controller@40018000 {
  31                      <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
  32         interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
  33                           "edma0-chan14-rx", "edma0-chan15-tx";
  34 +       power-domains = <&pd IMX_SC_R_DMA_0_CH12>,
  35 +                       <&pd IMX_SC_R_DMA_0_CH13>,
  36 +                       <&pd IMX_SC_R_DMA_0_CH14>,
  37 +                       <&pd IMX_SC_R_DMA_0_CH15>;
  38 +       power-domain-names = "edma0-chan12", "edma0-chan13",
  39 +                            "edma0-chan14", "edma0-chan15";
  40         status = "okay";
  41  };
  42
  43 @@ -65,7 +73,8 @@ lpuart1: serial@5a070000 {
  44         clock-names = "ipg";
  45         assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
  46         assigned-clock-rates = <80000000>;
  47 -       power-domains = <&pd_dma_lpuart1>;
  48 +       power-domains = <&pd IMX_SC_R_UART_1>,
  49 +       power-domain-names = "uart";
  50         dma-names = "tx","rx";
  51         dmas = <&edma0 15 0 0>,
  52                 <&edma0 14 0 1>;
  53 --- a/drivers/dma/fsl-edma-v3.c
  54 +++ b/drivers/dma/fsl-edma-v3.c
  55 @@ -27,6 +27,8 @@
  56  #include <linux/of_address.h>
  57  #include <linux/of_irq.h>
  58  #include <linux/of_dma.h>
  59 +#include <linux/pm_runtime.h>
  60 +#include <linux/pm_domain.h>
  61
  62  #include "virt-dma.h"
  63
  64 @@ -164,6 +166,7 @@ struct fsl_edma3_chan {
  65         u32                             chn_real_count;
  66         char                            txirq_name[32];
  67         struct platform_device          *pdev;
  68 +       struct device                   *dev;
  69  };
  70
  71  struct fsl_edma3_desc {
  72 @@ -798,8 +801,10 @@ static int fsl_edma3_alloc_chan_resource
  73         fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
  74                                 sizeof(struct fsl_edma3_hw_tcd),
  75                                 32, 0);
  76 +       pm_runtime_get_sync(fsl_chan->dev);
  77         /* clear meaningless pending irq anyway */
  78         writel(1, fsl_chan->membase + EDMA_CH_INT);
  79 +
  80         ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
  81                         fsl_edma3_tx_handler, fsl_chan->edma3->irqflag,
  82                         fsl_chan->txirq_name, fsl_chan);
  83 @@ -830,6 +835,7 @@ static void fsl_edma3_free_chan_resource
  84         dma_pool_destroy(fsl_chan->tcd_pool);
  85         fsl_chan->tcd_pool = NULL;
  86         fsl_chan->used = false;
  87 +       pm_runtime_put_sync(fsl_chan->dev);
  88  }
  89
  90  static void fsl_edma3_synchronize(struct dma_chan *chan)
  91 @@ -839,6 +845,37 @@ static void fsl_edma3_synchronize(struct
  92         vchan_synchronize(&fsl_chan->vchan);
  93  }
  94
  95 +static struct device *fsl_edma3_attach_pd(struct device *dev,
  96 +                                         struct device_node *np, int index)
  97 +{
  98 +       const char *domn = "edma0-chan01";
  99 +       struct device *pd_chan;
 100 +       struct device_link *link;
 101 +       int ret;
 102 +
 103 +       ret = of_property_read_string_index(np, "power-domain-names", index,
 104 +                                               &domn);
 105 +       if (ret) {
 106 +               dev_err(dev, "parse power-domain-names error.(%d)\n", ret);
 107 +               return NULL;
 108 +       }
 109 +
 110 +       pd_chan = dev_pm_domain_attach_by_name(dev, domn);
 111 +       if (!pd_chan)
 112 +               return NULL;
 113 +
 114 +       link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
 115 +                                            DL_FLAG_PM_RUNTIME |
 116 +                                            DL_FLAG_RPM_ACTIVE);
 117 +       if (IS_ERR(link)) {
 118 +               dev_err(dev, "Failed to add device_link to %s: %ld\n", domn,
 119 +                       PTR_ERR(link));
 120 +               return NULL;
 121 +       }
 122 +
 123 +       return pd_chan;
 124 +}
 125 +
 126  static int fsl_edma3_probe(struct platform_device *pdev)
 127  {
 128         struct device_node *np = pdev->dev.of_node;
 129 @@ -962,6 +999,22 @@ static int fsl_edma3_probe(struct platfo
 130                 dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n");
 131                 return ret;
 132         }
 133 +       /* Attach power domains from dts for each dma chanel device */
 134 +       for (i = 0; i < fsl_edma3->n_chans; i++) {
 135 +               struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i];
 136 +               struct device *dev;
 137 +
 138 +               dev = fsl_edma3_attach_pd(&pdev->dev, np, i);
 139 +               if (!dev) {
 140 +                       dev_err(dev, "edma channel attach failed.\n");
 141 +                       return -EINVAL;
 142 +               }
 143 +
 144 +               fsl_chan->dev = dev;
 145 +               /* clear meaningless pending irq anyway */
 146 +               writel(1, fsl_chan->membase + EDMA_CH_INT);
 147 +               pm_runtime_put_sync(dev);
 148 +       }
 149
 150         ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3);
 151         if (ret) {
 152 @@ -970,6 +1023,9 @@ static int fsl_edma3_probe(struct platfo
 153                 return ret;
 154         }
 155
 156 +       pm_runtime_dont_use_autosuspend(&pdev->dev);
 157 +       pm_runtime_enable(&pdev->dev);
 158 +
 159         return 0;
 160  }
 161
 162 @@ -1068,7 +1124,7 @@ static int __init fsl_edma3_init(void)
 163  {
 164         return platform_driver_register(&fsl_edma3_driver);
 165  }
 166 -subsys_initcall(fsl_edma3_init);
 167 +fs_initcall(fsl_edma3_init);
 168
 169  static void __exit fsl_edma3_exit(void)
 170  {