target/linux/layerscape/patches-5.4/806-dma-0021-MLK-21443-dmaengine-fsl-edma-v3-clear-pending-irq-be.patch

   1 From 63c3fd953a620873c722494355a345643607c0a2 Mon Sep 17 00:00:00 2001
   2 From: Robin Gong <yibin.gong@nxp.com>
   3 Date: Thu, 11 Apr 2019 14:36:37 +0800
   4 Subject: [PATCH] MLK-21443: dmaengine: fsl-edma-v3: clear pending irq before
   5  request irq
   6
   7 edma interrupt maybe happened during reboot or watchdog reset, meanwhile
   8 gic never power down on i.mx8QM/QXP, thus the unexpect irq will come in
   9 once edma driver request irq at probe phase. Unfortunately, at that time
  10 that edma channel's power domain which power-up by customer driver such
  11 as audio/uart driver may not be ready, so kernel panic triggered once
  12 touch such edma registers which still not power up in interrupt handler.
  13 Move request irq from probe to alloc dma channel so that edma channel's
  14 power domain has already been powered, besides, clear meaningless
  15 interrupt before request irq.
  16
  17 Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  18 Acked-by: Fugang Duan <fugang.duan@nxp.com>
  19 (cherry picked from commit 0a0d8f8b944094342fda18f23f3ac13b8a73871d)
  20 ---
  21  drivers/dma/fsl-edma-v3.c | 34 ++++++++++++++++++++++------------
  22  1 file changed, 22 insertions(+), 12 deletions(-)
  23
  24 --- a/drivers/dma/fsl-edma-v3.c
  25 +++ b/drivers/dma/fsl-edma-v3.c
  26 @@ -162,7 +162,8 @@ struct fsl_edma3_chan {
  27         int                             is_dfifo;
  28         struct dma_pool                 *tcd_pool;
  29         u32                             chn_real_count;
  30 -       char                            txirq_name[32];
  31 +       char                            txirq_name[32];
  32 +       struct platform_device          *pdev;
  33  };
  34
  35  struct fsl_edma3_desc {
  36 @@ -180,6 +181,7 @@ struct fsl_edma3_reg_save {
  37
  38  struct fsl_edma3_engine {
  39         struct dma_device       dma_dev;
  40 +       unsigned long           irqflag;
  41         struct mutex            fsl_edma3_mutex;
  42         u32                     n_chans;
  43         int                     errirq;
  44 @@ -790,10 +792,23 @@ static struct dma_chan *fsl_edma3_xlate(
  45  static int fsl_edma3_alloc_chan_resources(struct dma_chan *chan)
  46  {
  47         struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
  48 +       struct platform_device *pdev = fsl_chan->pdev;
  49 +       int ret;
  50
  51         fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
  52                                 sizeof(struct fsl_edma3_hw_tcd),
  53                                 32, 0);
  54 +       /* clear meaningless pending irq anyway */
  55 +       writel(1, fsl_chan->membase + EDMA_CH_INT);
  56 +       ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
  57 +                       fsl_edma3_tx_handler, fsl_chan->edma3->irqflag,
  58 +                       fsl_chan->txirq_name, fsl_chan);
  59 +       if (ret) {
  60 +               dev_err(&pdev->dev, "Can't register %s IRQ.\n",
  61 +                       fsl_chan->txirq_name);
  62 +               return ret;
  63 +       }
  64 +
  65         return 0;
  66  }
  67
  68 @@ -803,6 +818,8 @@ static void fsl_edma3_free_chan_resource
  69         unsigned long flags;
  70         LIST_HEAD(head);
  71
  72 +       devm_free_irq(&fsl_chan->pdev->dev, fsl_chan->txirq, fsl_chan);
  73 +
  74         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
  75         fsl_edma3_disable_request(fsl_chan);
  76         fsl_chan->edesc = NULL;
  77 @@ -830,7 +847,6 @@ static int fsl_edma3_probe(struct platfo
  78         struct resource *res;
  79         int len, chans;
  80         int ret, i;
  81 -       unsigned long irqflag = 0;
  82
  83         ret = of_property_read_u32(np, "dma-channels", &chans);
  84         if (ret) {
  85 @@ -845,7 +861,7 @@ static int fsl_edma3_probe(struct platfo
  86
  87         /* Audio edma rx/tx channel shared interrupt */
  88         if (of_property_read_bool(np, "shared-interrupt"))
  89 -               irqflag = IRQF_SHARED;
  90 +               fsl_edma3->irqflag = IRQF_SHARED;
  91
  92         fsl_edma3->swap = of_device_is_compatible(np, "fsl,imx8qm-adma");
  93         fsl_edma3->n_chans = chans;
  94 @@ -853,12 +869,13 @@ static int fsl_edma3_probe(struct platfo
  95         INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels);
  96         for (i = 0; i < fsl_edma3->n_chans; i++) {
  97                 struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i];
  98 -               const char *txirq_name = fsl_chan->txirq_name;
  99 +               const char *txirq_name;
 100                 char chanid[3], id_len = 0;
 101                 char *p = chanid;
 102                 unsigned long val;
 103
 104                 fsl_chan->edma3 = fsl_edma3;
 105 +               fsl_chan->pdev = pdev;
 106                 fsl_chan->pm_state = RUNNING;
 107                 fsl_chan->idle = true;
 108                 /* Get per channel membase */
 109 @@ -904,14 +921,7 @@ static int fsl_edma3_probe(struct platfo
 110                         return fsl_chan->txirq;
 111                 }
 112
 113 -               ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
 114 -                               fsl_edma3_tx_handler, irqflag, txirq_name,
 115 -                               fsl_chan);
 116 -               if (ret) {
 117 -                       dev_err(&pdev->dev, "Can't register %s IRQ.\n",
 118 -                               txirq_name);
 119 -                       return ret;
 120 -               }
 121 +               memcpy(fsl_chan->txirq_name, txirq_name, strlen(txirq_name));
 122
 123                 fsl_chan->vchan.desc_free = fsl_edma3_free_desc;
 124                 vchan_init(&fsl_chan->vchan, &fsl_edma3->dma_dev);