target/linux/layerscape/patches-5.4/806-dma-0005-MLK-15003-2-Document-fsl_edma_v3-update-document.patch

   1 From c5a10c542853662bf85884aecee1c086ecec9acf Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
   3 Date: Mon, 5 Jun 2017 11:37:57 +0800
   4 Subject: [PATCH] MLK-15003-2: Document: fsl_edma_v3: update document
   5
   6 update fsl_edma_v3 document for #dma-cell is changed
   7 one more cell is added, which is for local/remote access.
   8
   9 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
  10 (cherry picked from commit 65543fb7fefbdb7df4cb60931a88f61507c5073f)
  11 ---
  12  Documentation/devicetree/bindings/dma/fsl-edma-v3.txt | 10 ++++++----
  13  1 file changed, 6 insertions(+), 4 deletions(-)
  14
  15 --- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
  16 +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
  17 @@ -14,11 +14,13 @@ Required properties:
  18  - interrupts : A list of interrupt-specifiers, each channel has one interrupt.
  19  - interrupt-names : Should contain:
  20         "edma-chan12-tx" - the channel12 transmission interrupt
  21 -- #dma-cells : Must be <3>.
  22 +- #dma-cells : Must be <4>.
  23         The 1st cell specifies the channel ID.
  24         The 2nd cell specifies the channel priority.
  25         The 3rd cell specifies the channel type like for transmit or receive:
  26                 0: transmit, 1: receive.
  27 +       The 4th cell specifies the local access or remote access:
  28 +               0: local, 1: remote.
  29         See the SoC's reference manual for all the supported request sources.
  30  - dma-channels : Number of channels supported by the controller
  31
  32 @@ -29,7 +31,7 @@ edma0: dma-controller@40018000 {
  33               <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
  34               <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
  35               <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
  36 -       #dma-cells = <3>;
  37 +       #dma-cells = <4>;
  38         dma-channels = <4>;
  39         interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
  40                      <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
  41 @@ -58,7 +60,7 @@ lpuart1: serial@5a070000 {
  42         assigned-clock-rates = <80000000>;
  43         power-domains = <&pd_dma_lpuart1>;
  44         dma-names = "tx","rx";
  45 -       dmas = <&edma0 15 0 0>,
  46 -               <&edma0 14 0 1>;
  47 +       dmas = <&edma0 15 0 0 0>,
  48 +               <&edma0 14 0 1 0>;
  49         status = "disabled";
  50  };