target/linux/layerscape/patches-5.4/805-display-0003-drm-bridge-add-Cadence-MHDP-HDMI-DP-API.patch

   1 From d94a1a8c31cab273b3409c9c380a8089a794f592 Mon Sep 17 00:00:00 2001
   2 From: Sandor Yu <Sandor.yu@nxp.com>
   3 Date: Wed, 10 Jul 2019 14:22:12 +0800
   4 Subject: [PATCH] drm: bridge: add Cadence MHDP HDMI/DP API
   5
   6 Changes made in the low level driver (cdn-dp-reg.*):
   7 - moved it to from drivers/gpu/drm/rockchip to
   8  drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c and
   9  include/drm/bridge/cdns-mhdp-common.h
  10 - functions for sending/receiving commands are now public
  11 - added functions for reading registers and link training adjustment
  12
  13 Changes made in RK's driver (cdn-dp-core.*):
  14 - Moved audio_info and audio_pdev fields from cdn_dp_device to
  15   cdns_mhdp_device structure.
  16
  17 Signed-off-by: Quentin Schulz<quentin.schulz@free-electrons.com>
  18 Signed-off-by: Piotr Sroka <piotrs@cadence.com>
  19 Signed-off-by: Damian Kos <dkos@cadence.com>
  20 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
  21 ---
  22  drivers/gpu/drm/bridge/Kconfig                    |    2 +
  23  drivers/gpu/drm/bridge/Makefile                   |    1 +
  24  drivers/gpu/drm/bridge/cadence/Kconfig            |    7 +
  25  drivers/gpu/drm/bridge/cadence/Makefile           |    3 +
  26  drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 1165 +++++++++++++++++++++
  27  drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c   |  296 ++++++
  28  drivers/gpu/drm/bridge/cadence/cdns-mhdp.h        |  209 ++++
  29  drivers/gpu/drm/rockchip/Kconfig                  |    4 +-
  30  drivers/gpu/drm/rockchip/Makefile                 |    2 +-
  31  drivers/gpu/drm/rockchip/cdn-dp-core.c            |   48 +-
  32  drivers/gpu/drm/rockchip/cdn-dp-core.h            |    5 +-
  33  drivers/gpu/drm/rockchip/cdn-dp-reg.c             |  968 -----------------
  34  drivers/gpu/drm/rockchip/cdn-dp-reg.h             |  546 ----------
  35  include/drm/bridge/cdns-mhdp-cbs.h                |   29 +
  36  include/drm/bridge/cdns-mhdp-common.h             |  704 +++++++++++++
  37  15 files changed, 2446 insertions(+), 1543 deletions(-)
  38  create mode 100644 drivers/gpu/drm/bridge/cadence/Kconfig
  39  create mode 100644 drivers/gpu/drm/bridge/cadence/Makefile
  40  create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
  41  create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c
  42  create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp.h
  43  delete mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c
  44  delete mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h
  45  create mode 100644 include/drm/bridge/cdns-mhdp-cbs.h
  46  create mode 100644 include/drm/bridge/cdns-mhdp-common.h
  47
  48 --- a/drivers/gpu/drm/bridge/Kconfig
  49 +++ b/drivers/gpu/drm/bridge/Kconfig
  50 @@ -154,6 +154,8 @@ source "drivers/gpu/drm/bridge/analogix/
  51
  52  source "drivers/gpu/drm/bridge/adv7511/Kconfig"
  53
  54 +source "drivers/gpu/drm/bridge/cadence/Kconfig"
  55 +
  56  source "drivers/gpu/drm/bridge/synopsys/Kconfig"
  57
  58  endmenu
  59 --- a/drivers/gpu/drm/bridge/Makefile
  60 +++ b/drivers/gpu/drm/bridge/Makefile
  61 @@ -16,4 +16,5 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogi
  62  obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
  63  obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
  64  obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
  65 +obj-y += cadence/
  66  obj-y += synopsys/
  67 --- /dev/null
  68 +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
  69 @@ -0,0 +1,7 @@
  70 +config DRM_CDNS_MHDP
  71 +       tristate "Cadence MHDP COMMON API driver"
  72 +       select DRM_KMS_HELPER
  73 +       select DRM_PANEL_BRIDGE
  74 +       depends on OF
  75 +       help
  76 +         Support Cadence MHDP API library.
  77 --- /dev/null
  78 +++ b/drivers/gpu/drm/bridge/cadence/Makefile
  79 @@ -0,0 +1,3 @@
  80 +#ccflags-y := -Iinclude/drm
  81 +
  82 +obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp-common.o cdns-mhdp-hdmi.o
  83 --- /dev/null
  84 +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
  85 @@ -0,0 +1,1165 @@
  86 +// SPDX-License-Identifier: GPL-2.0
  87 +/*
  88 + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  89 + * Author: Chris Zhong <zyw@rock-chips.com>
  90 + *
  91 + * This software is licensed under the terms of the GNU General Public
  92 + * License version 2, as published by the Free Software Foundation, and
  93 + * may be copied, distributed, and modified under those terms.
  94 + *
  95 + * This program is distributed in the hope that it will be useful,
  96 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  97 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  98 + * GNU General Public License for more details.
  99 + */
 100 +
 101 +#include <linux/clk.h>
 102 +#include <linux/delay.h>
 103 +#include <linux/device.h>
 104 +#include <linux/io.h>
 105 +#include <linux/iopoll.h>
 106 +#include <linux/reset.h>
 107 +
 108 +#include <asm/unaligned.h>
 109 +
 110 +#include <drm/bridge/cdns-mhdp-common.h>
 111 +#include <drm/drm_modes.h>
 112 +#include <drm/drm_print.h>
 113 +
 114 +#define CDNS_DP_SPDIF_CLK              200000000
 115 +#define FW_ALIVE_TIMEOUT_US            1000000
 116 +#define MAILBOX_RETRY_US               1000
 117 +#define MAILBOX_TIMEOUT_US             5000000
 118 +#define LINK_TRAINING_RETRY_MS         20
 119 +#define LINK_TRAINING_TIMEOUT_MS       500
 120 +
 121 +static inline u32 get_unaligned_be24(const void *p)
 122 +{
 123 +       const u8 *_p = p;
 124 +
 125 +       return _p[0] << 16 | _p[1] << 8 | _p[2];
 126 +}
 127 +
 128 +static inline void put_unaligned_be24(u32 val, void *p)
 129 +{
 130 +       u8 *_p = p;
 131 +
 132 +       _p[0] = val >> 16;
 133 +       _p[1] = val >> 8;
 134 +       _p[2] = val;
 135 +}
 136 +
 137 +void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk)
 138 +{
 139 +       writel(clk / 1000000, mhdp->regs + SW_CLK_H);
 140 +}
 141 +EXPORT_SYMBOL(cdns_mhdp_set_fw_clk);
 142 +
 143 +void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp)
 144 +{
 145 +       u32 val;
 146 +
 147 +       val = DPTX_FRMR_DATA_CLK_RSTN_EN |
 148 +             DPTX_FRMR_DATA_CLK_EN |
 149 +             DPTX_PHY_DATA_RSTN_EN |
 150 +             DPTX_PHY_DATA_CLK_EN |
 151 +             DPTX_PHY_CHAR_RSTN_EN |
 152 +             DPTX_PHY_CHAR_CLK_EN |
 153 +             SOURCE_AUX_SYS_CLK_RSTN_EN |
 154 +             SOURCE_AUX_SYS_CLK_EN |
 155 +             DPTX_SYS_CLK_RSTN_EN |
 156 +             DPTX_SYS_CLK_EN |
 157 +             CFG_DPTX_VIF_CLK_RSTN_EN |
 158 +             CFG_DPTX_VIF_CLK_EN;
 159 +       writel(val, mhdp->regs + SOURCE_DPTX_CAR);
 160 +
 161 +       val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN;
 162 +       writel(val, mhdp->regs + SOURCE_PHY_CAR);
 163 +
 164 +       val = SOURCE_PKT_SYS_RSTN_EN |
 165 +             SOURCE_PKT_SYS_CLK_EN |
 166 +             SOURCE_PKT_DATA_RSTN_EN |
 167 +             SOURCE_PKT_DATA_CLK_EN;
 168 +       writel(val, mhdp->regs + SOURCE_PKT_CAR);
 169 +
 170 +       val = SPDIF_CDR_CLK_RSTN_EN |
 171 +             SPDIF_CDR_CLK_EN |
 172 +             SOURCE_AIF_SYS_RSTN_EN |
 173 +             SOURCE_AIF_SYS_CLK_EN |
 174 +             SOURCE_AIF_CLK_RSTN_EN |
 175 +             SOURCE_AIF_CLK_EN;
 176 +       writel(val, mhdp->regs + SOURCE_AIF_CAR);
 177 +
 178 +       val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN |
 179 +             SOURCE_CIPHER_SYS_CLK_EN |
 180 +             SOURCE_CIPHER_CHAR_CLK_RSTN_EN |
 181 +             SOURCE_CIPHER_CHAR_CLK_EN;
 182 +       writel(val, mhdp->regs + SOURCE_CIPHER_CAR);
 183 +
 184 +       val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN |
 185 +             SOURCE_CRYPTO_SYS_CLK_EN;
 186 +       writel(val, mhdp->regs + SOURCE_CRYPTO_CAR);
 187 +
 188 +       /* enable Mailbox and PIF interrupt */
 189 +       writel(0, mhdp->regs + APB_INT_MASK);
 190 +}
 191 +EXPORT_SYMBOL(cdns_mhdp_clock_reset);
 192 +
 193 +int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
 194 +{
 195 +       int val, ret;
 196 +
 197 +       ret = readx_poll_timeout(readl, mhdp->regs + MAILBOX_EMPTY_ADDR,
 198 +                                val, !val, MAILBOX_RETRY_US,
 199 +                                MAILBOX_TIMEOUT_US);
 200 +       if (ret < 0)
 201 +               return ret;
 202 +
 203 +       return readl(mhdp->regs + MAILBOX0_RD_DATA) & 0xff;
 204 +}
 205 +EXPORT_SYMBOL(cdns_mhdp_mailbox_read);
 206 +
 207 +static int cdp_dp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
 208 +{
 209 +       int ret, full;
 210 +
 211 +       ret = readx_poll_timeout(readl, mhdp->regs + MAILBOX_FULL_ADDR,
 212 +                                full, !full, MAILBOX_RETRY_US,
 213 +                                MAILBOX_TIMEOUT_US);
 214 +       if (ret < 0)
 215 +               return ret;
 216 +
 217 +       writel(val, mhdp->regs + MAILBOX0_WR_DATA);
 218 +
 219 +       return 0;
 220 +}
 221 +
 222 +int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
 223 +                                             u8 module_id, u8 opcode,
 224 +                                             u16 req_size)
 225 +{
 226 +       u32 mbox_size, i;
 227 +       u8 header[4];
 228 +       int ret;
 229 +
 230 +       /* read the header of the message */
 231 +       for (i = 0; i < 4; i++) {
 232 +               ret = cdns_mhdp_mailbox_read(mhdp);
 233 +               if (ret < 0)
 234 +                       return ret;
 235 +
 236 +               header[i] = ret;
 237 +       }
 238 +
 239 +       mbox_size = get_unaligned_be16(header + 2);
 240 +
 241 +       if (opcode != header[0] || module_id != header[1] ||
 242 +           req_size != mbox_size) {
 243 +               /*
 244 +                * If the message in mailbox is not what we want, we need to
 245 +                * clear the mailbox by reading its contents.
 246 +                */
 247 +               for (i = 0; i < mbox_size; i++)
 248 +                       if (cdns_mhdp_mailbox_read(mhdp) < 0)
 249 +                               break;
 250 +
 251 +               return -EINVAL;
 252 +       }
 253 +
 254 +       return 0;
 255 +}
 256 +EXPORT_SYMBOL(cdns_mhdp_mailbox_validate_receive);
 257 +
 258 +int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp,
 259 +                                         u8 *buff, u16 buff_size)
 260 +{
 261 +       u32 i;
 262 +       int ret;
 263 +
 264 +       for (i = 0; i < buff_size; i++) {
 265 +               ret = cdns_mhdp_mailbox_read(mhdp);
 266 +               if (ret < 0)
 267 +                       return ret;
 268 +
 269 +               buff[i] = ret;
 270 +       }
 271 +
 272 +       return 0;
 273 +}
 274 +EXPORT_SYMBOL(cdns_mhdp_mailbox_read_receive);
 275 +
 276 +int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id,
 277 +                                 u8 opcode, u16 size, u8 *message)
 278 +{
 279 +       u8 header[4];
 280 +       int ret, i;
 281 +
 282 +       header[0] = opcode;
 283 +       header[1] = module_id;
 284 +       put_unaligned_be16(size, header + 2);
 285 +
 286 +       for (i = 0; i < 4; i++) {
 287 +               ret = cdp_dp_mailbox_write(mhdp, header[i]);
 288 +               if (ret)
 289 +                       return ret;
 290 +       }
 291 +
 292 +       for (i = 0; i < size; i++) {
 293 +               ret = cdp_dp_mailbox_write(mhdp, message[i]);
 294 +               if (ret)
 295 +                       return ret;
 296 +       }
 297 +
 298 +       return 0;
 299 +}
 300 +EXPORT_SYMBOL(cdns_mhdp_mailbox_send);
 301 +
 302 +int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr)
 303 +{
 304 +       u8 msg[4], resp[8];
 305 +       u32 val;
 306 +       int ret;
 307 +
 308 +       if (addr == 0) {
 309 +               ret = -EINVAL;
 310 +               goto err_reg_read;
 311 +       }
 312 +
 313 +       put_unaligned_be32(addr, msg);
 314 +
 315 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
 316 +                                    GENERAL_READ_REGISTER,
 317 +                                    sizeof(msg), msg);
 318 +       if (ret)
 319 +               goto err_reg_read;
 320 +
 321 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL,
 322 +                                                GENERAL_READ_REGISTER,
 323 +                                                sizeof(resp));
 324 +       if (ret)
 325 +               goto err_reg_read;
 326 +
 327 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, resp, sizeof(resp));
 328 +       if (ret)
 329 +               goto err_reg_read;
 330 +
 331 +       /* Returned address value should be the same as requested */
 332 +       if (memcmp(msg, resp, sizeof(msg))) {
 333 +               ret = -EINVAL;
 334 +               goto err_reg_read;
 335 +       }
 336 +
 337 +       val = get_unaligned_be32(resp + 4);
 338 +
 339 +       return val;
 340 +err_reg_read:
 341 +       DRM_DEV_ERROR(mhdp->dev, "Failed to read register.\n");
 342 +
 343 +       return ret;
 344 +}
 345 +EXPORT_SYMBOL(cdns_mhdp_reg_read);
 346 +
 347 +int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val)
 348 +{
 349 +       u8 msg[8];
 350 +
 351 +       put_unaligned_be32(addr, msg);
 352 +       put_unaligned_be32(val, msg + 4);
 353 +
 354 +       return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
 355 +                                     GENERAL_WRITE_REGISTER, sizeof(msg), msg);
 356 +}
 357 +EXPORT_SYMBOL(cdns_mhdp_reg_write);
 358 +
 359 +int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
 360 +                                  u8 start_bit, u8 bits_no, u32 val)
 361 +{
 362 +       u8 field[8];
 363 +
 364 +       put_unaligned_be16(addr, field);
 365 +       field[2] = start_bit;
 366 +       field[3] = bits_no;
 367 +       put_unaligned_be32(val, field + 4);
 368 +
 369 +       return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 370 +                                     DPTX_WRITE_FIELD, sizeof(field), field);
 371 +}
 372 +EXPORT_SYMBOL(cdns_mhdp_reg_write_bit);
 373 +
 374 +int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
 375 +                       u32 addr, u8 *data, u16 len)
 376 +{
 377 +       u8 msg[5], reg[5];
 378 +       int ret;
 379 +
 380 +       put_unaligned_be16(len, msg);
 381 +       put_unaligned_be24(addr, msg + 2);
 382 +
 383 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 384 +                                    DPTX_READ_DPCD, sizeof(msg), msg);
 385 +       if (ret)
 386 +               goto err_dpcd_read;
 387 +
 388 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
 389 +                                                DPTX_READ_DPCD,
 390 +                                                sizeof(reg) + len);
 391 +       if (ret)
 392 +               goto err_dpcd_read;
 393 +
 394 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
 395 +       if (ret)
 396 +               goto err_dpcd_read;
 397 +
 398 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len);
 399 +
 400 +err_dpcd_read:
 401 +       return ret;
 402 +}
 403 +EXPORT_SYMBOL(cdns_mhdp_dpcd_read);
 404 +
 405 +int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value)
 406 +{
 407 +       u8 msg[6], reg[5];
 408 +       int ret;
 409 +
 410 +       put_unaligned_be16(1, msg);
 411 +       put_unaligned_be24(addr, msg + 2);
 412 +       msg[5] = value;
 413 +
 414 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 415 +                                    DPTX_WRITE_DPCD, sizeof(msg), msg);
 416 +       if (ret)
 417 +               goto err_dpcd_write;
 418 +
 419 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
 420 +                                                DPTX_WRITE_DPCD, sizeof(reg));
 421 +       if (ret)
 422 +               goto err_dpcd_write;
 423 +
 424 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
 425 +       if (ret)
 426 +               goto err_dpcd_write;
 427 +
 428 +       if (addr != get_unaligned_be24(reg + 2))
 429 +               ret = -EINVAL;
 430 +
 431 +err_dpcd_write:
 432 +       if (ret)
 433 +               DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret);
 434 +       return ret;
 435 +}
 436 +EXPORT_SYMBOL(cdns_mhdp_dpcd_write);
 437 +
 438 +int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem,
 439 +                           u32 i_size, const u32 *d_mem, u32 d_size)
 440 +{
 441 +       u32 reg;
 442 +       int i, ret;
 443 +
 444 +       /* reset ucpu before load firmware*/
 445 +       writel(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET,
 446 +              mhdp->regs + APB_CTRL);
 447 +
 448 +       for (i = 0; i < i_size; i += 4)
 449 +               writel(*i_mem++, mhdp->regs + ADDR_IMEM + i);
 450 +
 451 +       for (i = 0; i < d_size; i += 4)
 452 +               writel(*d_mem++, mhdp->regs + ADDR_DMEM + i);
 453 +
 454 +       /* un-reset ucpu */
 455 +       writel(0, mhdp->regs + APB_CTRL);
 456 +
 457 +       /* check the keep alive register to make sure fw working */
 458 +       ret = readx_poll_timeout(readl, mhdp->regs + KEEP_ALIVE,
 459 +                                reg, reg, 2000, FW_ALIVE_TIMEOUT_US);
 460 +       if (ret < 0) {
 461 +               DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n",
 462 +                             reg);
 463 +               return -EINVAL;
 464 +       }
 465 +
 466 +       reg = readl(mhdp->regs + VER_L) & 0xff;
 467 +       mhdp->fw_version = reg;
 468 +       reg = readl(mhdp->regs + VER_H) & 0xff;
 469 +       mhdp->fw_version |= reg << 8;
 470 +       reg = readl(mhdp->regs + VER_LIB_L_ADDR) & 0xff;
 471 +       mhdp->fw_version |= reg << 16;
 472 +       reg = readl(mhdp->regs + VER_LIB_H_ADDR) & 0xff;
 473 +       mhdp->fw_version |= reg << 24;
 474 +
 475 +       DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version);
 476 +
 477 +       return 0;
 478 +}
 479 +EXPORT_SYMBOL(cdns_mhdp_load_firmware);
 480 +
 481 +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable)
 482 +{
 483 +       u8 msg[5];
 484 +       int ret, i;
 485 +
 486 +       msg[0] = GENERAL_MAIN_CONTROL;
 487 +       msg[1] = MB_MODULE_ID_GENERAL;
 488 +       msg[2] = 0;
 489 +       msg[3] = 1;
 490 +       msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
 491 +
 492 +       for (i = 0; i < sizeof(msg); i++) {
 493 +               ret = cdp_dp_mailbox_write(mhdp, msg[i]);
 494 +               if (ret)
 495 +                       goto err_set_firmware_active;
 496 +       }
 497 +
 498 +       /* read the firmware state */
 499 +       for (i = 0; i < sizeof(msg); i++)  {
 500 +               ret = cdns_mhdp_mailbox_read(mhdp);
 501 +               if (ret < 0)
 502 +                       goto err_set_firmware_active;
 503 +
 504 +               msg[i] = ret;
 505 +       }
 506 +
 507 +       ret = 0;
 508 +
 509 +err_set_firmware_active:
 510 +       if (ret < 0)
 511 +               DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n");
 512 +       return ret;
 513 +}
 514 +EXPORT_SYMBOL(cdns_mhdp_set_firmware_active);
 515 +
 516 +int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, u8 lanes, bool flip)
 517 +{
 518 +       u8 msg[8];
 519 +       int ret;
 520 +
 521 +       msg[0] = CDNS_DP_MAX_LINK_RATE;
 522 +       msg[1] = lanes | SCRAMBLER_EN;
 523 +       msg[2] = VOLTAGE_LEVEL_2;
 524 +       msg[3] = PRE_EMPHASIS_LEVEL_3;
 525 +       msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
 526 +       msg[5] = FAST_LT_NOT_SUPPORT;
 527 +       msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL;
 528 +       msg[7] = ENHANCED;
 529 +
 530 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 531 +                                    DPTX_SET_HOST_CAPABILITIES,
 532 +                                    sizeof(msg), msg);
 533 +       if (ret)
 534 +               goto err_set_host_cap;
 535 +
 536 +/* TODO Sandor */
 537 +//     ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL,
 538 +//                               AUX_HOST_INVERT);
 539 +
 540 +err_set_host_cap:
 541 +       if (ret)
 542 +               DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret);
 543 +       return ret;
 544 +}
 545 +EXPORT_SYMBOL(cdns_mhdp_set_host_cap);
 546 +
 547 +int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp)
 548 +{
 549 +       u8 msg[5];
 550 +       int ret;
 551 +
 552 +       memset(msg, 0, sizeof(msg));
 553 +
 554 +       msg[0] = DPTX_EVENT_ENABLE_HPD | DPTX_EVENT_ENABLE_TRAINING;
 555 +
 556 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 557 +                                    DPTX_ENABLE_EVENT, sizeof(msg), msg);
 558 +       if (ret)
 559 +               DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret);
 560 +
 561 +       return ret;
 562 +}
 563 +EXPORT_SYMBOL(cdns_mhdp_event_config);
 564 +
 565 +u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp)
 566 +{
 567 +       return readl(mhdp->regs + SW_EVENTS0);
 568 +}
 569 +EXPORT_SYMBOL(cdns_mhdp_get_event);
 570 +
 571 +int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp)
 572 +{
 573 +       u8 status;
 574 +       int ret;
 575 +
 576 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 577 +                                    DPTX_HPD_STATE, 0, NULL);
 578 +       if (ret)
 579 +               goto err_get_hpd;
 580 +
 581 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
 582 +                                                DPTX_HPD_STATE,
 583 +                                                sizeof(status));
 584 +       if (ret)
 585 +               goto err_get_hpd;
 586 +
 587 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status));
 588 +       if (ret)
 589 +               goto err_get_hpd;
 590 +
 591 +       return status;
 592 +
 593 +err_get_hpd:
 594 +       DRM_DEV_ERROR(mhdp->dev, "get hpd status failed: %d\n", ret);
 595 +       return ret;
 596 +}
 597 +EXPORT_SYMBOL(cdns_mhdp_get_hpd_status);
 598 +
 599 +int cdns_mhdp_get_edid_block(void *data, u8 *edid,
 600 +                         unsigned int block, size_t length)
 601 +{
 602 +       struct cdns_mhdp_device *mhdp = data;
 603 +       u8 msg[2], reg[2], i;
 604 +       int ret;
 605 +
 606 +       for (i = 0; i < 4; i++) {
 607 +               msg[0] = block / 2;
 608 +               msg[1] = block % 2;
 609 +
 610 +               ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 611 +                                            DPTX_GET_EDID, sizeof(msg), msg);
 612 +               if (ret)
 613 +                       continue;
 614 +
 615 +               ret = cdns_mhdp_mailbox_validate_receive(mhdp,
 616 +                                                        MB_MODULE_ID_DP_TX,
 617 +                                                        DPTX_GET_EDID,
 618 +                                                        sizeof(reg) + length);
 619 +               if (ret)
 620 +                       continue;
 621 +
 622 +               ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
 623 +               if (ret)
 624 +                       continue;
 625 +
 626 +               ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length);
 627 +               if (ret)
 628 +                       continue;
 629 +
 630 +               if (reg[0] == length && reg[1] == block / 2)
 631 +                       break;
 632 +       }
 633 +
 634 +       if (ret)
 635 +               DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n",
 636 +                             block, ret);
 637 +
 638 +       return ret;
 639 +}
 640 +EXPORT_SYMBOL(cdns_mhdp_get_edid_block);
 641 +
 642 +static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp)
 643 +{
 644 +       unsigned long timeout;
 645 +       u8 msg, event[2];
 646 +       int ret;
 647 +
 648 +       msg = LINK_TRAINING_RUN;
 649 +
 650 +       /* start training */
 651 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 652 +                                    DPTX_TRAINING_CONTROL, sizeof(msg), &msg);
 653 +       if (ret)
 654 +               goto err_training_start;
 655 +
 656 +       timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS);
 657 +       while (time_before(jiffies, timeout)) {
 658 +               msleep(LINK_TRAINING_RETRY_MS);
 659 +               ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 660 +                                            DPTX_READ_EVENT, 0, NULL);
 661 +               if (ret)
 662 +                       goto err_training_start;
 663 +
 664 +               ret = cdns_mhdp_mailbox_validate_receive(mhdp,
 665 +                                                        MB_MODULE_ID_DP_TX,
 666 +                                                        DPTX_READ_EVENT,
 667 +                                                        sizeof(event));
 668 +               if (ret)
 669 +                       goto err_training_start;
 670 +
 671 +               ret = cdns_mhdp_mailbox_read_receive(mhdp, event,
 672 +                                                    sizeof(event));
 673 +               if (ret)
 674 +                       goto err_training_start;
 675 +
 676 +               if (event[1] & EQ_PHASE_FINISHED)
 677 +                       return 0;
 678 +       }
 679 +
 680 +       ret = -ETIMEDOUT;
 681 +
 682 +err_training_start:
 683 +       DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret);
 684 +       return ret;
 685 +}
 686 +
 687 +static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp)
 688 +{
 689 +       u8 status[10];
 690 +       int ret;
 691 +
 692 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 693 +                                    DPTX_READ_LINK_STAT, 0, NULL);
 694 +       if (ret)
 695 +               goto err_get_training_status;
 696 +
 697 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
 698 +                                                DPTX_READ_LINK_STAT,
 699 +                                                sizeof(status));
 700 +       if (ret)
 701 +               goto err_get_training_status;
 702 +
 703 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status));
 704 +       if (ret)
 705 +               goto err_get_training_status;
 706 +
 707 +       mhdp->dp.link.rate = drm_dp_bw_code_to_link_rate(status[0]);
 708 +       mhdp->dp.link.num_lanes = status[1];
 709 +
 710 +err_get_training_status:
 711 +       if (ret)
 712 +               DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n",
 713 +                             ret);
 714 +       return ret;
 715 +}
 716 +
 717 +int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp)
 718 +{
 719 +       int ret;
 720 +
 721 +       ret = cdns_mhdp_training_start(mhdp);
 722 +       if (ret) {
 723 +               DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n",
 724 +                             ret);
 725 +               return ret;
 726 +       }
 727 +
 728 +       ret = cdns_mhdp_get_training_status(mhdp);
 729 +       if (ret) {
 730 +               DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n",
 731 +                             ret);
 732 +               return ret;
 733 +       }
 734 +
 735 +       DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.link.rate,
 736 +                         mhdp->dp.link.num_lanes);
 737 +       return ret;
 738 +}
 739 +EXPORT_SYMBOL(cdns_mhdp_train_link);
 740 +
 741 +int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active)
 742 +{
 743 +       u8 msg;
 744 +       int ret;
 745 +
 746 +       msg = !!active;
 747 +
 748 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
 749 +                                    DPTX_SET_VIDEO, sizeof(msg), &msg);
 750 +       if (ret)
 751 +               DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret);
 752 +
 753 +       return ret;
 754 +}
 755 +EXPORT_SYMBOL(cdns_mhdp_set_video_status);
 756 +
 757 +static int cdns_mhdp_get_msa_misc(struct video_info *video,
 758 +                                 struct drm_display_mode *mode)
 759 +{
 760 +       u32 msa_misc;
 761 +       u8 val[2] = {0};
 762 +
 763 +       switch (video->color_fmt) {
 764 +       case PXL_RGB:
 765 +       case Y_ONLY:
 766 +               val[0] = 0;
 767 +               break;
 768 +       /* set YUV default color space conversion to BT601 */
 769 +       case YCBCR_4_4_4:
 770 +               val[0] = 6 + BT_601 * 8;
 771 +               break;
 772 +       case YCBCR_4_2_2:
 773 +               val[0] = 5 + BT_601 * 8;
 774 +               break;
 775 +       case YCBCR_4_2_0:
 776 +               val[0] = 5;
 777 +               break;
 778 +       };
 779 +
 780 +       switch (video->color_depth) {
 781 +       case 6:
 782 +               val[1] = 0;
 783 +               break;
 784 +       case 8:
 785 +               val[1] = 1;
 786 +               break;
 787 +       case 10:
 788 +               val[1] = 2;
 789 +               break;
 790 +       case 12:
 791 +               val[1] = 3;
 792 +               break;
 793 +       case 16:
 794 +               val[1] = 4;
 795 +               break;
 796 +       };
 797 +
 798 +       msa_misc = 2 * val[0] + 32 * val[1] +
 799 +                  ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0);
 800 +
 801 +       return msa_misc;
 802 +}
 803 +
 804 +int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp)
 805 +{
 806 +       struct video_info *video = &mhdp->video_info;
 807 +       struct drm_display_mode *mode = &mhdp->mode;
 808 +       u64 symbol;
 809 +       u32 val, link_rate, rem;
 810 +       u8 bit_per_pix, tu_size_reg = TU_SIZE;
 811 +       int ret;
 812 +
 813 +       bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ?
 814 +                     (video->color_depth * 2) : (video->color_depth * 3);
 815 +
 816 +       link_rate = mhdp->dp.link.rate / 1000;
 817 +
 818 +       ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE);
 819 +       if (ret)
 820 +               goto err_config_video;
 821 +
 822 +       ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0);
 823 +       if (ret)
 824 +               goto err_config_video;
 825 +
 826 +       /*
 827 +        * get a best tu_size and valid symbol:
 828 +        * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32
 829 +        * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes)
 830 +        * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set
 831 +        *    TU += 2 and repeat 2nd step.
 832 +        */
 833 +       do {
 834 +               tu_size_reg += 2;
 835 +               symbol = tu_size_reg * mode->clock * bit_per_pix;
 836 +               do_div(symbol, mhdp->dp.link.num_lanes * link_rate * 8);
 837 +               rem = do_div(symbol, 1000);
 838 +               if (tu_size_reg > 64) {
 839 +                       ret = -EINVAL;
 840 +                       DRM_DEV_ERROR(mhdp->dev,
 841 +                                     "tu error, clk:%d, lanes:%d, rate:%d\n",
 842 +                                     mode->clock, mhdp->dp.link.num_lanes,
 843 +                                     link_rate);
 844 +                       goto err_config_video;
 845 +               }
 846 +       } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
 847 +                (rem > 850) || (rem < 100));
 848 +
 849 +       val = symbol + (tu_size_reg << 8);
 850 +       val |= TU_CNT_RST_EN;
 851 +       ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val);
 852 +       if (ret)
 853 +               goto err_config_video;
 854 +
 855 +       /* set the FIFO Buffer size */
 856 +       val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
 857 +       val /= (mhdp->dp.link.num_lanes * link_rate);
 858 +       val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
 859 +       val += 2;
 860 +       ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val);
 861 +
 862 +       switch (video->color_depth) {
 863 +       case 6:
 864 +               val = BCS_6;
 865 +               break;
 866 +       case 8:
 867 +               val = BCS_8;
 868 +               break;
 869 +       case 10:
 870 +               val = BCS_10;
 871 +               break;
 872 +       case 12:
 873 +               val = BCS_12;
 874 +               break;
 875 +       case 16:
 876 +               val = BCS_16;
 877 +               break;
 878 +       };
 879 +
 880 +       val += video->color_fmt << 8;
 881 +       ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val);
 882 +       if (ret)
 883 +               goto err_config_video;
 884 +
 885 +       val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0;
 886 +       val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0;
 887 +       ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val);
 888 +       if (ret)
 889 +               goto err_config_video;
 890 +
 891 +       val = (mode->hsync_start - mode->hdisplay) << 16;
 892 +       val |= mode->htotal - mode->hsync_end;
 893 +       ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val);
 894 +       if (ret)
 895 +               goto err_config_video;
 896 +
 897 +       val = mode->hdisplay * bit_per_pix / 8;
 898 +       ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val);
 899 +       if (ret)
 900 +               goto err_config_video;
 901 +
 902 +       val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16);
 903 +       ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val);
 904 +       if (ret)
 905 +               goto err_config_video;
 906 +
 907 +       val = mode->hsync_end - mode->hsync_start;
 908 +       val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15);
 909 +       ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val);
 910 +       if (ret)
 911 +               goto err_config_video;
 912 +
 913 +       val = mode->vtotal;
 914 +       val |= (mode->vtotal - mode->vsync_start) << 16;
 915 +       ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val);
 916 +       if (ret)
 917 +               goto err_config_video;
 918 +
 919 +       val = mode->vsync_end - mode->vsync_start;
 920 +       val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15);
 921 +       ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val);
 922 +       if (ret)
 923 +               goto err_config_video;
 924 +
 925 +       val = cdns_mhdp_get_msa_misc(video, mode);
 926 +       ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val);
 927 +       if (ret)
 928 +               goto err_config_video;
 929 +
 930 +       ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1);
 931 +       if (ret)
 932 +               goto err_config_video;
 933 +
 934 +       val = mode->hsync_end - mode->hsync_start;
 935 +       val |= mode->hdisplay << 16;
 936 +       ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val);
 937 +       if (ret)
 938 +               goto err_config_video;
 939 +
 940 +       val = mode->vdisplay;
 941 +       val |= (mode->vtotal - mode->vsync_start) << 16;
 942 +       ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val);
 943 +       if (ret)
 944 +               goto err_config_video;
 945 +
 946 +       val = mode->vtotal;
 947 +       ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val);
 948 +       if (ret)
 949 +               goto err_config_video;
 950 +
 951 +       ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0);
 952 +
 953 +err_config_video:
 954 +       if (ret)
 955 +               DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret);
 956 +       return ret;
 957 +}
 958 +EXPORT_SYMBOL(cdns_mhdp_config_video);
 959 +
 960 +int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp,
 961 +                        struct audio_info *audio)
 962 +{
 963 +       int ret;
 964 +
 965 +       ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, 0);
 966 +       if (ret) {
 967 +               DRM_DEV_ERROR(mhdp->dev, "audio stop failed: %d\n", ret);
 968 +               return ret;
 969 +       }
 970 +
 971 +       writel(0, mhdp->regs + SPDIF_CTRL_ADDR);
 972 +
 973 +       /* clearn the audio config and reset */
 974 +       writel(0, mhdp->regs + AUDIO_SRC_CNTL);
 975 +       writel(0, mhdp->regs + AUDIO_SRC_CNFG);
 976 +       writel(AUDIO_SW_RST, mhdp->regs + AUDIO_SRC_CNTL);
 977 +       writel(0, mhdp->regs + AUDIO_SRC_CNTL);
 978 +
 979 +       /* reset smpl2pckt component  */
 980 +       writel(0, mhdp->regs + SMPL2PKT_CNTL);
 981 +       writel(AUDIO_SW_RST, mhdp->regs + SMPL2PKT_CNTL);
 982 +       writel(0, mhdp->regs + SMPL2PKT_CNTL);
 983 +
 984 +       /* reset FIFO */
 985 +       writel(AUDIO_SW_RST, mhdp->regs + FIFO_CNTL);
 986 +       writel(0, mhdp->regs + FIFO_CNTL);
 987 +
 988 +       if (audio->format == AFMT_SPDIF)
 989 +               clk_disable_unprepare(mhdp->spdif_clk);
 990 +
 991 +       return 0;
 992 +}
 993 +EXPORT_SYMBOL(cdns_mhdp_audio_stop);
 994 +
 995 +int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable)
 996 +{
 997 +       int ret;
 998 +
 999 +       ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 4, 1, enable);
1000 +       if (ret)
1001 +               DRM_DEV_ERROR(mhdp->dev, "audio mute failed: %d\n", ret);
1002 +
1003 +       return ret;
1004 +}
1005 +EXPORT_SYMBOL(cdns_mhdp_audio_mute);
1006 +
1007 +static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp,
1008 +                                      struct audio_info *audio)
1009 +{
1010 +       int sub_pckt_num = 1, i2s_port_en_val = 0xf, i;
1011 +       u32 val;
1012 +
1013 +       if (audio->channels == 2) {
1014 +               if (mhdp->dp.link.num_lanes == 1)
1015 +                       sub_pckt_num = 2;
1016 +               else
1017 +                       sub_pckt_num = 4;
1018 +
1019 +               i2s_port_en_val = 1;
1020 +       } else if (audio->channels == 4) {
1021 +               i2s_port_en_val = 3;
1022 +       }
1023 +
1024 +       writel(0x0, mhdp->regs + SPDIF_CTRL_ADDR);
1025 +
1026 +       writel(SYNC_WR_TO_CH_ZERO, mhdp->regs + FIFO_CNTL);
1027 +
1028 +       val = MAX_NUM_CH(audio->channels);
1029 +       val |= NUM_OF_I2S_PORTS(audio->channels);
1030 +       val |= AUDIO_TYPE_LPCM;
1031 +       val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
1032 +       writel(val, mhdp->regs + SMPL2PKT_CNFG);
1033 +
1034 +       if (audio->sample_width == 16)
1035 +               val = 0;
1036 +       else if (audio->sample_width == 24)
1037 +               val = 1 << 9;
1038 +       else
1039 +               val = 2 << 9;
1040 +
1041 +       val |= AUDIO_CH_NUM(audio->channels);
1042 +       val |= I2S_DEC_PORT_EN(i2s_port_en_val);
1043 +       val |= TRANS_SMPL_WIDTH_32;
1044 +       writel(val, mhdp->regs + AUDIO_SRC_CNFG);
1045 +
1046 +       for (i = 0; i < (audio->channels + 1) / 2; i++) {
1047 +               if (audio->sample_width == 16)
1048 +                       val = (0x02 << 8) | (0x02 << 20);
1049 +               else if (audio->sample_width == 24)
1050 +                       val = (0x0b << 8) | (0x0b << 20);
1051 +
1052 +               val |= ((2 * i) << 4) | ((2 * i + 1) << 16);
1053 +               writel(val, mhdp->regs + STTS_BIT_CH(i));
1054 +       }
1055 +
1056 +       switch (audio->sample_rate) {
1057 +       case 32000:
1058 +               val = SAMPLING_FREQ(3) |
1059 +                     ORIGINAL_SAMP_FREQ(0xc);
1060 +               break;
1061 +       case 44100:
1062 +               val = SAMPLING_FREQ(0) |
1063 +                     ORIGINAL_SAMP_FREQ(0xf);
1064 +               break;
1065 +       case 48000:
1066 +               val = SAMPLING_FREQ(2) |
1067 +                     ORIGINAL_SAMP_FREQ(0xd);
1068 +               break;
1069 +       case 88200:
1070 +               val = SAMPLING_FREQ(8) |
1071 +                     ORIGINAL_SAMP_FREQ(0x7);
1072 +               break;
1073 +       case 96000:
1074 +               val = SAMPLING_FREQ(0xa) |
1075 +                     ORIGINAL_SAMP_FREQ(5);
1076 +               break;
1077 +       case 176400:
1078 +               val = SAMPLING_FREQ(0xc) |
1079 +                     ORIGINAL_SAMP_FREQ(3);
1080 +               break;
1081 +       case 192000:
1082 +               val = SAMPLING_FREQ(0xe) |
1083 +                     ORIGINAL_SAMP_FREQ(1);
1084 +               break;
1085 +       }
1086 +       val |= 4;
1087 +       writel(val, mhdp->regs + COM_CH_STTS_BITS);
1088 +
1089 +       writel(SMPL2PKT_EN, mhdp->regs + SMPL2PKT_CNTL);
1090 +       writel(I2S_DEC_START, mhdp->regs + AUDIO_SRC_CNTL);
1091 +}
1092 +
1093 +static void cdns_mhdp_audio_config_spdif(struct cdns_mhdp_device *mhdp)
1094 +{
1095 +       u32 val;
1096 +
1097 +       writel(SYNC_WR_TO_CH_ZERO, mhdp->regs + FIFO_CNTL);
1098 +
1099 +       val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4);
1100 +       writel(val, mhdp->regs + SMPL2PKT_CNFG);
1101 +       writel(SMPL2PKT_EN, mhdp->regs + SMPL2PKT_CNTL);
1102 +
1103 +       val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
1104 +       writel(val, mhdp->regs + SPDIF_CTRL_ADDR);
1105 +
1106 +       clk_prepare_enable(mhdp->spdif_clk);
1107 +       clk_set_rate(mhdp->spdif_clk, CDNS_DP_SPDIF_CLK);
1108 +}
1109 +
1110 +int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp,
1111 +                          struct audio_info *audio)
1112 +{
1113 +       int ret;
1114 +
1115 +       /* reset the spdif clk before config */
1116 +       if (audio->format == AFMT_SPDIF) {
1117 +               reset_control_assert(mhdp->spdif_rst);
1118 +               reset_control_deassert(mhdp->spdif_rst);
1119 +       }
1120 +
1121 +       ret = cdns_mhdp_reg_write(mhdp, CM_LANE_CTRL, LANE_REF_CYC);
1122 +       if (ret)
1123 +               goto err_audio_config;
1124 +
1125 +       ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 0);
1126 +       if (ret)
1127 +               goto err_audio_config;
1128 +
1129 +       if (audio->format == AFMT_I2S)
1130 +               cdns_mhdp_audio_config_i2s(mhdp, audio);
1131 +       else if (audio->format == AFMT_SPDIF)
1132 +               cdns_mhdp_audio_config_spdif(mhdp);
1133 +
1134 +       ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN);
1135 +
1136 +err_audio_config:
1137 +       if (ret)
1138 +               DRM_DEV_ERROR(mhdp->dev, "audio config failed: %d\n", ret);
1139 +       return ret;
1140 +}
1141 +EXPORT_SYMBOL(cdns_mhdp_audio_config);
1142 +
1143 +int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp,
1144 +                       u8 nlanes, u16 udelay, u8 *lanes_data, u8 *dpcd)
1145 +{
1146 +       u8 payload[7];
1147 +       u8 hdr[5]; /* For DPCD read response header */
1148 +       u32 addr;
1149 +       u8 const nregs = 6; /* Registers 0x202-0x207 */
1150 +       int ret;
1151 +
1152 +       if (nlanes != 4 && nlanes != 2 && nlanes != 1) {
1153 +               DRM_DEV_ERROR(mhdp->dev, "invalid number of lanes: %d\n",
1154 +                             nlanes);
1155 +               ret = -EINVAL;
1156 +               goto err_adjust_lt;
1157 +       }
1158 +
1159 +       payload[0] = nlanes;
1160 +       put_unaligned_be16(udelay, payload + 1);
1161 +       memcpy(payload + 3, lanes_data, nlanes);
1162 +
1163 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
1164 +                                    DPTX_ADJUST_LT,
1165 +                                    sizeof(payload), payload);
1166 +       if (ret)
1167 +               goto err_adjust_lt;
1168 +
1169 +       /* Yes, read the DPCD read command response */
1170 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
1171 +                                                DPTX_READ_DPCD,
1172 +                                                sizeof(hdr) + nregs);
1173 +       if (ret)
1174 +               goto err_adjust_lt;
1175 +
1176 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, hdr, sizeof(hdr));
1177 +       if (ret)
1178 +               goto err_adjust_lt;
1179 +
1180 +       addr = get_unaligned_be24(hdr + 2);
1181 +       if (addr != DP_LANE0_1_STATUS)
1182 +               goto err_adjust_lt;
1183 +
1184 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, dpcd, nregs);
1185 +
1186 +err_adjust_lt:
1187 +       if (ret)
1188 +               DRM_DEV_ERROR(mhdp->dev, "Failed to adjust Link Training.\n");
1189 +
1190 +       return ret;
1191 +}
1192 +EXPORT_SYMBOL(cdns_mhdp_adjust_lt);
1193 +
1194 +int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val)
1195 +{
1196 +       return cdns_mhdp_reg_write(mhdp, ADDR_PHY_AFE + (addr << 2), val);
1197 +}
1198 +EXPORT_SYMBOL(cdns_phy_reg_write);
1199 +
1200 +u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr)
1201 +{
1202 +       return cdns_mhdp_reg_read(mhdp, ADDR_PHY_AFE + (addr << 2));
1203 +}
1204 +EXPORT_SYMBOL(cdns_phy_reg_read);
1205 +
1206 +int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp)
1207 +{
1208 +       u8 status;
1209 +       int ret;
1210 +
1211 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE,
1212 +                                 0, NULL);
1213 +       if (ret)
1214 +               goto err_get_hpd;
1215 +
1216 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL,
1217 +                                                       GENERAL_GET_HPD_STATE, sizeof(status));
1218 +       if (ret)
1219 +               goto err_get_hpd;
1220 +
1221 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status));
1222 +       if (ret)
1223 +               goto err_get_hpd;
1224 +
1225 +       return status;
1226 +
1227 +err_get_hpd:
1228 +       DRM_ERROR("read hpd  failed: %d\n", ret);
1229 +       return ret;
1230 +}
1231 +EXPORT_SYMBOL(cdns_mhdp_read_hpd);
1232 +
1233 +bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp)
1234 +{
1235 +       u32  alive, newalive;
1236 +       u8 retries_left = 10;
1237 +
1238 +       alive = readl(mhdp->regs + KEEP_ALIVE);
1239 +
1240 +       while (retries_left--) {
1241 +               udelay(2);
1242 +
1243 +               newalive = readl(mhdp->regs + KEEP_ALIVE);
1244 +               if (alive == newalive)
1245 +                       continue;
1246 +               return true;
1247 +       }
1248 +       return false;
1249 +}
1250 +EXPORT_SYMBOL(cdns_mhdp_check_alive);
1251 --- /dev/null
1252 +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c
1253 @@ -0,0 +1,296 @@
1254 +/*
1255 + * Copyright (C) 2019 NXP Semiconductor, Inc.
1256 + *
1257 + * This program is free software; you can redistribute it and/or modify
1258 + * it under the terms of the GNU General Public License as published by
1259 + * the Free Software Foundation; either version 2 of the License, or
1260 + * (at your option) any later version.
1261 + */
1262 +
1263 +#include <drm/drmP.h>
1264 +#include <linux/io.h>
1265 +#include <drm/bridge/cdns-mhdp-common.h>
1266 +
1267 +int cdns_hdmi_get_edid_block(void *data, u8 *edid,
1268 +                         u32 block, size_t length)
1269 +{
1270 +       struct cdns_mhdp_device *mhdp = data;
1271 +       u8 msg[2], reg[5], i;
1272 +       int ret;
1273 +
1274 +       for (i = 0; i < 4; i++) {
1275 +               msg[0] = block / 2;
1276 +               msg[1] = block % 2;
1277 +
1278 +               ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID,
1279 +                                         sizeof(msg), msg);
1280 +               if (ret)
1281 +                       continue;
1282 +
1283 +               ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX,
1284 +                                                     HDMI_TX_EDID, sizeof(reg) + length);
1285 +               if (ret)
1286 +                       continue;
1287 +
1288 +               ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
1289 +               if (ret)
1290 +                       continue;
1291 +
1292 +               ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length);
1293 +               if (ret)
1294 +                       continue;
1295 +
1296 +               if ((reg[3] << 8 | reg[4]) == length)
1297 +                       break;
1298 +       }
1299 +
1300 +       if (ret)
1301 +               DRM_ERROR("get block[%d] edid failed: %d\n", block, ret);
1302 +       return ret;
1303 +}
1304 +
1305 +int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data)
1306 +{
1307 +       u8 msg[4], reg[6];
1308 +       int ret;
1309 +
1310 +       msg[0] = 0x54;
1311 +       msg[1] = addr;
1312 +       msg[2] = 0;
1313 +       msg[3] = 1;
1314 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ,
1315 +                                 sizeof(msg), msg);
1316 +       if (ret)
1317 +               goto err_scdc_read;
1318 +
1319 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX,
1320 +                                             HDMI_TX_READ, sizeof(reg));
1321 +       if (ret)
1322 +               goto err_scdc_read;
1323 +
1324 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
1325 +       if (ret)
1326 +               goto err_scdc_read;
1327 +
1328 +       *data = reg[5];
1329 +
1330 +err_scdc_read:
1331 +       if (ret)
1332 +               DRM_ERROR("scdc read failed: %d\n", ret);
1333 +       return ret;
1334 +}
1335 +
1336 +int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value)
1337 +{
1338 +       u8 msg[5], reg[5];
1339 +       int ret;
1340 +
1341 +       msg[0] = 0x54;
1342 +       msg[1] = addr;
1343 +       msg[2] = 0;
1344 +       msg[3] = 1;
1345 +       msg[4] = value;
1346 +       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE,
1347 +                                 sizeof(msg), msg);
1348 +       if (ret)
1349 +               goto err_scdc_write;
1350 +
1351 +       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX,
1352 +                                             HDMI_TX_WRITE, sizeof(reg));
1353 +       if (ret)
1354 +               goto err_scdc_write;
1355 +
1356 +       ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
1357 +       if (ret)
1358 +               goto err_scdc_write;
1359 +
1360 +       if (reg[0] != 0)
1361 +               ret = -EINVAL;
1362 +
1363 +err_scdc_write:
1364 +       if (ret)
1365 +               DRM_ERROR("scdc write failed: %d\n", ret);
1366 +       return ret;
1367 +}
1368 +
1369 +int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp,
1370 +                                int protocol,
1371 +                                u32 char_rate)
1372 +{
1373 +       u32 reg0;
1374 +       u32 reg1;
1375 +       u32 val;
1376 +       int ret;
1377 +
1378 +       /* Set PHY to HDMI data */
1379 +       ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1));
1380 +       if (ret < 0)
1381 +               return ret;
1382 +
1383 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD,
1384 +                                       F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0));
1385 +       if (ret < 0)
1386 +               return ret;
1387 +
1388 +       /* open CARS */
1389 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF);
1390 +       if (ret < 0)
1391 +               return ret;
1392 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF);
1393 +       if (ret < 0)
1394 +               return ret;
1395 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF);
1396 +       if (ret < 0)
1397 +               return ret;
1398 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF);
1399 +       if (ret < 0)
1400 +               return ret;
1401 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF);
1402 +       if (ret < 0)
1403 +               return ret;
1404 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF);
1405 +       if (ret < 0)
1406 +               return ret;
1407 +       ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3);
1408 +       if (ret < 0)
1409 +               return ret;
1410 +
1411 +       reg0 = reg1 = 0x7c1f;
1412 +       if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) {
1413 +               reg0 = 0;
1414 +               reg1 = 0xFFFFF;
1415 +       }
1416 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0);
1417 +       if (ret < 0)
1418 +               return ret;
1419 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1);
1420 +       if (ret < 0)
1421 +               return ret;
1422 +
1423 +       /* set hdmi mode and preemble mode data enable */
1424 +       val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) |  F_DATA_EN(1) |
1425 +                       F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF);
1426 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
1427 +
1428 +       return ret;
1429 +}
1430 +
1431 +int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp,
1432 +                                             struct drm_display_mode *mode,
1433 +                                                 struct video_info *video_info)
1434 +{
1435 +       int ret;
1436 +       u32 val;
1437 +       u32 vsync_lines = mode->vsync_end - mode->vsync_start;
1438 +       u32 eof_lines = mode->vsync_start - mode->vdisplay;
1439 +       u32 sof_lines = mode->vtotal - mode->vsync_end;
1440 +       u32 hblank = mode->htotal - mode->hdisplay;
1441 +       u32 hactive = mode->hdisplay;
1442 +       u32 vblank = mode->vtotal - mode->vdisplay;
1443 +       u32 vactive = mode->vdisplay;
1444 +       u32 hfront = mode->hsync_start - mode->hdisplay;
1445 +       u32 hback = mode->htotal - mode->hsync_end;
1446 +       u32 vfront = eof_lines;
1447 +       u32 hsync = hblank - hfront - hback;
1448 +       u32 vsync = vsync_lines;
1449 +       u32 vback = sof_lines;
1450 +       u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) +
1451 +                                               ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2);
1452 +
1453 +       ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive << 16) + hblank);
1454 +       if (ret < 0)
1455 +               return ret;
1456 +
1457 +       ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive << 16) + vblank);
1458 +       if (ret < 0)
1459 +               return ret;
1460 +
1461 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront);
1462 +       if (ret < 0)
1463 +               return ret;
1464 +
1465 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync);
1466 +       if (ret < 0)
1467 +               return ret;
1468 +
1469 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback);
1470 +       if (ret < 0)
1471 +               return ret;
1472 +
1473 +       ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity);
1474 +       if (ret < 0)
1475 +               return ret;
1476 +
1477 +       /* Reset Data Enable */
1478 +       val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER);
1479 +       val &= ~F_DATA_EN(1);
1480 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
1481 +       if (ret < 0)
1482 +               return ret;
1483 +
1484 +       /* Set bpc */
1485 +       val &= ~F_VIF_DATA_WIDTH(3);
1486 +       switch (video_info->color_depth) {
1487 +       case 10:
1488 +               val |= F_VIF_DATA_WIDTH(1);
1489 +               break;
1490 +       case 12:
1491 +               val |= F_VIF_DATA_WIDTH(2);
1492 +               break;
1493 +       case 16:
1494 +               val |= F_VIF_DATA_WIDTH(3);
1495 +               break;
1496 +       case 8:
1497 +       default:
1498 +               val |= F_VIF_DATA_WIDTH(0);
1499 +               break;
1500 +       }
1501 +
1502 +       /* select color encoding */
1503 +       val &= ~F_HDMI_ENCODING(3);
1504 +       switch (video_info->color_fmt) {
1505 +       case YCBCR_4_4_4:
1506 +               val |= F_HDMI_ENCODING(2);
1507 +               break;
1508 +       case YCBCR_4_2_2:
1509 +               val |= F_HDMI_ENCODING(1);
1510 +               break;
1511 +       case YCBCR_4_2_0:
1512 +               val |= F_HDMI_ENCODING(3);
1513 +               break;
1514 +       case PXL_RGB:
1515 +       default:
1516 +               val |= F_HDMI_ENCODING(0);
1517 +               break;
1518 +       }
1519 +
1520 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
1521 +       if (ret < 0)
1522 +               return ret;
1523 +
1524 +       /* set data enable */
1525 +       val |= F_DATA_EN(1);
1526 +       ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
1527 +
1528 +       return ret;
1529 +}
1530 +
1531 +int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp)
1532 +{
1533 +       u32 val;
1534 +
1535 +       val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER);
1536 +       val &= ~F_GCP_EN(1);
1537 +
1538 +       return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
1539 +}
1540 +
1541 +int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp)
1542 +{
1543 +       u32 val;
1544 +
1545 +       val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER);
1546 +       val |= F_GCP_EN(1);
1547 +
1548 +       return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
1549 +}
1550 --- /dev/null
1551 +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h
1552 @@ -0,0 +1,209 @@
1553 +/* SPDX-License-Identifier: GPL-2.0 */
1554 +/*
1555 + * Cadence MHDP DP MST bridge driver.
1556 + *
1557 + * Copyright: 2018 Cadence Design Systems, Inc.
1558 + *
1559 + * Author: Quentin Schulz <quentin.schulz@free-electrons.com>
1560 + */
1561 +
1562 +
1563 +#ifndef CDNS_MHDP_H
1564 +#define CDNS_MHDP_H
1565 +
1566 +#include <drm/drm_dp_mst_helper.h>
1567 +
1568 +#define CDNS_APB_CFG                           0x00000
1569 +#define CDNS_APB_CTRL                          (CDNS_APB_CFG + 0x00)
1570 +#define CDNS_MAILBOX_FULL                      (CDNS_APB_CFG + 0x08)
1571 +#define CDNS_MAILBOX_EMPTY                     (CDNS_APB_CFG + 0x0c)
1572 +#define CDNS_MAILBOX_TX_DATA                   (CDNS_APB_CFG + 0x10)
1573 +#define CDNS_MAILBOX_RX_DATA                   (CDNS_APB_CFG + 0x14)
1574 +#define CDNS_KEEP_ALIVE                                (CDNS_APB_CFG + 0x18)
1575 +#define CDNS_KEEP_ALIVE_MASK                   GENMASK(7, 0)
1576 +
1577 +#define CDNS_MB_INT_MASK                       (CDNS_APB_CFG + 0x34)
1578 +
1579 +#define CDNS_SW_CLK_L                          (CDNS_APB_CFG + 0x3c)
1580 +#define CDNS_SW_CLK_H                          (CDNS_APB_CFG + 0x40)
1581 +#define CDNS_SW_EVENT0                         (CDNS_APB_CFG + 0x44)
1582 +#define CDNS_DPTX_HPD                          BIT(0)
1583 +
1584 +#define CDNS_SW_EVENT1                         (CDNS_APB_CFG + 0x48)
1585 +#define CDNS_SW_EVENT2                         (CDNS_APB_CFG + 0x4c)
1586 +#define CDNS_SW_EVENT3                         (CDNS_APB_CFG + 0x50)
1587 +
1588 +#define CDNS_APB_INT_MASK                      (CDNS_APB_CFG + 0x6C)
1589 +#define CDNS_APB_INT_MASK_MAILBOX_INT          BIT(0)
1590 +#define CDNS_APB_INT_MASK_SW_EVENT_INT         BIT(1)
1591 +
1592 +#define CDNS_DPTX_CAR                          (CDNS_APB_CFG + 0x904)
1593 +#define CDNS_VIF_CLK_EN                                BIT(0)
1594 +#define CDNS_VIF_CLK_RSTN                      BIT(1)
1595 +
1596 +#define CDNS_SOURCE_VIDEO_IF(s)                        (0x00b00 + (s * 0x20))
1597 +#define CDNS_BND_HSYNC2VSYNC(s)                        (CDNS_SOURCE_VIDEO_IF(s) + \
1598 +                                                0x00)
1599 +#define CDNS_IP_DTCT_WIN                       GENMASK(11, 0)
1600 +#define CDNS_IP_DET_INTERLACE_FORMAT           BIT(12)
1601 +#define CDNS_IP_BYPASS_V_INTERFACE             BIT(13)
1602 +
1603 +#define CDNS_HSYNC2VSYNC_POL_CTRL(s)           (CDNS_SOURCE_VIDEO_IF(s) + \
1604 +                                                0x10)
1605 +#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW          BIT(1)
1606 +#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW          BIT(2)
1607 +
1608 +#define CDNS_DPTX_PHY_CONFIG                   0x02000
1609 +#define CDNS_PHY_TRAINING_EN                   BIT(0)
1610 +#define CDNS_PHY_TRAINING_TYPE(x)              (((x) & GENMASK(3, 0)) << 1)
1611 +#define CDNS_PHY_SCRAMBLER_BYPASS              BIT(5)
1612 +#define CDNS_PHY_ENCODER_BYPASS                        BIT(6)
1613 +#define CDNS_PHY_SKEW_BYPASS                   BIT(7)
1614 +#define CDNS_PHY_TRAINING_AUTO                 BIT(8)
1615 +#define CDNS_PHY_LANE0_SKEW(x)                 (((x) & GENMASK(2, 0)) << 9)
1616 +#define CDNS_PHY_LANE1_SKEW(x)                 (((x) & GENMASK(2, 0)) << 12)
1617 +#define CDNS_PHY_LANE2_SKEW(x)                 (((x) & GENMASK(2, 0)) << 15)
1618 +#define CDNS_PHY_LANE3_SKEW(x)                 (((x) & GENMASK(2, 0)) << 18)
1619 +#define CDNS_PHY_COMMON_CONFIG                 (CDNS_PHY_LANE1_SKEW(1) | \
1620 +                                               CDNS_PHY_LANE2_SKEW(2) |  \
1621 +                                               CDNS_PHY_LANE3_SKEW(3))
1622 +#define CDNS_PHY_10BIT_EN                      BIT(21)
1623 +
1624 +#define CDNS_DPTX_FRAMER                       0x02200
1625 +#define CDNS_DP_FRAMER_GLOBAL_CONFIG           (CDNS_DPTX_FRAMER + 0x00)
1626 +#define CDNS_DP_NUM_LANES(x)                   (x - 1)
1627 +#define CDNS_DP_MST_EN                         BIT(2)
1628 +#define CDNS_DP_FRAMER_EN                      BIT(3)
1629 +#define CDNS_DP_RATE_GOVERNOR_EN               BIT(4)
1630 +#define CDNS_DP_NO_VIDEO_MODE                  BIT(5)
1631 +#define CDNS_DP_DISABLE_PHY_RST                        BIT(6)
1632 +#define CDNS_DP_WR_FAILING_EDGE_VSYNC          BIT(7)
1633 +
1634 +#define CDNS_DP_SW_RESET                       (CDNS_DPTX_FRAMER + 0x04)
1635 +#define CDNS_DP_FRAMER_TU                      (CDNS_DPTX_FRAMER + 0x08)
1636 +#define CDNS_DP_FRAMER_TU_SIZE(x)              (((x) & GENMASK(6, 0)) << 8)
1637 +#define CDNS_DP_FRAMER_TU_VS(x)                        ((x) & GENMASK(5, 0))
1638 +#define CDNS_DP_FRAMER_TU_CNT_RST_EN           BIT(15)
1639 +
1640 +#define CDNS_DPTX_STREAM(s)                    (0x03000 + s * 0x80)
1641 +#define CDNS_DP_MSA_HORIZONTAL_0(s)            (CDNS_DPTX_STREAM(s) + 0x00)
1642 +#define CDNS_DP_MSAH0_H_TOTAL(x)               (x)
1643 +#define CDNS_DP_MSAH0_HSYNC_START(x)           ((x) << 16)
1644 +
1645 +#define CDNS_DP_MSA_HORIZONTAL_1(s)            (CDNS_DPTX_STREAM(s) + 0x04)
1646 +#define CDNS_DP_MSAH1_HSYNC_WIDTH(x)           (x)
1647 +#define CDNS_DP_MSAH1_HSYNC_POL_LOW            BIT(15)
1648 +#define CDNS_DP_MSAH1_HDISP_WIDTH(x)           ((x) << 16)
1649 +
1650 +#define CDNS_DP_MSA_VERTICAL_0(s)              (CDNS_DPTX_STREAM(s) + 0x08)
1651 +#define CDNS_DP_MSAV0_V_TOTAL(x)               (x)
1652 +#define CDNS_DP_MSAV0_VSYNC_START(x)           ((x) << 16)
1653 +
1654 +#define CDNS_DP_MSA_VERTICAL_1(s)              (CDNS_DPTX_STREAM(s) + 0x0c)
1655 +#define CDNS_DP_MSAV1_VSYNC_WIDTH(x)           (x)
1656 +#define CDNS_DP_MSAV1_VSYNC_POL_LOW            BIT(15)
1657 +#define CDNS_DP_MSAV1_VDISP_WIDTH(x)           ((x) << 16)
1658 +
1659 +#define CDNS_DP_MSA_MISC(s)                    (CDNS_DPTX_STREAM(s) + 0x10)
1660 +#define CDNS_DP_STREAM_CONFIGs(s)              (CDNS_DPTX_STREAM(s) + 0x14)
1661 +#define CDNS_DP_STREAM_CONFIG_2(s)             (CDNS_DPTX_STREAM(s) + 0x2c)
1662 +#define CDNS_DP_SC2_TU_VS_DIFF(x)              ((x) << 8)
1663 +
1664 +#define CDNS_DP_HORIZONTAL(s)                  (CDNS_DPTX_STREAM(s) + 0x30)
1665 +#define CDNS_DP_H_HSYNC_WIDTH(x)               (x)
1666 +#define CDNS_DP_H_H_TOTAL(x)                   ((x) << 16)
1667 +
1668 +#define CDNS_DP_VERTICAL_0(s)                  (CDNS_DPTX_STREAM(s) + 0x34)
1669 +#define CDNS_DP_V0_VHEIGHT(x)                  (x)
1670 +#define CDNS_DP_V0_VSTART(x)                   ((x) << 16)
1671 +
1672 +#define CDNS_DP_VERTICAL_1(s)                  (CDNS_DPTX_STREAM(s) + 0x38)
1673 +#define CDNS_DP_V1_VTOTAL(x)                   (x)
1674 +#define CDNS_DP_V1_VTOTAL_EVEN                 BIT(16)
1675 +
1676 +#define CDNS_DP_FRAMER_PXL_REPR(s)             (CDNS_DPTX_STREAM(s) + 0x4c)
1677 +#define CDNS_DP_FRAMER_6_BPC                   BIT(0)
1678 +#define CDNS_DP_FRAMER_8_BPC                   BIT(1)
1679 +#define CDNS_DP_FRAMER_10_BPC                  BIT(2)
1680 +#define CDNS_DP_FRAMER_12_BPC                  BIT(3)
1681 +#define CDNS_DP_FRAMER_16_BPC                  BIT(4)
1682 +#define CDNS_DP_FRAMER_PXL_FORMAT              0x8
1683 +#define CDNS_DP_FRAMER_RGB                     BIT(0)
1684 +#define CDNS_DP_FRAMER_YCBCR444                        BIT(1)
1685 +#define CDNS_DP_FRAMER_YCBCR422                        BIT(2)
1686 +#define CDNS_DP_FRAMER_YCBCR420                        BIT(3)
1687 +#define CDNS_DP_FRAMER_Y_ONLY                  BIT(4)
1688 +
1689 +#define CDNS_DP_FRAMER_SP(s)                   (CDNS_DPTX_STREAM(s) + 0x10)
1690 +#define CDNS_DP_FRAMER_VSYNC_POL_LOW           BIT(0)
1691 +#define CDNS_DP_FRAMER_HSYNC_POL_LOW           BIT(1)
1692 +#define CDNS_DP_FRAMER_INTERLACE               BIT(2)
1693 +
1694 +#define CDNS_DP_LINE_THRESH(s)                 (CDNS_DPTX_STREAM(s) + 0x64)
1695 +#define CDNS_DP_ACTIVE_LINE_THRESH(x)          (x)
1696 +
1697 +#define CDNS_DP_VB_ID(s)                       (CDNS_DPTX_STREAM(s) + 0x68)
1698 +#define CDNS_DP_VB_ID_INTERLACED               BIT(2)
1699 +#define CDNS_DP_VB_ID_COMPRESSED               BIT(6)
1700 +
1701 +#define CDNS_DP_FRONT_BACK_PORCH(s)            (CDNS_DPTX_STREAM(s) + 0x78)
1702 +#define CDNS_DP_BACK_PORCH(x)                  (x)
1703 +#define CDNS_DP_FRONT_PORCH(x)                 ((x) << 16)
1704 +
1705 +#define CDNS_DP_BYTE_COUNT(s)                  (CDNS_DPTX_STREAM(s) + 0x7c)
1706 +#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT        16
1707 +
1708 +#define CDNS_DP_MST_STREAM_CONFIG(s)           (CDNS_DPTX_STREAM(s) + 0x14)
1709 +#define CDNS_DP_MST_STRM_CFG_STREAM_EN         BIT(0)
1710 +#define CDNS_DP_MST_STRM_CFG_NO_VIDEO          BIT(1)
1711 +
1712 +#define CDNS_DP_MST_SLOT_ALLOCATE(s)           (CDNS_DPTX_STREAM(s) + 0x44)
1713 +#define CDNS_DP_S_ALLOC_START_SLOT(x)          (x)
1714 +#define CDNS_DP_S_ALLOC_END_SLOT(x)            ((x) << 8)
1715 +
1716 +#define CDNS_DP_RATE_GOVERNING(s)              (CDNS_DPTX_STREAM(s) + 0x48)
1717 +#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x)          (x)
1718 +#define CDNS_DP_RG_TARG_AV_SLOTS_X(x)          (x << 4)
1719 +#define CDNS_DP_RG_ENABLE                      BIT(10)
1720 +
1721 +#define CDNS_DP_MTPH_CONTROL                   0x2264
1722 +#define CDNS_DP_MTPH_ECF_EN                    BIT(0)
1723 +#define CDNS_DP_MTPH_ACT_EN                    BIT(1)
1724 +#define CDNS_DP_MTPH_LVP_EN                    BIT(2)
1725 +
1726 +#define CDNS_DP_MTPH_STATUS                    0x226C
1727 +#define CDNS_DP_MTPH_ACT_STATUS                        BIT(0)
1728 +
1729 +
1730 +#define CDNS_DPTX_GLOBAL                       0x02300
1731 +#define CDNS_DP_LANE_EN                                (CDNS_DPTX_GLOBAL + 0x00)
1732 +#define CDNS_DP_LANE_EN_LANES(x)               GENMASK(x - 1, 0)
1733 +#define CDNS_DP_ENHNCD                         (CDNS_DPTX_GLOBAL + 0x04)
1734 +
1735 +
1736 +#define to_mhdp_connector(x) container_of(x, struct cdns_mhdp_connector, base)
1737 +#define to_mhdp_bridge(x) container_of(x, struct cdns_mhdp_bridge, base)
1738 +#define mgr_to_mhdp(x) container_of(x, struct cdns_mhdp_device, mst_mgr)
1739 +
1740 +#define CDNS_MHDP_MAX_STREAMS   4
1741 +
1742 +enum pixel_format {
1743 +       PIXEL_FORMAT_RGB = 1,
1744 +       PIXEL_FORMAT_YCBCR_444 = 2,
1745 +       PIXEL_FORMAT_YCBCR_422 = 4,
1746 +       PIXEL_FORMAT_YCBCR_420 = 8,
1747 +       PIXEL_FORMAT_Y_ONLY = 16,
1748 +};
1749 +
1750 +
1751 +int cdns_mhdp_mst_init(struct cdns_mhdp_device *mhdp);
1752 +void cdns_mhdp_mst_deinit(struct cdns_mhdp_device *mhdp);
1753 +bool cdns_mhdp_mst_probe(struct cdns_mhdp_device *mhdp);
1754 +enum pixel_format cdns_mhdp_get_pxlfmt(u32 color_formats);
1755 +u32 cdns_mhdp_get_bpp(u32 bpc, u32 color_formats);
1756 +void cdns_mhdp_configure_video(struct drm_bridge *bridge);
1757 +void cdns_mhdp_mst_enable(struct drm_bridge *bridge);
1758 +void cdns_mhdp_mst_disable(struct drm_bridge *bridge);
1759 +void cdns_mhdp_enable(struct drm_bridge *bridge);
1760 +
1761 +#endif
1762 --- a/drivers/gpu/drm/rockchip/Kconfig
1763 +++ b/drivers/gpu/drm/rockchip/Kconfig
1764 @@ -29,7 +29,9 @@ config ROCKCHIP_ANALOGIX_DP
1765
1766  config ROCKCHIP_CDN_DP
1767          bool "Rockchip cdn DP"
1768 -       depends on EXTCON=y || (EXTCON=m && DRM_ROCKCHIP=m)
1769 +       depends on DRM_ROCKCHIP
1770 +       select EXTCON
1771 +       select DRM_CDNS_MHDP
1772          help
1773           This selects support for Rockchip SoC specific extensions
1774           for the cdn DP driver. If you want to enable Dp on
1775 --- a/drivers/gpu/drm/rockchip/Makefile
1776 +++ b/drivers/gpu/drm/rockchip/Makefile
1777 @@ -8,7 +8,7 @@ rockchipdrm-y := rockchip_drm_drv.o rock
1778  rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
1779
1780  rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
1781 -rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
1782 +rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o
1783  rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
1784  rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
1785  rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
1786 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
1787 +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
1788 @@ -25,7 +25,7 @@
1789  #include "rockchip_drm_vop.h"
1790
1791  #define connector_to_dp(c) \
1792 -               container_of(c, struct cdn_dp_device, mhdp.connector)
1793 +               container_of(c, struct cdn_dp_device, mhdp.connector.base)
1794
1795  #define encoder_to_dp(c) \
1796                 container_of(c, struct cdn_dp_device, encoder)
1797 @@ -282,7 +282,7 @@ static int cdn_dp_connector_mode_valid(s
1798  {
1799         struct cdn_dp_device *dp = connector_to_dp(connector);
1800         struct drm_display_info *display_info =
1801 -               &dp->mhdp.connector.display_info;
1802 +               &dp->mhdp.connector.base.display_info;
1803         u32 requested, actual, rate, sink_max, source_max = 0;
1804         u8 lanes, bpc;
1805
1806 @@ -378,7 +378,7 @@ static int cdn_dp_get_sink_capability(st
1807         }
1808
1809         kfree(dp->edid);
1810 -       dp->edid = drm_do_get_edid(&dp->mhdp.connector,
1811 +       dp->edid = drm_do_get_edid(&dp->mhdp.connector.base,
1812                                    cdns_mhdp_get_edid_block, &dp->mhdp);
1813         return 0;
1814  }
1815 @@ -484,8 +484,8 @@ static int cdn_dp_disable(struct cdn_dp_
1816         cdns_mhdp_set_firmware_active(&dp->mhdp, false);
1817         cdn_dp_clk_disable(dp);
1818         dp->active = false;
1819 -       dp->mhdp.link.rate = 0;
1820 -       dp->mhdp.link.num_lanes = 0;
1821 +       dp->mhdp.dp.link.rate = 0;
1822 +       dp->mhdp.dp.link.num_lanes = 0;
1823         if (!dp->connected) {
1824                 kfree(dp->edid);
1825                 dp->edid = NULL;
1826 @@ -550,7 +550,7 @@ static void cdn_dp_encoder_mode_set(stru
1827  {
1828         struct cdn_dp_device *dp = encoder_to_dp(encoder);
1829         struct drm_display_info *display_info =
1830 -               &dp->mhdp.connector.display_info;
1831 +               &dp->mhdp.connector.base.display_info;
1832         struct video_info *video = &dp->mhdp.video_info;
1833
1834         switch (display_info->bpc) {
1835 @@ -578,7 +578,7 @@ static bool cdn_dp_check_link_status(str
1836         struct cdn_dp_port *port = cdn_dp_connected_port(dp);
1837         u8 sink_lanes = drm_dp_max_lane_count(dp->dpcd);
1838
1839 -       if (!port || !dp->mhdp.link.rate || !dp->mhdp.link.num_lanes)
1840 +       if (!port || !dp->mhdp.dp.link.rate || !dp->mhdp.dp.link.num_lanes)
1841                 return false;
1842
1843         if (cdns_mhdp_dpcd_read(&dp->mhdp, DP_LANE0_1_STATUS, link_status,
1844 @@ -807,7 +807,7 @@ static int cdn_dp_audio_hw_params(struct
1845
1846         ret = cdns_mhdp_audio_config(&dp->mhdp, &audio);
1847         if (!ret)
1848 -               dp->audio_info = audio;
1849 +               dp->mhdp.audio_info = audio;
1850
1851  out:
1852         mutex_unlock(&dp->lock);
1853 @@ -823,9 +823,9 @@ static void cdn_dp_audio_shutdown(struct
1854         if (!dp->active)
1855                 goto out;
1856
1857 -       ret = cdns_mhdp_audio_stop(&dp->mhdp, &dp->audio_info);
1858 +       ret = cdns_mhdp_audio_stop(&dp->mhdp, &dp->mhdp.audio_info);
1859         if (!ret)
1860 -               dp->audio_info.format = AFMT_UNUSED;
1861 +               dp->mhdp.audio_info.format = AFMT_UNUSED;
1862  out:
1863         mutex_unlock(&dp->lock);
1864  }
1865 @@ -854,8 +854,8 @@ static int cdn_dp_audio_get_eld(struct d
1866  {
1867         struct cdn_dp_device *dp = dev_get_drvdata(dev);
1868
1869 -       memcpy(buf, dp->mhdp.connector.eld,
1870 -              min(sizeof(dp->mhdp.connector.eld), len));
1871 +       memcpy(buf, dp->mhdp.connector.base.eld,
1872 +              min(sizeof(dp->mhdp.connector.base.eld), len));
1873
1874         return 0;
1875  }
1876 @@ -877,11 +877,11 @@ static int cdn_dp_audio_codec_init(struc
1877                 .max_i2s_channels = 8,
1878         };
1879
1880 -       dp->audio_pdev = platform_device_register_data(
1881 -                        dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1882 -                        &codec_data, sizeof(codec_data));
1883 +       dp->mhdp.audio_pdev = platform_device_register_data(
1884 +                             dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1885 +                             &codec_data, sizeof(codec_data));
1886
1887 -       return PTR_ERR_OR_ZERO(dp->audio_pdev);
1888 +       return PTR_ERR_OR_ZERO(dp->mhdp.audio_pdev);
1889  }
1890
1891  static int cdn_dp_request_firmware(struct cdn_dp_device *dp)
1892 @@ -927,7 +927,7 @@ static void cdn_dp_pd_event_work(struct
1893  {
1894         struct cdn_dp_device *dp = container_of(work, struct cdn_dp_device,
1895                                                 event_work);
1896 -       struct drm_connector *connector = &dp->mhdp.connector;
1897 +       struct drm_connector *connector = &dp->mhdp.connector.base;
1898         enum drm_connector_status old_status;
1899         struct device *dev = dp->mhdp.dev;
1900
1901 @@ -965,8 +965,8 @@ static void cdn_dp_pd_event_work(struct
1902
1903         /* Enabled and connected with a sink, re-train if requested */
1904         } else if (!cdn_dp_check_link_status(dp)) {
1905 -               unsigned int rate = dp->mhdp.link.rate;
1906 -               unsigned int lanes = dp->mhdp.link.num_lanes;
1907 +               unsigned int rate = dp->mhdp.dp.link.rate;
1908 +               unsigned int lanes = dp->mhdp.dp.link.num_lanes;
1909                 struct drm_display_mode *mode = &dp->mhdp.mode;
1910
1911                 DRM_DEV_INFO(dev, "Connected with sink. Re-train link\n");
1912 @@ -979,8 +979,8 @@ static void cdn_dp_pd_event_work(struct
1913
1914                 /* If training result is changed, update the video config */
1915                 if (mode->clock &&
1916 -                   (rate != dp->mhdp.link.rate ||
1917 -                    lanes != dp->mhdp.link.num_lanes)) {
1918 +                   (rate != dp->mhdp.dp.link.rate ||
1919 +                    lanes != dp->mhdp.dp.link.num_lanes)) {
1920                         ret = cdns_mhdp_config_video(&dp->mhdp);
1921                         if (ret) {
1922                                 dp->connected = false;
1923 @@ -1053,7 +1053,7 @@ static int cdn_dp_bind(struct device *de
1924
1925         drm_encoder_helper_add(encoder, &cdn_dp_encoder_helper_funcs);
1926
1927 -       connector = &dp->mhdp.connector;
1928 +       connector = &dp->mhdp.connector.base;
1929         connector->polled = DRM_CONNECTOR_POLL_HPD;
1930         connector->dpms = DRM_MODE_DPMS_OFF;
1931
1932 @@ -1104,7 +1104,7 @@ static void cdn_dp_unbind(struct device
1933  {
1934         struct cdn_dp_device *dp = dev_get_drvdata(dev);
1935         struct drm_encoder *encoder = &dp->encoder;
1936 -       struct drm_connector *connector = &dp->mhdp.connector;
1937 +       struct drm_connector *connector = &dp->mhdp.connector.base;
1938
1939         cancel_work_sync(&dp->event_work);
1940         cdn_dp_encoder_disable(encoder);
1941 @@ -1208,7 +1208,7 @@ static int cdn_dp_remove(struct platform
1942  {
1943         struct cdn_dp_device *dp = platform_get_drvdata(pdev);
1944
1945 -       platform_device_unregister(dp->audio_pdev);
1946 +       platform_device_unregister(dp->mhdp.audio_pdev);
1947         cdn_dp_suspend(dp->mhdp.dev);
1948         component_del(&pdev->dev, &cdn_dp_component_ops);
1949
1950 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
1951 +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
1952 @@ -7,12 +7,13 @@
1953  #ifndef _CDN_DP_CORE_H
1954  #define _CDN_DP_CORE_H
1955
1956 +#include <drm/bridge/cdns-mhdp-common.h>
1957 +#include <drm/drmP.h>
1958  #include <drm/drm_dp_helper.h>
1959  #include <drm/drm_panel.h>
1960  #include <drm/drm_probe_helper.h>
1961
1962  #include "rockchip_drm_drv.h"
1963 -#include "cdn-dp-reg.h"
1964
1965  #define MAX_PHY                2
1966
1967 @@ -37,7 +38,6 @@ struct cdn_dp_device {
1968         struct cdns_mhdp_device mhdp;
1969         struct drm_device *drm_dev;
1970         struct drm_encoder encoder;
1971 -       struct platform_device *audio_pdev;
1972         struct work_struct event_work;
1973         struct edid *edid;
1974
1975 @@ -56,7 +56,6 @@ struct cdn_dp_device {
1976         struct reset_control *dptx_rst;
1977         struct reset_control *apb_rst;
1978         struct reset_control *core_rst;
1979 -       struct audio_info audio_info;
1980         struct cdn_dp_port *port[MAX_PHY];
1981         u8 ports;
1982         u8 lanes;
1983 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
1984 +++ /dev/null
1985 @@ -1,968 +0,0 @@
1986 -// SPDX-License-Identifier: GPL-2.0-only
1987 -/*
1988 - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
1989 - * Author: Chris Zhong <zyw@rock-chips.com>
1990 - */
1991 -
1992 -#include <linux/clk.h>
1993 -#include <linux/device.h>
1994 -#include <linux/delay.h>
1995 -#include <linux/io.h>
1996 -#include <linux/iopoll.h>
1997 -#include <linux/reset.h>
1998 -
1999 -#include "cdn-dp-core.h"
2000 -#include "cdn-dp-reg.h"
2001 -
2002 -#define CDNS_DP_SPDIF_CLK              200000000
2003 -#define FW_ALIVE_TIMEOUT_US            1000000
2004 -#define MAILBOX_RETRY_US               1000
2005 -#define MAILBOX_TIMEOUT_US             5000000
2006 -#define LINK_TRAINING_RETRY_MS         20
2007 -#define LINK_TRAINING_TIMEOUT_MS       500
2008 -
2009 -void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk)
2010 -{
2011 -       writel(clk / 1000000, mhdp->regs + SW_CLK_H);
2012 -}
2013 -
2014 -void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp)
2015 -{
2016 -       u32 val;
2017 -
2018 -       val = DPTX_FRMR_DATA_CLK_RSTN_EN |
2019 -             DPTX_FRMR_DATA_CLK_EN |
2020 -             DPTX_PHY_DATA_RSTN_EN |
2021 -             DPTX_PHY_DATA_CLK_EN |
2022 -             DPTX_PHY_CHAR_RSTN_EN |
2023 -             DPTX_PHY_CHAR_CLK_EN |
2024 -             SOURCE_AUX_SYS_CLK_RSTN_EN |
2025 -             SOURCE_AUX_SYS_CLK_EN |
2026 -             DPTX_SYS_CLK_RSTN_EN |
2027 -             DPTX_SYS_CLK_EN |
2028 -             CFG_DPTX_VIF_CLK_RSTN_EN |
2029 -             CFG_DPTX_VIF_CLK_EN;
2030 -       writel(val, mhdp->regs + SOURCE_DPTX_CAR);
2031 -
2032 -       val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN;
2033 -       writel(val, mhdp->regs + SOURCE_PHY_CAR);
2034 -
2035 -       val = SOURCE_PKT_SYS_RSTN_EN |
2036 -             SOURCE_PKT_SYS_CLK_EN |
2037 -             SOURCE_PKT_DATA_RSTN_EN |
2038 -             SOURCE_PKT_DATA_CLK_EN;
2039 -       writel(val, mhdp->regs + SOURCE_PKT_CAR);
2040 -
2041 -       val = SPDIF_CDR_CLK_RSTN_EN |
2042 -             SPDIF_CDR_CLK_EN |
2043 -             SOURCE_AIF_SYS_RSTN_EN |
2044 -             SOURCE_AIF_SYS_CLK_EN |
2045 -             SOURCE_AIF_CLK_RSTN_EN |
2046 -             SOURCE_AIF_CLK_EN;
2047 -       writel(val, mhdp->regs + SOURCE_AIF_CAR);
2048 -
2049 -       val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN |
2050 -             SOURCE_CIPHER_SYS_CLK_EN |
2051 -             SOURCE_CIPHER_CHAR_CLK_RSTN_EN |
2052 -             SOURCE_CIPHER_CHAR_CLK_EN;
2053 -       writel(val, mhdp->regs + SOURCE_CIPHER_CAR);
2054 -
2055 -       val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN |
2056 -             SOURCE_CRYPTO_SYS_CLK_EN;
2057 -       writel(val, mhdp->regs + SOURCE_CRYPTO_CAR);
2058 -
2059 -       /* enable Mailbox and PIF interrupt */
2060 -       writel(0, mhdp->regs + APB_INT_MASK);
2061 -}
2062 -
2063 -static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
2064 -{
2065 -       int val, ret;
2066 -
2067 -       ret = readx_poll_timeout(readl, mhdp->regs + MAILBOX_EMPTY_ADDR,
2068 -                                val, !val, MAILBOX_RETRY_US,
2069 -                                MAILBOX_TIMEOUT_US);
2070 -       if (ret < 0)
2071 -               return ret;
2072 -
2073 -       return readl(mhdp->regs + MAILBOX0_RD_DATA) & 0xff;
2074 -}
2075 -
2076 -static int cdp_dp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
2077 -{
2078 -       int ret, full;
2079 -
2080 -       ret = readx_poll_timeout(readl, mhdp->regs + MAILBOX_FULL_ADDR,
2081 -                                full, !full, MAILBOX_RETRY_US,
2082 -                                MAILBOX_TIMEOUT_US);
2083 -       if (ret < 0)
2084 -               return ret;
2085 -
2086 -       writel(val, mhdp->regs + MAILBOX0_WR_DATA);
2087 -
2088 -       return 0;
2089 -}
2090 -
2091 -static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
2092 -                                             u8 module_id, u8 opcode,
2093 -                                             u16 req_size)
2094 -{
2095 -       u32 mbox_size, i;
2096 -       u8 header[4];
2097 -       int ret;
2098 -
2099 -       /* read the header of the message */
2100 -       for (i = 0; i < 4; i++) {
2101 -               ret = cdns_mhdp_mailbox_read(mhdp);
2102 -               if (ret < 0)
2103 -                       return ret;
2104 -
2105 -               header[i] = ret;
2106 -       }
2107 -
2108 -       mbox_size = (header[2] << 8) | header[3];
2109 -
2110 -       if (opcode != header[0] || module_id != header[1] ||
2111 -           req_size != mbox_size) {
2112 -               /*
2113 -                * If the message in mailbox is not what we want, we need to
2114 -                * clear the mailbox by reading its contents.
2115 -                */
2116 -               for (i = 0; i < mbox_size; i++)
2117 -                       if (cdns_mhdp_mailbox_read(mhdp) < 0)
2118 -                               break;
2119 -
2120 -               return -EINVAL;
2121 -       }
2122 -
2123 -       return 0;
2124 -}
2125 -
2126 -static int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp,
2127 -                                         u8 *buff, u16 buff_size)
2128 -{
2129 -       u32 i;
2130 -       int ret;
2131 -
2132 -       for (i = 0; i < buff_size; i++) {
2133 -               ret = cdns_mhdp_mailbox_read(mhdp);
2134 -               if (ret < 0)
2135 -                       return ret;
2136 -
2137 -               buff[i] = ret;
2138 -       }
2139 -
2140 -       return 0;
2141 -}
2142 -
2143 -static int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id,
2144 -                                 u8 opcode, u16 size, u8 *message)
2145 -{
2146 -       u8 header[4];
2147 -       int ret, i;
2148 -
2149 -       header[0] = opcode;
2150 -       header[1] = module_id;
2151 -       header[2] = (size >> 8) & 0xff;
2152 -       header[3] = size & 0xff;
2153 -
2154 -       for (i = 0; i < 4; i++) {
2155 -               ret = cdp_dp_mailbox_write(mhdp, header[i]);
2156 -               if (ret)
2157 -                       return ret;
2158 -       }
2159 -
2160 -       for (i = 0; i < size; i++) {
2161 -               ret = cdp_dp_mailbox_write(mhdp, message[i]);
2162 -               if (ret)
2163 -                       return ret;
2164 -       }
2165 -
2166 -       return 0;
2167 -}
2168 -
2169 -static int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u16 addr, u32 val)
2170 -{
2171 -       u8 msg[6];
2172 -
2173 -       msg[0] = (addr >> 8) & 0xff;
2174 -       msg[1] = addr & 0xff;
2175 -       msg[2] = (val >> 24) & 0xff;
2176 -       msg[3] = (val >> 16) & 0xff;
2177 -       msg[4] = (val >> 8) & 0xff;
2178 -       msg[5] = val & 0xff;
2179 -       return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2180 -                                     DPTX_WRITE_REGISTER, sizeof(msg), msg);
2181 -}
2182 -
2183 -static int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
2184 -                                  u8 start_bit, u8 bits_no, u32 val)
2185 -{
2186 -       u8 field[8];
2187 -
2188 -       field[0] = (addr >> 8) & 0xff;
2189 -       field[1] = addr & 0xff;
2190 -       field[2] = start_bit;
2191 -       field[3] = bits_no;
2192 -       field[4] = (val >> 24) & 0xff;
2193 -       field[5] = (val >> 16) & 0xff;
2194 -       field[6] = (val >> 8) & 0xff;
2195 -       field[7] = val & 0xff;
2196 -
2197 -       return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2198 -                                     DPTX_WRITE_FIELD, sizeof(field), field);
2199 -}
2200 -
2201 -int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
2202 -                       u32 addr, u8 *data, u16 len)
2203 -{
2204 -       u8 msg[5], reg[5];
2205 -       int ret;
2206 -
2207 -       msg[0] = (len >> 8) & 0xff;
2208 -       msg[1] = len & 0xff;
2209 -       msg[2] = (addr >> 16) & 0xff;
2210 -       msg[3] = (addr >> 8) & 0xff;
2211 -       msg[4] = addr & 0xff;
2212 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2213 -                                    DPTX_READ_DPCD, sizeof(msg), msg);
2214 -       if (ret)
2215 -               goto err_dpcd_read;
2216 -
2217 -       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
2218 -                                                DPTX_READ_DPCD,
2219 -                                                sizeof(reg) + len);
2220 -       if (ret)
2221 -               goto err_dpcd_read;
2222 -
2223 -       ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
2224 -       if (ret)
2225 -               goto err_dpcd_read;
2226 -
2227 -       ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len);
2228 -
2229 -err_dpcd_read:
2230 -       return ret;
2231 -}
2232 -
2233 -int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value)
2234 -{
2235 -       u8 msg[6], reg[5];
2236 -       int ret;
2237 -
2238 -       msg[0] = 0;
2239 -       msg[1] = 1;
2240 -       msg[2] = (addr >> 16) & 0xff;
2241 -       msg[3] = (addr >> 8) & 0xff;
2242 -       msg[4] = addr & 0xff;
2243 -       msg[5] = value;
2244 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2245 -                                    DPTX_WRITE_DPCD, sizeof(msg), msg);
2246 -       if (ret)
2247 -               goto err_dpcd_write;
2248 -
2249 -       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
2250 -                                                DPTX_WRITE_DPCD, sizeof(reg));
2251 -       if (ret)
2252 -               goto err_dpcd_write;
2253 -
2254 -       ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
2255 -       if (ret)
2256 -               goto err_dpcd_write;
2257 -
2258 -       if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4]))
2259 -               ret = -EINVAL;
2260 -
2261 -err_dpcd_write:
2262 -       if (ret)
2263 -               DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret);
2264 -       return ret;
2265 -}
2266 -
2267 -int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem,
2268 -                           u32 i_size, const u32 *d_mem, u32 d_size)
2269 -{
2270 -       u32 reg;
2271 -       int i, ret;
2272 -
2273 -       /* reset ucpu before load firmware*/
2274 -       writel(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET,
2275 -              mhdp->regs + APB_CTRL);
2276 -
2277 -       for (i = 0; i < i_size; i += 4)
2278 -               writel(*i_mem++, mhdp->regs + ADDR_IMEM + i);
2279 -
2280 -       for (i = 0; i < d_size; i += 4)
2281 -               writel(*d_mem++, mhdp->regs + ADDR_DMEM + i);
2282 -
2283 -       /* un-reset ucpu */
2284 -       writel(0, mhdp->regs + APB_CTRL);
2285 -
2286 -       /* check the keep alive register to make sure fw working */
2287 -       ret = readx_poll_timeout(readl, mhdp->regs + KEEP_ALIVE,
2288 -                                reg, reg, 2000, FW_ALIVE_TIMEOUT_US);
2289 -       if (ret < 0) {
2290 -               DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n",
2291 -                             reg);
2292 -               return -EINVAL;
2293 -       }
2294 -
2295 -       reg = readl(mhdp->regs + VER_L) & 0xff;
2296 -       mhdp->fw_version = reg;
2297 -       reg = readl(mhdp->regs + VER_H) & 0xff;
2298 -       mhdp->fw_version |= reg << 8;
2299 -       reg = readl(mhdp->regs + VER_LIB_L_ADDR) & 0xff;
2300 -       mhdp->fw_version |= reg << 16;
2301 -       reg = readl(mhdp->regs + VER_LIB_H_ADDR) & 0xff;
2302 -       mhdp->fw_version |= reg << 24;
2303 -
2304 -       DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version);
2305 -
2306 -       return 0;
2307 -}
2308 -
2309 -int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable)
2310 -{
2311 -       u8 msg[5];
2312 -       int ret, i;
2313 -
2314 -       msg[0] = GENERAL_MAIN_CONTROL;
2315 -       msg[1] = MB_MODULE_ID_GENERAL;
2316 -       msg[2] = 0;
2317 -       msg[3] = 1;
2318 -       msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
2319 -
2320 -       for (i = 0; i < sizeof(msg); i++) {
2321 -               ret = cdp_dp_mailbox_write(mhdp, msg[i]);
2322 -               if (ret)
2323 -                       goto err_set_firmware_active;
2324 -       }
2325 -
2326 -       /* read the firmware state */
2327 -       for (i = 0; i < sizeof(msg); i++)  {
2328 -               ret = cdns_mhdp_mailbox_read(mhdp);
2329 -               if (ret < 0)
2330 -                       goto err_set_firmware_active;
2331 -
2332 -               msg[i] = ret;
2333 -       }
2334 -
2335 -       ret = 0;
2336 -
2337 -err_set_firmware_active:
2338 -       if (ret < 0)
2339 -               DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n");
2340 -       return ret;
2341 -}
2342 -
2343 -int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, u8 lanes, bool flip)
2344 -{
2345 -       u8 msg[8];
2346 -       int ret;
2347 -
2348 -       msg[0] = CDNS_DP_MAX_LINK_RATE;
2349 -       msg[1] = lanes | SCRAMBLER_EN;
2350 -       msg[2] = VOLTAGE_LEVEL_2;
2351 -       msg[3] = PRE_EMPHASIS_LEVEL_3;
2352 -       msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
2353 -       msg[5] = FAST_LT_NOT_SUPPORT;
2354 -       msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL;
2355 -       msg[7] = ENHANCED;
2356 -
2357 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2358 -                                    DPTX_SET_HOST_CAPABILITIES,
2359 -                                    sizeof(msg), msg);
2360 -       if (ret)
2361 -               goto err_set_host_cap;
2362 -
2363 -       ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL,
2364 -                                 AUX_HOST_INVERT);
2365 -
2366 -err_set_host_cap:
2367 -       if (ret)
2368 -               DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret);
2369 -       return ret;
2370 -}
2371 -
2372 -int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp)
2373 -{
2374 -       u8 msg[5];
2375 -       int ret;
2376 -
2377 -       memset(msg, 0, sizeof(msg));
2378 -
2379 -       msg[0] = DPTX_EVENT_ENABLE_HPD | DPTX_EVENT_ENABLE_TRAINING;
2380 -
2381 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2382 -                                    DPTX_ENABLE_EVENT, sizeof(msg), msg);
2383 -       if (ret)
2384 -               DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret);
2385 -
2386 -       return ret;
2387 -}
2388 -
2389 -u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp)
2390 -{
2391 -       return readl(mhdp->regs + SW_EVENTS0);
2392 -}
2393 -
2394 -int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp)
2395 -{
2396 -       u8 status;
2397 -       int ret;
2398 -
2399 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2400 -                                    DPTX_HPD_STATE, 0, NULL);
2401 -       if (ret)
2402 -               goto err_get_hpd;
2403 -
2404 -       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
2405 -                                                DPTX_HPD_STATE,
2406 -                                                sizeof(status));
2407 -       if (ret)
2408 -               goto err_get_hpd;
2409 -
2410 -       ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status));
2411 -       if (ret)
2412 -               goto err_get_hpd;
2413 -
2414 -       return status;
2415 -
2416 -err_get_hpd:
2417 -       DRM_DEV_ERROR(mhdp->dev, "get hpd status failed: %d\n", ret);
2418 -       return ret;
2419 -}
2420 -
2421 -int cdns_mhdp_get_edid_block(void *data, u8 *edid,
2422 -                         unsigned int block, size_t length)
2423 -{
2424 -       struct cdns_mhdp_device *mhdp = data;
2425 -       u8 msg[2], reg[2], i;
2426 -       int ret;
2427 -
2428 -       for (i = 0; i < 4; i++) {
2429 -               msg[0] = block / 2;
2430 -               msg[1] = block % 2;
2431 -
2432 -               ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2433 -                                            DPTX_GET_EDID, sizeof(msg), msg);
2434 -               if (ret)
2435 -                       continue;
2436 -
2437 -               ret = cdns_mhdp_mailbox_validate_receive(mhdp,
2438 -                                                        MB_MODULE_ID_DP_TX,
2439 -                                                        DPTX_GET_EDID,
2440 -                                                        sizeof(reg) + length);
2441 -               if (ret)
2442 -                       continue;
2443 -
2444 -               ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg));
2445 -               if (ret)
2446 -                       continue;
2447 -
2448 -               ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length);
2449 -               if (ret)
2450 -                       continue;
2451 -
2452 -               if (reg[0] == length && reg[1] == block / 2)
2453 -                       break;
2454 -       }
2455 -
2456 -       if (ret)
2457 -               DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n",
2458 -                             block, ret);
2459 -
2460 -       return ret;
2461 -}
2462 -
2463 -static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp)
2464 -{
2465 -       unsigned long timeout;
2466 -       u8 msg, event[2];
2467 -       int ret;
2468 -
2469 -       msg = LINK_TRAINING_RUN;
2470 -
2471 -       /* start training */
2472 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2473 -                                    DPTX_TRAINING_CONTROL, sizeof(msg), &msg);
2474 -       if (ret)
2475 -               goto err_training_start;
2476 -
2477 -       timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS);
2478 -       while (time_before(jiffies, timeout)) {
2479 -               msleep(LINK_TRAINING_RETRY_MS);
2480 -               ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
2481 -                                            DPTX_READ_EVENT, 0, NULL);
2482 -               if (ret)
2483 -                       goto err_training_start;
2484 -
2485 -               ret = cdns_mhdp_mailbox_validate_receive(mhdp,
2486 -                                                        MB_MODULE_ID_DP_TX,
2487 -                                                        DPTX_READ_EVENT,
2488 -                                                        sizeof(event));
2489 -               if (ret)
2490 -                       goto err_training_start;
2491 -
2492 -               ret = cdns_mhdp_mailbox_read_receive(mhdp, event,
2493 -                                                    sizeof(event));
2494 -               if (ret)
2495 -                       goto err_training_start;
2496 -
2497 -               if (event[1] & EQ_PHASE_FINISHED)
2498 -                       return 0;
2499 -       }
2500 -
2501 -       ret = -ETIMEDOUT;
2502 -
2503 -err_training_start:
2504 -       DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret);
2505 -       return ret;
2506 -}
2507 -
2508 -static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp)
2509 -{
2510 -       u8 status[10];
2511 -       int ret;
2512 -
2513 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, DPTX_READ_LINK_STAT,
2514 -                                 0, NULL);
2515 -       if (ret)
2516 -               goto err_get_training_status;
2517 -
2518 -       ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX,
2519 -                                             DPTX_READ_LINK_STAT,
2520 -                                             sizeof(status));
2521 -       if (ret)
2522 -               goto err_get_training_status;
2523 -
2524 -       ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status));
2525 -       if (ret)
2526 -               goto err_get_training_status;
2527 -
2528 -       mhdp->link.rate = drm_dp_bw_code_to_link_rate(status[0]);
2529 -       mhdp->link.num_lanes = status[1];
2530 -
2531 -err_get_training_status:
2532 -       if (ret)
2533 -               DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n", ret);
2534 -       return ret;
2535 -}
2536 -
2537 -int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp)
2538 -{
2539 -       int ret;
2540 -
2541 -       ret = cdns_mhdp_training_start(mhdp);
2542 -       if (ret) {
2543 -               DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n", ret);
2544 -               return ret;
2545 -       }
2546 -
2547 -       ret = cdns_mhdp_get_training_status(mhdp);
2548 -       if (ret) {
2549 -               DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n", ret);
2550 -               return ret;
2551 -       }
2552 -
2553 -       DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->link.rate,
2554 -                         mhdp->link.num_lanes);
2555 -       return ret;
2556 -}
2557 -
2558 -int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active)
2559 -{
2560 -       u8 msg;
2561 -       int ret;
2562 -
2563 -       msg = !!active;
2564 -
2565 -       ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, DPTX_SET_VIDEO,
2566 -                                 sizeof(msg), &msg);
2567 -       if (ret)
2568 -               DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret);
2569 -
2570 -       return ret;
2571 -}
2572 -
2573 -static int cdns_mhdp_get_msa_misc(struct video_info *video,
2574 -                              struct drm_display_mode *mode)
2575 -{
2576 -       u32 msa_misc;
2577 -       u8 val[2] = {0};
2578 -
2579 -       switch (video->color_fmt) {
2580 -       case PXL_RGB:
2581 -       case Y_ONLY:
2582 -               val[0] = 0;
2583 -               break;
2584 -       /* set YUV default color space conversion to BT601 */
2585 -       case YCBCR_4_4_4:
2586 -               val[0] = 6 + BT_601 * 8;
2587 -               break;
2588 -       case YCBCR_4_2_2:
2589 -               val[0] = 5 + BT_601 * 8;
2590 -               break;
2591 -       case YCBCR_4_2_0:
2592 -               val[0] = 5;
2593 -               break;
2594 -       };
2595 -
2596 -       switch (video->color_depth) {
2597 -       case 6:
2598 -               val[1] = 0;
2599 -               break;
2600 -       case 8:
2601 -               val[1] = 1;
2602 -               break;
2603 -       case 10:
2604 -               val[1] = 2;
2605 -               break;
2606 -       case 12:
2607 -               val[1] = 3;
2608 -               break;
2609 -       case 16:
2610 -               val[1] = 4;
2611 -               break;
2612 -       };
2613 -
2614 -       msa_misc = 2 * val[0] + 32 * val[1] +
2615 -                  ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0);
2616 -
2617 -       return msa_misc;
2618 -}
2619 -
2620 -int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp)
2621 -{
2622 -       struct video_info *video = &mhdp->video_info;
2623 -       struct drm_display_mode *mode = &mhdp->mode;
2624 -       u64 symbol;
2625 -       u32 val, link_rate, rem;
2626 -       u8 bit_per_pix, tu_size_reg = TU_SIZE;
2627 -       int ret;
2628 -
2629 -       bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ?
2630 -                     (video->color_depth * 2) : (video->color_depth * 3);
2631 -
2632 -       link_rate = mhdp->link.rate / 1000;
2633 -
2634 -       ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE);
2635 -       if (ret)
2636 -               goto err_config_video;
2637 -
2638 -       ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0);
2639 -       if (ret)
2640 -               goto err_config_video;
2641 -
2642 -       /*
2643 -        * get a best tu_size and valid symbol:
2644 -        * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32
2645 -        * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes)
2646 -        * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set
2647 -        *    TU += 2 and repeat 2nd step.
2648 -        */
2649 -       do {
2650 -               tu_size_reg += 2;
2651 -               symbol = tu_size_reg * mode->clock * bit_per_pix;
2652 -               do_div(symbol, mhdp->link.num_lanes * link_rate * 8);
2653 -               rem = do_div(symbol, 1000);
2654 -               if (tu_size_reg > 64) {
2655 -                       ret = -EINVAL;
2656 -                       DRM_DEV_ERROR(mhdp->dev,
2657 -                                     "tu error, clk:%d, lanes:%d, rate:%d\n",
2658 -                                     mode->clock, mhdp->link.num_lanes,
2659 -                                     link_rate);
2660 -                       goto err_config_video;
2661 -               }
2662 -       } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
2663 -                (rem > 850) || (rem < 100));
2664 -
2665 -       val = symbol + (tu_size_reg << 8);
2666 -       val |= TU_CNT_RST_EN;
2667 -       ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val);
2668 -       if (ret)
2669 -               goto err_config_video;
2670 -
2671 -       /* set the FIFO Buffer size */
2672 -       val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
2673 -       val /= (mhdp->link.num_lanes * link_rate);
2674 -       val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
2675 -       val += 2;
2676 -       ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val);
2677 -
2678 -       switch (video->color_depth) {
2679 -       case 6:
2680 -               val = BCS_6;
2681 -               break;
2682 -       case 8:
2683 -               val = BCS_8;
2684 -               break;
2685 -       case 10:
2686 -               val = BCS_10;
2687 -               break;
2688 -       case 12:
2689 -               val = BCS_12;
2690 -               break;
2691 -       case 16:
2692 -               val = BCS_16;
2693 -               break;
2694 -       };
2695 -
2696 -       val += video->color_fmt << 8;
2697 -       ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val);
2698 -       if (ret)
2699 -               goto err_config_video;
2700 -
2701 -       val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0;
2702 -       val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0;
2703 -       ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val);
2704 -       if (ret)
2705 -               goto err_config_video;
2706 -
2707 -       val = (mode->hsync_start - mode->hdisplay) << 16;
2708 -       val |= mode->htotal - mode->hsync_end;
2709 -       ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val);
2710 -       if (ret)
2711 -               goto err_config_video;
2712 -
2713 -       val = mode->hdisplay * bit_per_pix / 8;
2714 -       ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val);
2715 -       if (ret)
2716 -               goto err_config_video;
2717 -
2718 -       val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16);
2719 -       ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val);
2720 -       if (ret)
2721 -               goto err_config_video;
2722 -
2723 -       val = mode->hsync_end - mode->hsync_start;
2724 -       val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15);
2725 -       ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val);
2726 -       if (ret)
2727 -               goto err_config_video;
2728 -
2729 -       val = mode->vtotal;
2730 -       val |= (mode->vtotal - mode->vsync_start) << 16;
2731 -       ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val);
2732 -       if (ret)
2733 -               goto err_config_video;
2734 -
2735 -       val = mode->vsync_end - mode->vsync_start;
2736 -       val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15);
2737 -       ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val);
2738 -       if (ret)
2739 -               goto err_config_video;
2740 -
2741 -       val = cdns_mhdp_get_msa_misc(video, mode);
2742 -       ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val);
2743 -       if (ret)
2744 -               goto err_config_video;
2745 -
2746 -       ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1);
2747 -       if (ret)
2748 -               goto err_config_video;
2749 -
2750 -       val = mode->hsync_end - mode->hsync_start;
2751 -       val |= mode->hdisplay << 16;
2752 -       ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val);
2753 -       if (ret)
2754 -               goto err_config_video;
2755 -
2756 -       val = mode->vdisplay;
2757 -       val |= (mode->vtotal - mode->vsync_start) << 16;
2758 -       ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val);
2759 -       if (ret)
2760 -               goto err_config_video;
2761 -
2762 -       val = mode->vtotal;
2763 -       ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val);
2764 -       if (ret)
2765 -               goto err_config_video;
2766 -
2767 -       ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0);
2768 -
2769 -err_config_video:
2770 -       if (ret)
2771 -               DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret);
2772 -       return ret;
2773 -}
2774 -
2775 -int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp,
2776 -                        struct audio_info *audio)
2777 -{
2778 -       int ret;
2779 -
2780 -       ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, 0);
2781 -       if (ret) {
2782 -               DRM_DEV_ERROR(mhdp->dev, "audio stop failed: %d\n", ret);
2783 -               return ret;
2784 -       }
2785 -
2786 -       writel(0, mhdp->regs + SPDIF_CTRL_ADDR);
2787 -
2788 -       /* clearn the audio config and reset */
2789 -       writel(0, mhdp->regs + AUDIO_SRC_CNTL);
2790 -       writel(0, mhdp->regs + AUDIO_SRC_CNFG);
2791 -       writel(AUDIO_SW_RST, mhdp->regs + AUDIO_SRC_CNTL);
2792 -       writel(0, mhdp->regs + AUDIO_SRC_CNTL);
2793 -
2794 -       /* reset smpl2pckt component  */
2795 -       writel(0, mhdp->regs + SMPL2PKT_CNTL);
2796 -       writel(AUDIO_SW_RST, mhdp->regs + SMPL2PKT_CNTL);
2797 -       writel(0, mhdp->regs + SMPL2PKT_CNTL);
2798 -
2799 -       /* reset FIFO */
2800 -       writel(AUDIO_SW_RST, mhdp->regs + FIFO_CNTL);
2801 -       writel(0, mhdp->regs + FIFO_CNTL);
2802 -
2803 -       if (audio->format == AFMT_SPDIF)
2804 -               clk_disable_unprepare(mhdp->spdif_clk);
2805 -
2806 -       return 0;
2807 -}
2808 -
2809 -int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable)
2810 -{
2811 -       int ret;
2812 -
2813 -       ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 4, 1, enable);
2814 -       if (ret)
2815 -               DRM_DEV_ERROR(mhdp->dev, "audio mute failed: %d\n", ret);
2816 -
2817 -       return ret;
2818 -}
2819 -
2820 -static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp,
2821 -                                      struct audio_info *audio)
2822 -{
2823 -       int sub_pckt_num = 1, i2s_port_en_val = 0xf, i;
2824 -       u32 val;
2825 -
2826 -       if (audio->channels == 2) {
2827 -               if (mhdp->link.num_lanes == 1)
2828 -                       sub_pckt_num = 2;
2829 -               else
2830 -                       sub_pckt_num = 4;
2831 -
2832 -               i2s_port_en_val = 1;
2833 -       } else if (audio->channels == 4) {
2834 -               i2s_port_en_val = 3;
2835 -       }
2836 -
2837 -       writel(0x0, mhdp->regs + SPDIF_CTRL_ADDR);
2838 -
2839 -       writel(SYNC_WR_TO_CH_ZERO, mhdp->regs + FIFO_CNTL);
2840 -
2841 -       val = MAX_NUM_CH(audio->channels);
2842 -       val |= NUM_OF_I2S_PORTS(audio->channels);
2843 -       val |= AUDIO_TYPE_LPCM;
2844 -       val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
2845 -       writel(val, mhdp->regs + SMPL2PKT_CNFG);
2846 -
2847 -       if (audio->sample_width == 16)
2848 -               val = 0;
2849 -       else if (audio->sample_width == 24)
2850 -               val = 1 << 9;
2851 -       else
2852 -               val = 2 << 9;
2853 -
2854 -       val |= AUDIO_CH_NUM(audio->channels);
2855 -       val |= I2S_DEC_PORT_EN(i2s_port_en_val);
2856 -       val |= TRANS_SMPL_WIDTH_32;
2857 -       writel(val, mhdp->regs + AUDIO_SRC_CNFG);
2858 -
2859 -       for (i = 0; i < (audio->channels + 1) / 2; i++) {
2860 -               if (audio->sample_width == 16)
2861 -                       val = (0x02 << 8) | (0x02 << 20);
2862 -               else if (audio->sample_width == 24)
2863 -                       val = (0x0b << 8) | (0x0b << 20);
2864 -
2865 -               val |= ((2 * i) << 4) | ((2 * i + 1) << 16);
2866 -               writel(val, mhdp->regs + STTS_BIT_CH(i));
2867 -       }
2868 -
2869 -       switch (audio->sample_rate) {
2870 -       case 32000:
2871 -               val = SAMPLING_FREQ(3) |
2872 -                     ORIGINAL_SAMP_FREQ(0xc);
2873 -               break;
2874 -       case 44100:
2875 -               val = SAMPLING_FREQ(0) |
2876 -                     ORIGINAL_SAMP_FREQ(0xf);
2877 -               break;
2878 -       case 48000:
2879 -               val = SAMPLING_FREQ(2) |
2880 -                     ORIGINAL_SAMP_FREQ(0xd);
2881 -               break;
2882 -       case 88200:
2883 -               val = SAMPLING_FREQ(8) |
2884 -                     ORIGINAL_SAMP_FREQ(0x7);
2885 -               break;
2886 -       case 96000:
2887 -               val = SAMPLING_FREQ(0xa) |
2888 -                     ORIGINAL_SAMP_FREQ(5);
2889 -               break;
2890 -       case 176400:
2891 -               val = SAMPLING_FREQ(0xc) |
2892 -                     ORIGINAL_SAMP_FREQ(3);
2893 -               break;
2894 -       case 192000:
2895 -               val = SAMPLING_FREQ(0xe) |
2896 -                     ORIGINAL_SAMP_FREQ(1);
2897 -               break;
2898 -       }
2899 -       val |= 4;
2900 -       writel(val, mhdp->regs + COM_CH_STTS_BITS);
2901 -
2902 -       writel(SMPL2PKT_EN, mhdp->regs + SMPL2PKT_CNTL);
2903 -       writel(I2S_DEC_START, mhdp->regs + AUDIO_SRC_CNTL);
2904 -}
2905 -
2906 -static void cdns_mhdp_audio_config_spdif(struct cdns_mhdp_device *mhdp)
2907 -{
2908 -       u32 val;
2909 -
2910 -       writel(SYNC_WR_TO_CH_ZERO, mhdp->regs + FIFO_CNTL);
2911 -
2912 -       val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4);
2913 -       writel(val, mhdp->regs + SMPL2PKT_CNFG);
2914 -       writel(SMPL2PKT_EN, mhdp->regs + SMPL2PKT_CNTL);
2915 -
2916 -       val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
2917 -       writel(val, mhdp->regs + SPDIF_CTRL_ADDR);
2918 -
2919 -       clk_prepare_enable(mhdp->spdif_clk);
2920 -       clk_set_rate(mhdp->spdif_clk, CDNS_DP_SPDIF_CLK);
2921 -}
2922 -
2923 -int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp,
2924 -                          struct audio_info *audio)
2925 -{
2926 -       int ret;
2927 -
2928 -       /* reset the spdif clk before config */
2929 -       if (audio->format == AFMT_SPDIF) {
2930 -               reset_control_assert(mhdp->spdif_rst);
2931 -               reset_control_deassert(mhdp->spdif_rst);
2932 -       }
2933 -
2934 -       ret = cdns_mhdp_reg_write(mhdp, CM_LANE_CTRL, LANE_REF_CYC);
2935 -       if (ret)
2936 -               goto err_audio_config;
2937 -
2938 -       ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 0);
2939 -       if (ret)
2940 -               goto err_audio_config;
2941 -
2942 -       if (audio->format == AFMT_I2S)
2943 -               cdns_mhdp_audio_config_i2s(mhdp, audio);
2944 -       else if (audio->format == AFMT_SPDIF)
2945 -               cdns_mhdp_audio_config_spdif(mhdp);
2946 -
2947 -       ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN);
2948 -
2949 -err_audio_config:
2950 -       if (ret)
2951 -               DRM_DEV_ERROR(mhdp->dev, "audio config failed: %d\n", ret);
2952 -       return ret;
2953 -}
2954 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.h
2955 +++ /dev/null
2956 @@ -1,546 +0,0 @@
2957 -/* SPDX-License-Identifier: GPL-2.0-only */
2958 -/*
2959 - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
2960 - * Author: Chris Zhong <zyw@rock-chips.com>
2961 - */
2962 -
2963 -#ifndef _CDN_DP_REG_H
2964 -#define _CDN_DP_REG_H
2965 -
2966 -#include <linux/bitops.h>
2967 -
2968 -#define ADDR_IMEM              0x10000
2969 -#define ADDR_DMEM              0x20000
2970 -
2971 -/* APB CFG addr */
2972 -#define APB_CTRL                       0
2973 -#define XT_INT_CTRL                    0x04
2974 -#define MAILBOX_FULL_ADDR              0x08
2975 -#define MAILBOX_EMPTY_ADDR             0x0c
2976 -#define MAILBOX0_WR_DATA               0x10
2977 -#define MAILBOX0_RD_DATA               0x14
2978 -#define KEEP_ALIVE                     0x18
2979 -#define VER_L                          0x1c
2980 -#define VER_H                          0x20
2981 -#define VER_LIB_L_ADDR                 0x24
2982 -#define VER_LIB_H_ADDR                 0x28
2983 -#define SW_DEBUG_L                     0x2c
2984 -#define SW_DEBUG_H                     0x30
2985 -#define MAILBOX_INT_MASK               0x34
2986 -#define MAILBOX_INT_STATUS             0x38
2987 -#define SW_CLK_L                       0x3c
2988 -#define SW_CLK_H                       0x40
2989 -#define SW_EVENTS0                     0x44
2990 -#define SW_EVENTS1                     0x48
2991 -#define SW_EVENTS2                     0x4c
2992 -#define SW_EVENTS3                     0x50
2993 -#define XT_OCD_CTRL                    0x60
2994 -#define APB_INT_MASK                   0x6c
2995 -#define APB_STATUS_MASK                        0x70
2996 -
2997 -/* audio decoder addr */
2998 -#define AUDIO_SRC_CNTL                 0x30000
2999 -#define AUDIO_SRC_CNFG                 0x30004
3000 -#define COM_CH_STTS_BITS               0x30008
3001 -#define STTS_BIT_CH(x)                 (0x3000c + ((x) << 2))
3002 -#define SPDIF_CTRL_ADDR                        0x3004c
3003 -#define SPDIF_CH1_CS_3100_ADDR         0x30050
3004 -#define SPDIF_CH1_CS_6332_ADDR         0x30054
3005 -#define SPDIF_CH1_CS_9564_ADDR         0x30058
3006 -#define SPDIF_CH1_CS_12796_ADDR                0x3005c
3007 -#define SPDIF_CH1_CS_159128_ADDR       0x30060
3008 -#define SPDIF_CH1_CS_191160_ADDR       0x30064
3009 -#define SPDIF_CH2_CS_3100_ADDR         0x30068
3010 -#define SPDIF_CH2_CS_6332_ADDR         0x3006c
3011 -#define SPDIF_CH2_CS_9564_ADDR         0x30070
3012 -#define SPDIF_CH2_CS_12796_ADDR                0x30074
3013 -#define SPDIF_CH2_CS_159128_ADDR       0x30078
3014 -#define SPDIF_CH2_CS_191160_ADDR       0x3007c
3015 -#define SMPL2PKT_CNTL                  0x30080
3016 -#define SMPL2PKT_CNFG                  0x30084
3017 -#define FIFO_CNTL                      0x30088
3018 -#define FIFO_STTS                      0x3008c
3019 -
3020 -/* source pif addr */
3021 -#define SOURCE_PIF_WR_ADDR             0x30800
3022 -#define SOURCE_PIF_WR_REQ              0x30804
3023 -#define SOURCE_PIF_RD_ADDR             0x30808
3024 -#define SOURCE_PIF_RD_REQ              0x3080c
3025 -#define SOURCE_PIF_DATA_WR             0x30810
3026 -#define SOURCE_PIF_DATA_RD             0x30814
3027 -#define SOURCE_PIF_FIFO1_FLUSH         0x30818
3028 -#define SOURCE_PIF_FIFO2_FLUSH         0x3081c
3029 -#define SOURCE_PIF_STATUS              0x30820
3030 -#define SOURCE_PIF_INTERRUPT_SOURCE    0x30824
3031 -#define SOURCE_PIF_INTERRUPT_MASK      0x30828
3032 -#define SOURCE_PIF_PKT_ALLOC_REG       0x3082c
3033 -#define SOURCE_PIF_PKT_ALLOC_WR_EN     0x30830
3034 -#define SOURCE_PIF_SW_RESET            0x30834
3035 -
3036 -/* bellow registers need access by mailbox */
3037 -/* source car addr */
3038 -#define SOURCE_HDTX_CAR                        0x0900
3039 -#define SOURCE_DPTX_CAR                        0x0904
3040 -#define SOURCE_PHY_CAR                 0x0908
3041 -#define SOURCE_CEC_CAR                 0x090c
3042 -#define SOURCE_CBUS_CAR                        0x0910
3043 -#define SOURCE_PKT_CAR                 0x0918
3044 -#define SOURCE_AIF_CAR                 0x091c
3045 -#define SOURCE_CIPHER_CAR              0x0920
3046 -#define SOURCE_CRYPTO_CAR              0x0924
3047 -
3048 -/* clock meters addr */
3049 -#define CM_CTRL                                0x0a00
3050 -#define CM_I2S_CTRL                    0x0a04
3051 -#define CM_SPDIF_CTRL                  0x0a08
3052 -#define CM_VID_CTRL                    0x0a0c
3053 -#define CM_LANE_CTRL                   0x0a10
3054 -#define I2S_NM_STABLE                  0x0a14
3055 -#define I2S_NCTS_STABLE                        0x0a18
3056 -#define SPDIF_NM_STABLE                        0x0a1c
3057 -#define SPDIF_NCTS_STABLE              0x0a20
3058 -#define NMVID_MEAS_STABLE              0x0a24
3059 -#define I2S_MEAS                       0x0a40
3060 -#define SPDIF_MEAS                     0x0a80
3061 -#define NMVID_MEAS                     0x0ac0
3062 -
3063 -/* source vif addr */
3064 -#define BND_HSYNC2VSYNC                        0x0b00
3065 -#define HSYNC2VSYNC_F1_L1              0x0b04
3066 -#define HSYNC2VSYNC_F2_L1              0x0b08
3067 -#define HSYNC2VSYNC_STATUS             0x0b0c
3068 -#define HSYNC2VSYNC_POL_CTRL           0x0b10
3069 -
3070 -/* dptx phy addr */
3071 -#define DP_TX_PHY_CONFIG_REG           0x2000
3072 -#define DP_TX_PHY_SW_RESET             0x2004
3073 -#define DP_TX_PHY_SCRAMBLER_SEED       0x2008
3074 -#define DP_TX_PHY_TRAINING_01_04       0x200c
3075 -#define DP_TX_PHY_TRAINING_05_08       0x2010
3076 -#define DP_TX_PHY_TRAINING_09_10       0x2014
3077 -#define TEST_COR                       0x23fc
3078 -
3079 -/* dptx hpd addr */
3080 -#define HPD_IRQ_DET_MIN_TIMER          0x2100
3081 -#define HPD_IRQ_DET_MAX_TIMER          0x2104
3082 -#define HPD_UNPLGED_DET_MIN_TIMER      0x2108
3083 -#define HPD_STABLE_TIMER               0x210c
3084 -#define HPD_FILTER_TIMER               0x2110
3085 -#define HPD_EVENT_MASK                 0x211c
3086 -#define HPD_EVENT_DET                  0x2120
3087 -
3088 -/* dpyx framer addr */
3089 -#define DP_FRAMER_GLOBAL_CONFIG                0x2200
3090 -#define DP_SW_RESET                    0x2204
3091 -#define DP_FRAMER_TU                   0x2208
3092 -#define DP_FRAMER_PXL_REPR             0x220c
3093 -#define DP_FRAMER_SP                   0x2210
3094 -#define AUDIO_PACK_CONTROL             0x2214
3095 -#define DP_VC_TABLE(x)                 (0x2218 + ((x) << 2))
3096 -#define DP_VB_ID                       0x2258
3097 -#define DP_MTPH_LVP_CONTROL            0x225c
3098 -#define DP_MTPH_SYMBOL_VALUES          0x2260
3099 -#define DP_MTPH_ECF_CONTROL            0x2264
3100 -#define DP_MTPH_ACT_CONTROL            0x2268
3101 -#define DP_MTPH_STATUS                 0x226c
3102 -#define DP_INTERRUPT_SOURCE            0x2270
3103 -#define DP_INTERRUPT_MASK              0x2274
3104 -#define DP_FRONT_BACK_PORCH            0x2278
3105 -#define DP_BYTE_COUNT                  0x227c
3106 -
3107 -/* dptx stream addr */
3108 -#define MSA_HORIZONTAL_0               0x2280
3109 -#define MSA_HORIZONTAL_1               0x2284
3110 -#define MSA_VERTICAL_0                 0x2288
3111 -#define MSA_VERTICAL_1                 0x228c
3112 -#define MSA_MISC                       0x2290
3113 -#define STREAM_CONFIG                  0x2294
3114 -#define AUDIO_PACK_STATUS              0x2298
3115 -#define VIF_STATUS                     0x229c
3116 -#define PCK_STUFF_STATUS_0             0x22a0
3117 -#define PCK_STUFF_STATUS_1             0x22a4
3118 -#define INFO_PACK_STATUS               0x22a8
3119 -#define RATE_GOVERNOR_STATUS           0x22ac
3120 -#define DP_HORIZONTAL                  0x22b0
3121 -#define DP_VERTICAL_0                  0x22b4
3122 -#define DP_VERTICAL_1                  0x22b8
3123 -#define DP_BLOCK_SDP                   0x22bc
3124 -
3125 -/* dptx glbl addr */
3126 -#define DPTX_LANE_EN                   0x2300
3127 -#define DPTX_ENHNCD                    0x2304
3128 -#define DPTX_INT_MASK                  0x2308
3129 -#define DPTX_INT_STATUS                        0x230c
3130 -
3131 -/* dp aux addr */
3132 -#define DP_AUX_HOST_CONTROL            0x2800
3133 -#define DP_AUX_INTERRUPT_SOURCE                0x2804
3134 -#define DP_AUX_INTERRUPT_MASK          0x2808
3135 -#define DP_AUX_SWAP_INVERSION_CONTROL  0x280c
3136 -#define DP_AUX_SEND_NACK_TRANSACTION   0x2810
3137 -#define DP_AUX_CLEAR_RX                        0x2814
3138 -#define DP_AUX_CLEAR_TX                        0x2818
3139 -#define DP_AUX_TIMER_STOP              0x281c
3140 -#define DP_AUX_TIMER_CLEAR             0x2820
3141 -#define DP_AUX_RESET_SW                        0x2824
3142 -#define DP_AUX_DIVIDE_2M               0x2828
3143 -#define DP_AUX_TX_PREACHARGE_LENGTH    0x282c
3144 -#define DP_AUX_FREQUENCY_1M_MAX                0x2830
3145 -#define DP_AUX_FREQUENCY_1M_MIN                0x2834
3146 -#define DP_AUX_RX_PRE_MIN              0x2838
3147 -#define DP_AUX_RX_PRE_MAX              0x283c
3148 -#define DP_AUX_TIMER_PRESET            0x2840
3149 -#define DP_AUX_NACK_FORMAT             0x2844
3150 -#define DP_AUX_TX_DATA                 0x2848
3151 -#define DP_AUX_RX_DATA                 0x284c
3152 -#define DP_AUX_TX_STATUS               0x2850
3153 -#define DP_AUX_RX_STATUS               0x2854
3154 -#define DP_AUX_RX_CYCLE_COUNTER                0x2858
3155 -#define DP_AUX_MAIN_STATES             0x285c
3156 -#define DP_AUX_MAIN_TIMER              0x2860
3157 -#define DP_AUX_AFE_OUT                 0x2864
3158 -
3159 -/* crypto addr */
3160 -#define CRYPTO_HDCP_REVISION           0x5800
3161 -#define HDCP_CRYPTO_CONFIG             0x5804
3162 -#define CRYPTO_INTERRUPT_SOURCE                0x5808
3163 -#define CRYPTO_INTERRUPT_MASK          0x580c
3164 -#define CRYPTO22_CONFIG                        0x5818
3165 -#define CRYPTO22_STATUS                        0x581c
3166 -#define SHA_256_DATA_IN                        0x583c
3167 -#define SHA_256_DATA_OUT_(x)           (0x5850 + ((x) << 2))
3168 -#define AES_32_KEY_(x)                 (0x5870 + ((x) << 2))
3169 -#define AES_32_DATA_IN                 0x5880
3170 -#define AES_32_DATA_OUT_(x)            (0x5884 + ((x) << 2))
3171 -#define CRYPTO14_CONFIG                        0x58a0
3172 -#define CRYPTO14_STATUS                        0x58a4
3173 -#define CRYPTO14_PRNM_OUT              0x58a8
3174 -#define CRYPTO14_KM_0                  0x58ac
3175 -#define CRYPTO14_KM_1                  0x58b0
3176 -#define CRYPTO14_AN_0                  0x58b4
3177 -#define CRYPTO14_AN_1                  0x58b8
3178 -#define CRYPTO14_YOUR_KSV_0            0x58bc
3179 -#define CRYPTO14_YOUR_KSV_1            0x58c0
3180 -#define CRYPTO14_MI_0                  0x58c4
3181 -#define CRYPTO14_MI_1                  0x58c8
3182 -#define CRYPTO14_TI_0                  0x58cc
3183 -#define CRYPTO14_KI_0                  0x58d0
3184 -#define CRYPTO14_KI_1                  0x58d4
3185 -#define CRYPTO14_BLOCKS_NUM            0x58d8
3186 -#define CRYPTO14_KEY_MEM_DATA_0                0x58dc
3187 -#define CRYPTO14_KEY_MEM_DATA_1                0x58e0
3188 -#define CRYPTO14_SHA1_MSG_DATA         0x58e4
3189 -#define CRYPTO14_SHA1_V_VALUE_(x)      (0x58e8 + ((x) << 2))
3190 -#define TRNG_CTRL                      0x58fc
3191 -#define TRNG_DATA_RDY                  0x5900
3192 -#define TRNG_DATA                      0x5904
3193 -
3194 -/* cipher addr */
3195 -#define HDCP_REVISION                  0x60000
3196 -#define INTERRUPT_SOURCE               0x60004
3197 -#define INTERRUPT_MASK                 0x60008
3198 -#define HDCP_CIPHER_CONFIG             0x6000c
3199 -#define AES_128_KEY_0                  0x60010
3200 -#define AES_128_KEY_1                  0x60014
3201 -#define AES_128_KEY_2                  0x60018
3202 -#define AES_128_KEY_3                  0x6001c
3203 -#define AES_128_RANDOM_0               0x60020
3204 -#define AES_128_RANDOM_1               0x60024
3205 -#define CIPHER14_KM_0                  0x60028
3206 -#define CIPHER14_KM_1                  0x6002c
3207 -#define CIPHER14_STATUS                        0x60030
3208 -#define CIPHER14_RI_PJ_STATUS          0x60034
3209 -#define CIPHER_MODE                    0x60038
3210 -#define CIPHER14_AN_0                  0x6003c
3211 -#define CIPHER14_AN_1                  0x60040
3212 -#define CIPHER22_AUTH                  0x60044
3213 -#define CIPHER14_R0_DP_STATUS          0x60048
3214 -#define CIPHER14_BOOTSTRAP             0x6004c
3215 -
3216 -#define DPTX_FRMR_DATA_CLK_RSTN_EN     BIT(11)
3217 -#define DPTX_FRMR_DATA_CLK_EN          BIT(10)
3218 -#define DPTX_PHY_DATA_RSTN_EN          BIT(9)
3219 -#define DPTX_PHY_DATA_CLK_EN           BIT(8)
3220 -#define DPTX_PHY_CHAR_RSTN_EN          BIT(7)
3221 -#define DPTX_PHY_CHAR_CLK_EN           BIT(6)
3222 -#define SOURCE_AUX_SYS_CLK_RSTN_EN     BIT(5)
3223 -#define SOURCE_AUX_SYS_CLK_EN          BIT(4)
3224 -#define DPTX_SYS_CLK_RSTN_EN           BIT(3)
3225 -#define DPTX_SYS_CLK_EN                        BIT(2)
3226 -#define CFG_DPTX_VIF_CLK_RSTN_EN       BIT(1)
3227 -#define CFG_DPTX_VIF_CLK_EN            BIT(0)
3228 -
3229 -#define SOURCE_PHY_RSTN_EN             BIT(1)
3230 -#define SOURCE_PHY_CLK_EN              BIT(0)
3231 -
3232 -#define SOURCE_PKT_SYS_RSTN_EN         BIT(3)
3233 -#define SOURCE_PKT_SYS_CLK_EN          BIT(2)
3234 -#define SOURCE_PKT_DATA_RSTN_EN                BIT(1)
3235 -#define SOURCE_PKT_DATA_CLK_EN         BIT(0)
3236 -
3237 -#define SPDIF_CDR_CLK_RSTN_EN          BIT(5)
3238 -#define SPDIF_CDR_CLK_EN               BIT(4)
3239 -#define SOURCE_AIF_SYS_RSTN_EN         BIT(3)
3240 -#define SOURCE_AIF_SYS_CLK_EN          BIT(2)
3241 -#define SOURCE_AIF_CLK_RSTN_EN         BIT(1)
3242 -#define SOURCE_AIF_CLK_EN              BIT(0)
3243 -
3244 -#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN       BIT(3)
3245 -#define SOURCE_CIPHER_SYS_CLK_EN               BIT(2)
3246 -#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN         BIT(1)
3247 -#define SOURCE_CIPHER_CHAR_CLK_EN              BIT(0)
3248 -
3249 -#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN  BIT(1)
3250 -#define SOURCE_CRYPTO_SYS_CLK_EN       BIT(0)
3251 -
3252 -#define APB_IRAM_PATH                  BIT(2)
3253 -#define APB_DRAM_PATH                  BIT(1)
3254 -#define APB_XT_RESET                   BIT(0)
3255 -
3256 -#define MAILBOX_INT_MASK_BIT           BIT(1)
3257 -#define PIF_INT_MASK_BIT               BIT(0)
3258 -#define ALL_INT_MASK                   3
3259 -
3260 -/* mailbox */
3261 -#define MB_OPCODE_ID                   0
3262 -#define MB_MODULE_ID                   1
3263 -#define MB_SIZE_MSB_ID                 2
3264 -#define MB_SIZE_LSB_ID                 3
3265 -#define MB_DATA_ID                     4
3266 -
3267 -#define MB_MODULE_ID_DP_TX             0x01
3268 -#define MB_MODULE_ID_HDCP_TX           0x07
3269 -#define MB_MODULE_ID_HDCP_RX           0x08
3270 -#define MB_MODULE_ID_HDCP_GENERAL      0x09
3271 -#define MB_MODULE_ID_GENERAL           0x0a
3272 -
3273 -/* general opcode */
3274 -#define GENERAL_MAIN_CONTROL            0x01
3275 -#define GENERAL_TEST_ECHO               0x02
3276 -#define GENERAL_BUS_SETTINGS            0x03
3277 -#define GENERAL_TEST_ACCESS             0x04
3278 -
3279 -#define DPTX_SET_POWER_MNG                     0x00
3280 -#define DPTX_SET_HOST_CAPABILITIES             0x01
3281 -#define DPTX_GET_EDID                          0x02
3282 -#define DPTX_READ_DPCD                         0x03
3283 -#define DPTX_WRITE_DPCD                                0x04
3284 -#define DPTX_ENABLE_EVENT                      0x05
3285 -#define DPTX_WRITE_REGISTER                    0x06
3286 -#define DPTX_READ_REGISTER                     0x07
3287 -#define DPTX_WRITE_FIELD                       0x08
3288 -#define DPTX_TRAINING_CONTROL                  0x09
3289 -#define DPTX_READ_EVENT                                0x0a
3290 -#define DPTX_READ_LINK_STAT                    0x0b
3291 -#define DPTX_SET_VIDEO                         0x0c
3292 -#define DPTX_SET_AUDIO                         0x0d
3293 -#define DPTX_GET_LAST_AUX_STAUS                        0x0e
3294 -#define DPTX_SET_LINK_BREAK_POINT              0x0f
3295 -#define DPTX_FORCE_LANES                       0x10
3296 -#define DPTX_HPD_STATE                         0x11
3297 -
3298 -#define FW_STANDBY                             0
3299 -#define FW_ACTIVE                              1
3300 -
3301 -#define DPTX_EVENT_ENABLE_HPD                  BIT(0)
3302 -#define DPTX_EVENT_ENABLE_TRAINING             BIT(1)
3303 -
3304 -#define LINK_TRAINING_NOT_ACTIVE               0
3305 -#define LINK_TRAINING_RUN                      1
3306 -#define LINK_TRAINING_RESTART                  2
3307 -
3308 -#define CONTROL_VIDEO_IDLE                     0
3309 -#define CONTROL_VIDEO_VALID                    1
3310 -
3311 -#define TU_CNT_RST_EN                          BIT(15)
3312 -#define VIF_BYPASS_INTERLACE                   BIT(13)
3313 -#define INTERLACE_FMT_DET                      BIT(12)
3314 -#define INTERLACE_DTCT_WIN                     0x20
3315 -
3316 -#define DP_FRAMER_SP_INTERLACE_EN              BIT(2)
3317 -#define DP_FRAMER_SP_HSP                       BIT(1)
3318 -#define DP_FRAMER_SP_VSP                       BIT(0)
3319 -
3320 -/* capability */
3321 -#define AUX_HOST_INVERT                                3
3322 -#define        FAST_LT_SUPPORT                         1
3323 -#define FAST_LT_NOT_SUPPORT                    0
3324 -#define LANE_MAPPING_NORMAL                    0x1b
3325 -#define LANE_MAPPING_FLIPPED                   0xe4
3326 -#define ENHANCED                               1
3327 -#define SCRAMBLER_EN                           BIT(4)
3328 -
3329 -#define        FULL_LT_STARTED                         BIT(0)
3330 -#define FASE_LT_STARTED                                BIT(1)
3331 -#define CLK_RECOVERY_FINISHED                  BIT(2)
3332 -#define EQ_PHASE_FINISHED                      BIT(3)
3333 -#define FASE_LT_START_FINISHED                 BIT(4)
3334 -#define CLK_RECOVERY_FAILED                    BIT(5)
3335 -#define EQ_PHASE_FAILED                                BIT(6)
3336 -#define FASE_LT_FAILED                         BIT(7)
3337 -
3338 -#define DPTX_HPD_EVENT                         BIT(0)
3339 -#define DPTX_TRAINING_EVENT                    BIT(1)
3340 -#define HDCP_TX_STATUS_EVENT                   BIT(4)
3341 -#define HDCP2_TX_IS_KM_STORED_EVENT            BIT(5)
3342 -#define HDCP2_TX_STORE_KM_EVENT                        BIT(6)
3343 -#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT     BIT(7)
3344 -
3345 -#define TU_SIZE                                        30
3346 -#define CDNS_DP_MAX_LINK_RATE                  DP_LINK_BW_5_4
3347 -
3348 -/* audio */
3349 -#define AUDIO_PACK_EN                          BIT(8)
3350 -#define SAMPLING_FREQ(x)                       (((x) & 0xf) << 16)
3351 -#define ORIGINAL_SAMP_FREQ(x)                  (((x) & 0xf) << 24)
3352 -#define SYNC_WR_TO_CH_ZERO                     BIT(1)
3353 -#define I2S_DEC_START                          BIT(1)
3354 -#define AUDIO_SW_RST                           BIT(0)
3355 -#define SMPL2PKT_EN                            BIT(1)
3356 -#define MAX_NUM_CH(x)                          (((x) & 0x1f) - 1)
3357 -#define NUM_OF_I2S_PORTS(x)                    ((((x) / 2 - 1) & 0x3) << 5)
3358 -#define AUDIO_TYPE_LPCM                                (2 << 7)
3359 -#define CFG_SUB_PCKT_NUM(x)                    ((((x) - 1) & 0x7) << 11)
3360 -#define AUDIO_CH_NUM(x)                                ((((x) - 1) & 0x1f) << 2)
3361 -#define TRANS_SMPL_WIDTH_16                    0
3362 -#define TRANS_SMPL_WIDTH_24                    BIT(11)
3363 -#define TRANS_SMPL_WIDTH_32                    (2 << 11)
3364 -#define I2S_DEC_PORT_EN(x)                     (((x) & 0xf) << 17)
3365 -#define SPDIF_ENABLE                           BIT(21)
3366 -#define SPDIF_AVG_SEL                          BIT(20)
3367 -#define SPDIF_JITTER_BYPASS                    BIT(19)
3368 -#define SPDIF_FIFO_MID_RANGE(x)                        (((x) & 0xff) << 11)
3369 -#define SPDIF_JITTER_THRSH(x)                  (((x) & 0xff) << 3)
3370 -#define SPDIF_JITTER_AVG_WIN(x)                        ((x) & 0x7)
3371 -
3372 -/* Reference cycles when using lane clock as reference */
3373 -#define LANE_REF_CYC                           0x8000
3374 -
3375 -enum voltage_swing_level {
3376 -       VOLTAGE_LEVEL_0,
3377 -       VOLTAGE_LEVEL_1,
3378 -       VOLTAGE_LEVEL_2,
3379 -       VOLTAGE_LEVEL_3,
3380 -};
3381 -
3382 -enum pre_emphasis_level {
3383 -       PRE_EMPHASIS_LEVEL_0,
3384 -       PRE_EMPHASIS_LEVEL_1,
3385 -       PRE_EMPHASIS_LEVEL_2,
3386 -       PRE_EMPHASIS_LEVEL_3,
3387 -};
3388 -
3389 -enum pattern_set {
3390 -       PTS1            = BIT(0),
3391 -       PTS2            = BIT(1),
3392 -       PTS3            = BIT(2),
3393 -       PTS4            = BIT(3),
3394 -       DP_NONE         = BIT(4)
3395 -};
3396 -
3397 -enum vic_color_depth {
3398 -       BCS_6 = 0x1,
3399 -       BCS_8 = 0x2,
3400 -       BCS_10 = 0x4,
3401 -       BCS_12 = 0x8,
3402 -       BCS_16 = 0x10,
3403 -};
3404 -
3405 -enum vic_bt_type {
3406 -       BT_601 = 0x0,
3407 -       BT_709 = 0x1,
3408 -};
3409 -
3410 -enum audio_format {
3411 -       AFMT_I2S = 0,
3412 -       AFMT_SPDIF = 1,
3413 -       AFMT_UNUSED,
3414 -};
3415 -
3416 -struct audio_info {
3417 -       enum audio_format format;
3418 -       int sample_rate;
3419 -       int channels;
3420 -       int sample_width;
3421 -};
3422 -
3423 -enum vic_pxl_encoding_format {
3424 -       PXL_RGB = 0x1,
3425 -       YCBCR_4_4_4 = 0x2,
3426 -       YCBCR_4_2_2 = 0x4,
3427 -       YCBCR_4_2_0 = 0x8,
3428 -       Y_ONLY = 0x10,
3429 -};
3430 -
3431 -struct video_info {
3432 -       bool h_sync_polarity;
3433 -       bool v_sync_polarity;
3434 -       bool interlaced;
3435 -       int color_depth;
3436 -       enum vic_pxl_encoding_format color_fmt;
3437 -};
3438 -
3439 -struct cdns_mhdp_host {
3440 -       unsigned int    link_rate;
3441 -       u8      lanes_cnt;
3442 -       u8      volt_swing;
3443 -       u8      pre_emphasis;
3444 -       u8      pattern_supp;
3445 -       u8      fast_link;
3446 -       u8      lane_mapping;
3447 -       u8      enhanced;
3448 -};
3449 -
3450 -struct cdns_mhdp_sink {
3451 -       unsigned int    link_rate;
3452 -       u8      lanes_cnt;
3453 -       u8      pattern_supp;
3454 -       u8      fast_link;
3455 -       u8      enhanced;
3456 -};
3457 -
3458 -struct cdns_mhdp_device {
3459 -       void __iomem            *regs;
3460 -
3461 -       struct device           *dev;
3462 -
3463 -       struct drm_dp_link      link;
3464 -       struct drm_connector    connector;
3465 -       struct clk              *spdif_clk;
3466 -       struct reset_control    *spdif_rst;
3467 -
3468 -       struct drm_dp_aux       aux;
3469 -       struct cdns_mhdp_host   host;
3470 -       struct cdns_mhdp_sink   sink;
3471 -       struct drm_bridge       bridge;
3472 -       struct phy              *phy;
3473 -       void __iomem            *dbg_regs;
3474 -
3475 -       struct video_info       video_info;
3476 -       struct drm_display_mode mode;
3477 -       unsigned int            fw_version;
3478 -};
3479 -
3480 -void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp);
3481 -void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk);
3482 -int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem,
3483 -                           u32 i_size, const u32 *d_mem, u32 d_size);
3484 -int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable);
3485 -int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, u8 lanes, bool flip);
3486 -int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp);
3487 -u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp);
3488 -int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp);
3489 -int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value);
3490 -int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
3491 -                       u32 addr, u8 *data, u16 len);
3492 -int cdns_mhdp_get_edid_block(void *mhdp, u8 *edid,
3493 -                            unsigned int block, size_t length);
3494 -int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp);
3495 -int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active);
3496 -int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp);
3497 -int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp,
3498 -                        struct audio_info *audio);
3499 -int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable);
3500 -int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp,
3501 -                          struct audio_info *audio);
3502 -#endif /* _CDN_DP_REG_H */
3503 --- /dev/null
3504 +++ b/include/drm/bridge/cdns-mhdp-cbs.h
3505 @@ -0,0 +1,29 @@
3506 +/* SPDX-License-Identifier: GPL-2.0 */
3507 +/*
3508 + * Cadence MHDP DP bridge callbacks.
3509 + *
3510 + * Copyright: 2018 Cadence Design Systems, Inc.
3511 + *
3512 + * Author: Piotr Sroka <piotrs@cadence.com>
3513 + */
3514 +
3515 +#ifndef CDNS_MHDP_CBS_H
3516 +#define CDNS_MHDP_CBS_H
3517 +
3518 +#include <drm/drm_bridge.h>
3519 +
3520 +struct cdns_mhdp_mst_cbs_funcs {
3521 +       struct drm_encoder *(*create_mst_encoder)(void *priv_data,
3522 +                                                 struct drm_bridge *bridge);
3523 +       void (*destroy_mst_encoder)(void *priv_data, struct drm_bridge *bridge);
3524 +};
3525 +
3526 +struct cdns_mhdp_mst_cbs {
3527 +       struct cdns_mhdp_mst_cbs_funcs funcs;
3528 +       void *priv_data;
3529 +};
3530 +
3531 +int mhdp_bridge_attach_mst_cbs(struct drm_bridge *bridge,
3532 +                              struct cdns_mhdp_mst_cbs *cbs);
3533 +
3534 +#endif
3535 --- /dev/null
3536 +++ b/include/drm/bridge/cdns-mhdp-common.h
3537 @@ -0,0 +1,704 @@
3538 +/* SPDX-License-Identifier: GPL-2.0 */
3539 +/*
3540 + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3541 + * Author: Chris Zhong <zyw@rock-chips.com>
3542 + *
3543 + * This software is licensed under the terms of the GNU General Public
3544 + * License version 2, as published by the Free Software Foundation, and
3545 + * may be copied, distributed, and modified under those terms.
3546 + *
3547 + * This program is distributed in the hope that it will be useful,
3548 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3549 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3550 + * GNU General Public License for more details.
3551 + */
3552 +
3553 +#ifndef CDNS_MHDP_COMMON_H_
3554 +#define CDNS_MHDP_COMMON_H_
3555 +
3556 +#include <drm/bridge/cdns-mhdp-cbs.h>
3557 +#include <drm/drm_bridge.h>
3558 +#include <drm/drm_connector.h>
3559 +#include <drm/drm_dp_helper.h>
3560 +#include <drm/drm_dp_mst_helper.h>
3561 +
3562 +#include <linux/bitops.h>
3563 +
3564 +#define ADDR_IMEM              0x10000
3565 +#define ADDR_DMEM              0x20000
3566 +#define ADDR_PHY_AFE   0x80000
3567 +
3568 +/* APB CFG addr */
3569 +#define APB_CTRL                       0
3570 +#define XT_INT_CTRL                    0x04
3571 +#define MAILBOX_FULL_ADDR              0x08
3572 +#define MAILBOX_EMPTY_ADDR             0x0c
3573 +#define MAILBOX0_WR_DATA               0x10
3574 +#define MAILBOX0_RD_DATA               0x14
3575 +#define KEEP_ALIVE                     0x18
3576 +#define VER_L                          0x1c
3577 +#define VER_H                          0x20
3578 +#define VER_LIB_L_ADDR                 0x24
3579 +#define VER_LIB_H_ADDR                 0x28
3580 +#define SW_DEBUG_L                     0x2c
3581 +#define SW_DEBUG_H                     0x30
3582 +#define MAILBOX_INT_MASK               0x34
3583 +#define MAILBOX_INT_STATUS             0x38
3584 +#define SW_CLK_L                       0x3c
3585 +#define SW_CLK_H                       0x40
3586 +#define SW_EVENTS0                     0x44
3587 +#define SW_EVENTS1                     0x48
3588 +#define SW_EVENTS2                     0x4c
3589 +#define SW_EVENTS3                     0x50
3590 +#define XT_OCD_CTRL                    0x60
3591 +#define APB_INT_MASK                   0x6c
3592 +#define APB_STATUS_MASK                        0x70
3593 +
3594 +/* audio decoder addr */
3595 +#define AUDIO_SRC_CNTL                 0x30000
3596 +#define AUDIO_SRC_CNFG                 0x30004
3597 +#define COM_CH_STTS_BITS               0x30008
3598 +#define STTS_BIT_CH(x)                 (0x3000c + ((x) << 2))
3599 +#define SPDIF_CTRL_ADDR                        0x3004c
3600 +#define SPDIF_CH1_CS_3100_ADDR         0x30050
3601 +#define SPDIF_CH1_CS_6332_ADDR         0x30054
3602 +#define SPDIF_CH1_CS_9564_ADDR         0x30058
3603 +#define SPDIF_CH1_CS_12796_ADDR                0x3005c
3604 +#define SPDIF_CH1_CS_159128_ADDR       0x30060
3605 +#define SPDIF_CH1_CS_191160_ADDR       0x30064
3606 +#define SPDIF_CH2_CS_3100_ADDR         0x30068
3607 +#define SPDIF_CH2_CS_6332_ADDR         0x3006c
3608 +#define SPDIF_CH2_CS_9564_ADDR         0x30070
3609 +#define SPDIF_CH2_CS_12796_ADDR                0x30074
3610 +#define SPDIF_CH2_CS_159128_ADDR       0x30078
3611 +#define SPDIF_CH2_CS_191160_ADDR       0x3007c
3612 +#define SMPL2PKT_CNTL                  0x30080
3613 +#define SMPL2PKT_CNFG                  0x30084
3614 +#define FIFO_CNTL                      0x30088
3615 +#define FIFO_STTS                      0x3008c
3616 +
3617 +/* source pif addr */
3618 +#define SOURCE_PIF_WR_ADDR             0x30800
3619 +#define SOURCE_PIF_WR_REQ              0x30804
3620 +#define SOURCE_PIF_RD_ADDR             0x30808
3621 +#define SOURCE_PIF_RD_REQ              0x3080c
3622 +#define SOURCE_PIF_DATA_WR             0x30810
3623 +#define SOURCE_PIF_DATA_RD             0x30814
3624 +#define SOURCE_PIF_FIFO1_FLUSH         0x30818
3625 +#define SOURCE_PIF_FIFO2_FLUSH         0x3081c
3626 +#define SOURCE_PIF_STATUS              0x30820
3627 +#define SOURCE_PIF_INTERRUPT_SOURCE    0x30824
3628 +#define SOURCE_PIF_INTERRUPT_MASK      0x30828
3629 +#define SOURCE_PIF_PKT_ALLOC_REG       0x3082c
3630 +#define SOURCE_PIF_PKT_ALLOC_WR_EN     0x30830
3631 +#define SOURCE_PIF_SW_RESET            0x30834
3632 +
3633 +/* bellow registers need access by mailbox */
3634 +/* source phy comp */
3635 +#define PHY_DATA_SEL                   0x0818
3636 +#define LANES_CONFIG                   0x0814
3637 +
3638 +/* source car addr */
3639 +#define SOURCE_HDTX_CAR                        0x0900
3640 +#define SOURCE_DPTX_CAR                        0x0904
3641 +#define SOURCE_PHY_CAR                 0x0908
3642 +#define SOURCE_CEC_CAR                 0x090c
3643 +#define SOURCE_CBUS_CAR                        0x0910
3644 +#define SOURCE_PKT_CAR                 0x0918
3645 +#define SOURCE_AIF_CAR                 0x091c
3646 +#define SOURCE_CIPHER_CAR              0x0920
3647 +#define SOURCE_CRYPTO_CAR              0x0924
3648 +
3649 +/* mhdp tx_top_comp */
3650 +#define SCHEDULER_H_SIZE               0x1000
3651 +#define SCHEDULER_V_SIZE               0x1004
3652 +#define HDTX_SIGNAL_FRONT_WIDTH        0x100c
3653 +#define HDTX_SIGNAL_SYNC_WIDTH 0x1010
3654 +#define HDTX_SIGNAL_BACK_WIDTH 0x1014
3655 +#define HDTX_CONTROLLER                        0x1018
3656 +#define HDTX_HPD                               0x1020
3657 +#define HDTX_CLOCK_REG_0               0x1024
3658 +#define HDTX_CLOCK_REG_1               0x1028
3659 +
3660 +/* clock meters addr */
3661 +#define CM_CTRL                                0x0a00
3662 +#define CM_I2S_CTRL                    0x0a04
3663 +#define CM_SPDIF_CTRL                  0x0a08
3664 +#define CM_VID_CTRL                    0x0a0c
3665 +#define CM_LANE_CTRL                   0x0a10
3666 +#define I2S_NM_STABLE                  0x0a14
3667 +#define I2S_NCTS_STABLE                        0x0a18
3668 +#define SPDIF_NM_STABLE                        0x0a1c
3669 +#define SPDIF_NCTS_STABLE              0x0a20
3670 +#define NMVID_MEAS_STABLE              0x0a24
3671 +#define I2S_MEAS                       0x0a40
3672 +#define SPDIF_MEAS                     0x0a80
3673 +#define NMVID_MEAS                     0x0ac0
3674 +
3675 +/* source vif addr */
3676 +#define BND_HSYNC2VSYNC                        0x0b00
3677 +#define HSYNC2VSYNC_F1_L1              0x0b04
3678 +#define HSYNC2VSYNC_F2_L1              0x0b08
3679 +#define HSYNC2VSYNC_STATUS             0x0b0c
3680 +#define HSYNC2VSYNC_POL_CTRL           0x0b10
3681 +
3682 +/* dptx phy addr */
3683 +#define DP_TX_PHY_CONFIG_REG           0x2000
3684 +#define DP_TX_PHY_SW_RESET             0x2004
3685 +#define DP_TX_PHY_SCRAMBLER_SEED       0x2008
3686 +#define DP_TX_PHY_TRAINING_01_04       0x200c
3687 +#define DP_TX_PHY_TRAINING_05_08       0x2010
3688 +#define DP_TX_PHY_TRAINING_09_10       0x2014
3689 +#define TEST_COR                       0x23fc
3690 +
3691 +/* dptx hpd addr */
3692 +#define HPD_IRQ_DET_MIN_TIMER          0x2100
3693 +#define HPD_IRQ_DET_MAX_TIMER          0x2104
3694 +#define HPD_UNPLGED_DET_MIN_TIMER      0x2108
3695 +#define HPD_STABLE_TIMER               0x210c
3696 +#define HPD_FILTER_TIMER               0x2110
3697 +#define HPD_EVENT_MASK                 0x211c
3698 +#define HPD_EVENT_DET                  0x2120
3699 +
3700 +/* dpyx framer addr */
3701 +#define DP_FRAMER_GLOBAL_CONFIG                0x2200
3702 +#define DP_SW_RESET                    0x2204
3703 +#define DP_FRAMER_TU                   0x2208
3704 +#define DP_FRAMER_PXL_REPR             0x220c
3705 +#define DP_FRAMER_SP                   0x2210
3706 +#define AUDIO_PACK_CONTROL             0x2214
3707 +#define DP_VC_TABLE(x)                 (0x2218 + ((x) << 2))
3708 +#define DP_VB_ID                       0x2258
3709 +#define DP_MTPH_LVP_CONTROL            0x225c
3710 +#define DP_MTPH_SYMBOL_VALUES          0x2260
3711 +#define DP_MTPH_ECF_CONTROL            0x2264
3712 +#define DP_MTPH_ACT_CONTROL            0x2268
3713 +#define DP_MTPH_STATUS                 0x226c
3714 +#define DP_INTERRUPT_SOURCE            0x2270
3715 +#define DP_INTERRUPT_MASK              0x2274
3716 +#define DP_FRONT_BACK_PORCH            0x2278
3717 +#define DP_BYTE_COUNT                  0x227c
3718 +
3719 +/* dptx stream addr */
3720 +#define MSA_HORIZONTAL_0               0x2280
3721 +#define MSA_HORIZONTAL_1               0x2284
3722 +#define MSA_VERTICAL_0                 0x2288
3723 +#define MSA_VERTICAL_1                 0x228c
3724 +#define MSA_MISC                       0x2290
3725 +#define STREAM_CONFIG                  0x2294
3726 +#define AUDIO_PACK_STATUS              0x2298
3727 +#define VIF_STATUS                     0x229c
3728 +#define PCK_STUFF_STATUS_0             0x22a0
3729 +#define PCK_STUFF_STATUS_1             0x22a4
3730 +#define INFO_PACK_STATUS               0x22a8
3731 +#define RATE_GOVERNOR_STATUS           0x22ac
3732 +#define DP_HORIZONTAL                  0x22b0
3733 +#define DP_VERTICAL_0                  0x22b4
3734 +#define DP_VERTICAL_1                  0x22b8
3735 +#define DP_BLOCK_SDP                   0x22bc
3736 +
3737 +/* dptx glbl addr */
3738 +#define DPTX_LANE_EN                   0x2300
3739 +#define DPTX_ENHNCD                    0x2304
3740 +#define DPTX_INT_MASK                  0x2308
3741 +#define DPTX_INT_STATUS                        0x230c
3742 +
3743 +/* dp aux addr */
3744 +#define DP_AUX_HOST_CONTROL            0x2800
3745 +#define DP_AUX_INTERRUPT_SOURCE                0x2804
3746 +#define DP_AUX_INTERRUPT_MASK          0x2808
3747 +#define DP_AUX_SWAP_INVERSION_CONTROL  0x280c
3748 +#define DP_AUX_SEND_NACK_TRANSACTION   0x2810
3749 +#define DP_AUX_CLEAR_RX                        0x2814
3750 +#define DP_AUX_CLEAR_TX                        0x2818
3751 +#define DP_AUX_TIMER_STOP              0x281c
3752 +#define DP_AUX_TIMER_CLEAR             0x2820
3753 +#define DP_AUX_RESET_SW                        0x2824
3754 +#define DP_AUX_DIVIDE_2M               0x2828
3755 +#define DP_AUX_TX_PREACHARGE_LENGTH    0x282c
3756 +#define DP_AUX_FREQUENCY_1M_MAX                0x2830
3757 +#define DP_AUX_FREQUENCY_1M_MIN                0x2834
3758 +#define DP_AUX_RX_PRE_MIN              0x2838
3759 +#define DP_AUX_RX_PRE_MAX              0x283c
3760 +#define DP_AUX_TIMER_PRESET            0x2840
3761 +#define DP_AUX_NACK_FORMAT             0x2844
3762 +#define DP_AUX_TX_DATA                 0x2848
3763 +#define DP_AUX_RX_DATA                 0x284c
3764 +#define DP_AUX_TX_STATUS               0x2850
3765 +#define DP_AUX_RX_STATUS               0x2854
3766 +#define DP_AUX_RX_CYCLE_COUNTER                0x2858
3767 +#define DP_AUX_MAIN_STATES             0x285c
3768 +#define DP_AUX_MAIN_TIMER              0x2860
3769 +#define DP_AUX_AFE_OUT                 0x2864
3770 +
3771 +/* crypto addr */
3772 +#define CRYPTO_HDCP_REVISION           0x5800
3773 +#define HDCP_CRYPTO_CONFIG             0x5804
3774 +#define CRYPTO_INTERRUPT_SOURCE                0x5808
3775 +#define CRYPTO_INTERRUPT_MASK          0x580c
3776 +#define CRYPTO22_CONFIG                        0x5818
3777 +#define CRYPTO22_STATUS                        0x581c
3778 +#define SHA_256_DATA_IN                        0x583c
3779 +#define SHA_256_DATA_OUT_(x)           (0x5850 + ((x) << 2))
3780 +#define AES_32_KEY_(x)                 (0x5870 + ((x) << 2))
3781 +#define AES_32_DATA_IN                 0x5880
3782 +#define AES_32_DATA_OUT_(x)            (0x5884 + ((x) << 2))
3783 +#define CRYPTO14_CONFIG                        0x58a0
3784 +#define CRYPTO14_STATUS                        0x58a4
3785 +#define CRYPTO14_PRNM_OUT              0x58a8
3786 +#define CRYPTO14_KM_0                  0x58ac
3787 +#define CRYPTO14_KM_1                  0x58b0
3788 +#define CRYPTO14_AN_0                  0x58b4
3789 +#define CRYPTO14_AN_1                  0x58b8
3790 +#define CRYPTO14_YOUR_KSV_0            0x58bc
3791 +#define CRYPTO14_YOUR_KSV_1            0x58c0
3792 +#define CRYPTO14_MI_0                  0x58c4
3793 +#define CRYPTO14_MI_1                  0x58c8
3794 +#define CRYPTO14_TI_0                  0x58cc
3795 +#define CRYPTO14_KI_0                  0x58d0
3796 +#define CRYPTO14_KI_1                  0x58d4
3797 +#define CRYPTO14_BLOCKS_NUM            0x58d8
3798 +#define CRYPTO14_KEY_MEM_DATA_0                0x58dc
3799 +#define CRYPTO14_KEY_MEM_DATA_1                0x58e0
3800 +#define CRYPTO14_SHA1_MSG_DATA         0x58e4
3801 +#define CRYPTO14_SHA1_V_VALUE_(x)      (0x58e8 + ((x) << 2))
3802 +#define TRNG_CTRL                      0x58fc
3803 +#define TRNG_DATA_RDY                  0x5900
3804 +#define TRNG_DATA                      0x5904
3805 +
3806 +/* cipher addr */
3807 +#define HDCP_REVISION                  0x60000
3808 +#define INTERRUPT_SOURCE               0x60004
3809 +#define INTERRUPT_MASK                 0x60008
3810 +#define HDCP_CIPHER_CONFIG             0x6000c
3811 +#define AES_128_KEY_0                  0x60010
3812 +#define AES_128_KEY_1                  0x60014
3813 +#define AES_128_KEY_2                  0x60018
3814 +#define AES_128_KEY_3                  0x6001c
3815 +#define AES_128_RANDOM_0               0x60020
3816 +#define AES_128_RANDOM_1               0x60024
3817 +#define CIPHER14_KM_0                  0x60028
3818 +#define CIPHER14_KM_1                  0x6002c
3819 +#define CIPHER14_STATUS                        0x60030
3820 +#define CIPHER14_RI_PJ_STATUS          0x60034
3821 +#define CIPHER_MODE                    0x60038
3822 +#define CIPHER14_AN_0                  0x6003c
3823 +#define CIPHER14_AN_1                  0x60040
3824 +#define CIPHER22_AUTH                  0x60044
3825 +#define CIPHER14_R0_DP_STATUS          0x60048
3826 +#define CIPHER14_BOOTSTRAP             0x6004c
3827 +
3828 +#define DPTX_FRMR_DATA_CLK_RSTN_EN     BIT(11)
3829 +#define DPTX_FRMR_DATA_CLK_EN          BIT(10)
3830 +#define DPTX_PHY_DATA_RSTN_EN          BIT(9)
3831 +#define DPTX_PHY_DATA_CLK_EN           BIT(8)
3832 +#define DPTX_PHY_CHAR_RSTN_EN          BIT(7)
3833 +#define DPTX_PHY_CHAR_CLK_EN           BIT(6)
3834 +#define SOURCE_AUX_SYS_CLK_RSTN_EN     BIT(5)
3835 +#define SOURCE_AUX_SYS_CLK_EN          BIT(4)
3836 +#define DPTX_SYS_CLK_RSTN_EN           BIT(3)
3837 +#define DPTX_SYS_CLK_EN                        BIT(2)
3838 +#define CFG_DPTX_VIF_CLK_RSTN_EN       BIT(1)
3839 +#define CFG_DPTX_VIF_CLK_EN            BIT(0)
3840 +
3841 +#define SOURCE_PHY_RSTN_EN             BIT(1)
3842 +#define SOURCE_PHY_CLK_EN              BIT(0)
3843 +
3844 +#define SOURCE_PKT_SYS_RSTN_EN         BIT(3)
3845 +#define SOURCE_PKT_SYS_CLK_EN          BIT(2)
3846 +#define SOURCE_PKT_DATA_RSTN_EN                BIT(1)
3847 +#define SOURCE_PKT_DATA_CLK_EN         BIT(0)
3848 +
3849 +#define SPDIF_CDR_CLK_RSTN_EN          BIT(5)
3850 +#define SPDIF_CDR_CLK_EN               BIT(4)
3851 +#define SOURCE_AIF_SYS_RSTN_EN         BIT(3)
3852 +#define SOURCE_AIF_SYS_CLK_EN          BIT(2)
3853 +#define SOURCE_AIF_CLK_RSTN_EN         BIT(1)
3854 +#define SOURCE_AIF_CLK_EN              BIT(0)
3855 +
3856 +#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN       BIT(3)
3857 +#define SOURCE_CIPHER_SYS_CLK_EN               BIT(2)
3858 +#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN         BIT(1)
3859 +#define SOURCE_CIPHER_CHAR_CLK_EN              BIT(0)
3860 +
3861 +#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN  BIT(1)
3862 +#define SOURCE_CRYPTO_SYS_CLK_EN       BIT(0)
3863 +
3864 +#define APB_IRAM_PATH                  BIT(2)
3865 +#define APB_DRAM_PATH                  BIT(1)
3866 +#define APB_XT_RESET                   BIT(0)
3867 +
3868 +#define MAILBOX_INT_MASK_BIT           BIT(1)
3869 +#define PIF_INT_MASK_BIT               BIT(0)
3870 +#define ALL_INT_MASK                   3
3871 +
3872 +/* mailbox */
3873 +#define MB_OPCODE_ID                   0
3874 +#define MB_MODULE_ID                   1
3875 +#define MB_SIZE_MSB_ID                 2
3876 +#define MB_SIZE_LSB_ID                 3
3877 +#define MB_DATA_ID                     4
3878 +
3879 +#define MB_MODULE_ID_DP_TX                     0x01
3880 +#define MB_MODULE_ID_HDMI_TX           0x03
3881 +#define MB_MODULE_ID_HDCP_TX           0x07
3882 +#define MB_MODULE_ID_HDCP_RX           0x08
3883 +#define MB_MODULE_ID_HDCP_GENERAL      0x09
3884 +#define MB_MODULE_ID_GENERAL           0x0A
3885 +
3886 +/* general opcode */
3887 +#define GENERAL_MAIN_CONTROL            0x01
3888 +#define GENERAL_TEST_ECHO               0x02
3889 +#define GENERAL_BUS_SETTINGS            0x03
3890 +#define GENERAL_TEST_ACCESS             0x04
3891 +#define GENERAL_WRITE_REGISTER          0x05
3892 +#define GENERAL_WRITE_FIELD             0x06
3893 +#define GENERAL_READ_REGISTER           0x07
3894 +#define GENERAL_GET_HPD_STATE           0x11
3895 +
3896 +/* DPTX opcode */
3897 +#define DPTX_SET_POWER_MNG                     0x00
3898 +#define DPTX_SET_HOST_CAPABILITIES             0x01
3899 +#define DPTX_GET_EDID                          0x02
3900 +#define DPTX_READ_DPCD                         0x03
3901 +#define DPTX_WRITE_DPCD                                0x04
3902 +#define DPTX_ENABLE_EVENT                      0x05
3903 +#define DPTX_WRITE_REGISTER                    0x06
3904 +#define DPTX_READ_REGISTER                     0x07
3905 +#define DPTX_WRITE_FIELD                       0x08
3906 +#define DPTX_TRAINING_CONTROL                  0x09
3907 +#define DPTX_READ_EVENT                                0x0a
3908 +#define DPTX_READ_LINK_STAT                    0x0b
3909 +#define DPTX_SET_VIDEO                         0x0c
3910 +#define DPTX_SET_AUDIO                         0x0d
3911 +#define DPTX_GET_LAST_AUX_STAUS                        0x0e
3912 +#define DPTX_SET_LINK_BREAK_POINT              0x0f
3913 +#define DPTX_FORCE_LANES                       0x10
3914 +#define DPTX_HPD_STATE                         0x11
3915 +#define DPTX_ADJUST_LT                         0x12
3916 +
3917 +/* HDMI TX opcode */
3918 +#define HDMI_TX_READ                           0x00
3919 +#define HDMI_TX_WRITE                          0x01
3920 +#define HDMI_TX_UPDATE_READ                    0x02
3921 +#define HDMI_TX_EDID                           0x03
3922 +#define HDMI_TX_EVENTS                         0x04
3923 +#define HDMI_TX_HPD_STATUS                     0x05
3924 +#define HDMI_TX_DEBUG_ECHO                     0xAA
3925 +#define HDMI_TX_TEST                           0xBB
3926 +#define HDMI_TX_EDID_INTERNAL          0xF0
3927 +
3928 +#define FW_STANDBY                             0
3929 +#define FW_ACTIVE                              1
3930 +
3931 +#define DPTX_EVENT_ENABLE_HPD                  BIT(0)
3932 +#define DPTX_EVENT_ENABLE_TRAINING             BIT(1)
3933 +
3934 +#define LINK_TRAINING_NOT_ACTIVE               0
3935 +#define LINK_TRAINING_RUN                      1
3936 +#define LINK_TRAINING_RESTART                  2
3937 +
3938 +#define CONTROL_VIDEO_IDLE                     0
3939 +#define CONTROL_VIDEO_VALID                    1
3940 +
3941 +#define TU_CNT_RST_EN                          BIT(15)
3942 +#define VIF_BYPASS_INTERLACE                   BIT(13)
3943 +#define INTERLACE_FMT_DET                      BIT(12)
3944 +#define INTERLACE_DTCT_WIN                     0x20
3945 +
3946 +#define DP_FRAMER_SP_INTERLACE_EN              BIT(2)
3947 +#define DP_FRAMER_SP_HSP                       BIT(1)
3948 +#define DP_FRAMER_SP_VSP                       BIT(0)
3949 +
3950 +/* capability */
3951 +#define AUX_HOST_INVERT                                3
3952 +#define        FAST_LT_SUPPORT                         1
3953 +#define FAST_LT_NOT_SUPPORT                    0
3954 +#define LANE_MAPPING_NORMAL                    0x1b
3955 +#define LANE_MAPPING_FLIPPED                   0xe4
3956 +#define ENHANCED                               1
3957 +#define SCRAMBLER_EN                           BIT(4)
3958 +
3959 +#define        FULL_LT_STARTED                         BIT(0)
3960 +#define FASE_LT_STARTED                                BIT(1)
3961 +#define CLK_RECOVERY_FINISHED                  BIT(2)
3962 +#define EQ_PHASE_FINISHED                      BIT(3)
3963 +#define FASE_LT_START_FINISHED                 BIT(4)
3964 +#define CLK_RECOVERY_FAILED                    BIT(5)
3965 +#define EQ_PHASE_FAILED                                BIT(6)
3966 +#define FASE_LT_FAILED                         BIT(7)
3967 +
3968 +#define DPTX_HPD_EVENT                         BIT(0)
3969 +#define DPTX_TRAINING_EVENT                    BIT(1)
3970 +#define HDCP_TX_STATUS_EVENT                   BIT(4)
3971 +#define HDCP2_TX_IS_KM_STORED_EVENT            BIT(5)
3972 +#define HDCP2_TX_STORE_KM_EVENT                        BIT(6)
3973 +#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT     BIT(7)
3974 +
3975 +#define TU_SIZE                                        30
3976 +#define CDNS_DP_MAX_LINK_RATE                  DP_LINK_BW_5_4
3977 +
3978 +#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
3979 +#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
3980 +#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
3981 +#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12)
3982 +#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15)
3983 +#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18)
3984 +#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7)
3985 +#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11)
3986 +#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3)
3987 +#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0)
3988 +#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12)
3989 +#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19)
3990 +#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0)
3991 +#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2)
3992 +#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4)
3993 +#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6)
3994 +#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21)
3995 +#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22)
3996 +#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
3997 +#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17)
3998 +#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
3999 +#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0)
4000 +#define F_DATA_WR(x) (x)
4001 +#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
4002 +#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0)
4003 +#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16)
4004 +#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8)
4005 +
4006 +/* audio */
4007 +#define AUDIO_PACK_EN                          BIT(8)
4008 +#define SAMPLING_FREQ(x)                       (((x) & 0xf) << 16)
4009 +#define ORIGINAL_SAMP_FREQ(x)                  (((x) & 0xf) << 24)
4010 +#define SYNC_WR_TO_CH_ZERO                     BIT(1)
4011 +#define I2S_DEC_START                          BIT(1)
4012 +#define AUDIO_SW_RST                           BIT(0)
4013 +#define SMPL2PKT_EN                            BIT(1)
4014 +#define MAX_NUM_CH(x)                          (((x) & 0x1f) - 1)
4015 +#define NUM_OF_I2S_PORTS(x)                    ((((x) / 2 - 1) & 0x3) << 5)
4016 +#define AUDIO_TYPE_LPCM                                (2 << 7)
4017 +#define CFG_SUB_PCKT_NUM(x)                    ((((x) - 1) & 0x7) << 11)
4018 +#define AUDIO_CH_NUM(x)                                ((((x) - 1) & 0x1f) << 2)
4019 +#define TRANS_SMPL_WIDTH_16                    0
4020 +#define TRANS_SMPL_WIDTH_24                    BIT(11)
4021 +#define TRANS_SMPL_WIDTH_32                    (2 << 11)
4022 +#define I2S_DEC_PORT_EN(x)                     (((x) & 0xf) << 17)
4023 +#define SPDIF_ENABLE                           BIT(21)
4024 +#define SPDIF_AVG_SEL                          BIT(20)
4025 +#define SPDIF_JITTER_BYPASS                    BIT(19)
4026 +#define SPDIF_FIFO_MID_RANGE(x)                        (((x) & 0xff) << 11)
4027 +#define SPDIF_JITTER_THRSH(x)                  (((x) & 0xff) << 3)
4028 +#define SPDIF_JITTER_AVG_WIN(x)                        ((x) & 0x7)
4029 +
4030 +/* Reference cycles when using lane clock as reference */
4031 +#define LANE_REF_CYC                           0x8000
4032 +
4033 +#define HOTPLUG_DEBOUNCE_MS            200
4034 +
4035 +enum voltage_swing_level {
4036 +       VOLTAGE_LEVEL_0,
4037 +       VOLTAGE_LEVEL_1,
4038 +       VOLTAGE_LEVEL_2,
4039 +       VOLTAGE_LEVEL_3,
4040 +};
4041 +
4042 +enum pre_emphasis_level {
4043 +       PRE_EMPHASIS_LEVEL_0,
4044 +       PRE_EMPHASIS_LEVEL_1,
4045 +       PRE_EMPHASIS_LEVEL_2,
4046 +       PRE_EMPHASIS_LEVEL_3,
4047 +};
4048 +
4049 +enum pattern_set {
4050 +       PTS1            = BIT(0),
4051 +       PTS2            = BIT(1),
4052 +       PTS3            = BIT(2),
4053 +       PTS4            = BIT(3),
4054 +       DP_NONE         = BIT(4)
4055 +};
4056 +
4057 +enum vic_color_depth {
4058 +       BCS_6 = 0x1,
4059 +       BCS_8 = 0x2,
4060 +       BCS_10 = 0x4,
4061 +       BCS_12 = 0x8,
4062 +       BCS_16 = 0x10,
4063 +};
4064 +
4065 +enum vic_bt_type {
4066 +       BT_601 = 0x0,
4067 +       BT_709 = 0x1,
4068 +};
4069 +
4070 +enum audio_format {
4071 +       AFMT_I2S = 0,
4072 +       AFMT_SPDIF = 1,
4073 +       AFMT_UNUSED,
4074 +};
4075 +
4076 +enum {
4077 +       MODE_DVI,
4078 +       MODE_HDMI_1_4,
4079 +       MODE_HDMI_2_0,
4080 +};
4081 +
4082 +struct audio_info {
4083 +       enum audio_format format;
4084 +       int sample_rate;
4085 +       int channels;
4086 +       int sample_width;
4087 +};
4088 +
4089 +enum vic_pxl_encoding_format {
4090 +       PXL_RGB = 0x1,
4091 +       YCBCR_4_4_4 = 0x2,
4092 +       YCBCR_4_2_2 = 0x4,
4093 +       YCBCR_4_2_0 = 0x8,
4094 +       Y_ONLY = 0x10,
4095 +};
4096 +
4097 +struct video_info {
4098 +       bool h_sync_polarity;
4099 +       bool v_sync_polarity;
4100 +       bool interlaced;
4101 +       int color_depth;
4102 +       enum vic_pxl_encoding_format color_fmt;
4103 +};
4104 +
4105 +struct cdns_mhdp_host {
4106 +       unsigned int    link_rate;
4107 +       u8      lanes_cnt;
4108 +       u8      volt_swing;
4109 +       u8      pre_emphasis;
4110 +       u8      pattern_supp;
4111 +       u8      fast_link;
4112 +       u8      lane_mapping;
4113 +       u8      enhanced;
4114 +};
4115 +
4116 +struct cdns_mhdp_sink {
4117 +       unsigned int    link_rate;
4118 +       u8      lanes_cnt;
4119 +       u8      pattern_supp;
4120 +       u8      fast_link;
4121 +       u8      enhanced;
4122 +};
4123 +
4124 +struct cdns_mhdp_bridge;
4125 +struct cdns_mhdp_connector;
4126 +
4127 +struct cdns_mhdp_bridge {
4128 +       struct cdns_mhdp_device *mhdp;
4129 +       struct drm_bridge base;
4130 +       int pbn;
4131 +       int8_t stream_id;
4132 +       struct cdns_mhdp_connector *connector;
4133 +       bool is_active;
4134 +};
4135 +
4136 +struct cdns_mhdp_connector {
4137 +       struct drm_connector base;
4138 +       bool is_mst_connector;
4139 +       struct drm_dp_mst_port *port;
4140 +       struct cdns_mhdp_bridge *bridge;
4141 +};
4142 +
4143 +struct cdns_mhdp_device {
4144 +       void __iomem            *regs;
4145 +
4146 +       struct device           *dev;
4147 +
4148 +       struct cdns_mhdp_connector  connector;
4149 +       struct clk              *spdif_clk;
4150 +       struct reset_control    *spdif_rst;
4151 +
4152 +       struct platform_device  *audio_pdev;
4153 +       struct audio_info       audio_info;
4154 +
4155 +       struct cdns_mhdp_bridge bridge;
4156 +       struct phy              *phy;
4157 +
4158 +       struct video_info       video_info;
4159 +       struct drm_display_mode mode;
4160 +       unsigned int            fw_version;
4161 +
4162 +       struct drm_dp_mst_topology_mgr mst_mgr;
4163 +       struct delayed_work hotplug_work;
4164 +
4165 +       bool link_up;
4166 +       bool power_up;
4167 +       bool plugged;
4168 +
4169 +       union {
4170 +               struct _dp_data {
4171 +                       struct drm_dp_link      link;
4172 +                       struct drm_dp_aux       aux;
4173 +                       struct cdns_mhdp_host   host;
4174 +                       struct cdns_mhdp_sink   sink;
4175 +                       struct cdns_mhdp_mst_cbs cbs;
4176 +                       bool is_mst;
4177 +                       bool can_mst;
4178 +                       u32 lane_mapping;
4179 +                       u32 link_rate;
4180 +                       u32 num_lanes;
4181 +               } dp;
4182 +               struct _hdmi_data {
4183 +                       u32 char_rate;
4184 +                       u32 hdmi_type;
4185 +               } hdmi;
4186 +       };
4187 +};
4188 +
4189 +void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp);
4190 +void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk);
4191 +int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem,
4192 +                           u32 i_size, const u32 *d_mem, u32 d_size);
4193 +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable);
4194 +int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, u8 lanes, bool flip);
4195 +int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp);
4196 +u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp);
4197 +int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp);
4198 +int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value);
4199 +int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
4200 +                       u32 addr, u8 *data, u16 len);
4201 +int cdns_mhdp_get_edid_block(void *mhdp, u8 *edid,
4202 +                            unsigned int block, size_t length);
4203 +int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp);
4204 +int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active);
4205 +int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp);
4206 +int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp,
4207 +                        struct audio_info *audio);
4208 +int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable);
4209 +int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp,
4210 +                          struct audio_info *audio);
4211 +int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr);
4212 +int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val);
4213 +int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
4214 +                           u8 start_bit, u8 bits_no, u32 val);
4215 +int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp, u8 nlanes,
4216 +                       u16 udelay, u8 *lanes_data,
4217 +                       u8 *dpcd);
4218 +
4219 +int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp);
4220 +u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr);
4221 +int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val);
4222 +int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id,
4223 +                                 u8 opcode, u16 size, u8 *message);
4224 +int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp,
4225 +                                         u8 *buff, u16 buff_size);
4226 +int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
4227 +                                             u8 module_id, u8 opcode,
4228 +                                             u16 req_size);
4229 +int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp);
4230 +
4231 +int cdns_hdmi_get_edid_block(void *data, u8 *edid, u32 block, size_t length);
4232 +int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data);
4233 +int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value);
4234 +int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, int protocol, u32 char_rate);
4235 +int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, struct drm_display_mode *mode,
4236 +                               struct video_info *video_info);
4237 +int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp);
4238 +int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp);
4239 +
4240 +bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp);
4241 +#endif /* CDNS_MHDP_COMMON_H_ */