target/linux/layerscape/patches-5.4/804-crypto-0041-LF-292-2-crypto-caam-add-power-management.patch

   1 From e8aeb8bbd925b50555c70ad4be86cf7d8e8767a6 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
   3 Date: Fri, 21 Feb 2020 11:48:40 +0100
   4 Subject: [PATCH] LF-292-2 crypto: caam - add power management
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Add support for suspend and resume operation for PM in CAAM driver.
  10
  11 When the CAAM goes in suspend, the hardware is considered to do nothing.
  12
  13 On some platforms, the power of the CAAM is not turned off so it keeps
  14 its configuration.
  15
  16 On other platforms, it doesn't so it is necessary to save the state of
  17 the CAAM:
  18  - JRs MID
  19  - Address of input and output rings
  20
  21 Limitation:
  22 When the CAAM is powered OFF, it is resetted so the JDKEK and TDKEK
  23 changes. This impacts crypto transforms using MDHA split-keys
  24 which are kept over suspend as they are encrypted with the JDKEK:
  25  - hmac(*) from caamhash.c
  26  - authenc(hmac(*),*) from caamalg.c
  27  - echainiv(authenc(hmac(*),*)) from caamalg.c
  28 The issue was already present in current code so this patch does not
  29 add a regression in this regard.
  30
  31 Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
  32 Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
  33 (cherry picked from commit c151af80cfda82eae533a80fb2bb0158dffe556d)
  34
  35 Differences vs. i.MX BSP:
  36 -RNG re-initialization done in ctrl, not in jr
  37
  38 The fix for MLK-22518 (drivers: crypto: caam: jr: Allow quiesce when quiesced)
  39 is integrated in this patch.
  40
  41 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
  42 Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
  43 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
  44 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
  45 ---
  46  drivers/crypto/caam/ctrl.c   | 116 +++++++++++++++++++++++
  47  drivers/crypto/caam/intern.h |  31 ++++++
  48  drivers/crypto/caam/jr.c     | 219 ++++++++++++++++++++++++++++++++++++-------
  49  drivers/crypto/caam/regs.h   |   3 +-
  50  4 files changed, 333 insertions(+), 36 deletions(-)
  51
  52 --- a/drivers/crypto/caam/ctrl.c
  53 +++ b/drivers/crypto/caam/ctrl.c
  54 @@ -665,6 +665,115 @@ static int caam_ctrl_rng_init(struct dev
  55         return 0;
  56  }
  57
  58 +#ifdef CONFIG_PM_SLEEP
  59 +
  60 +/* Indicate if the internal state of the CAAM is lost during PM */
  61 +static int caam_off_during_pm(void)
  62 +{
  63 +       bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") ||
  64 +                                of_machine_is_compatible("fsl,imx6qp") ||
  65 +                                of_machine_is_compatible("fsl,imx6dl");
  66 +
  67 +       return not_off_during_pm ? 0 : 1;
  68 +}
  69 +
  70 +static void caam_state_save(struct device *dev)
  71 +{
  72 +       struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
  73 +       struct caam_ctl_state *state = &ctrlpriv->state;
  74 +       struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
  75 +       u32 deco_inst, jr_inst;
  76 +       int i;
  77 +
  78 +       state->mcr = rd_reg32(&ctrl->mcr);
  79 +       state->scfgr = rd_reg32(&ctrl->scfgr);
  80 +
  81 +       deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
  82 +                    CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
  83 +       for (i = 0; i < deco_inst; i++) {
  84 +               state->deco_mid[i].liodn_ms =
  85 +                       rd_reg32(&ctrl->deco_mid[i].liodn_ms);
  86 +               state->deco_mid[i].liodn_ls =
  87 +                       rd_reg32(&ctrl->deco_mid[i].liodn_ls);
  88 +       }
  89 +
  90 +       jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
  91 +                  CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
  92 +       for (i = 0; i < jr_inst; i++) {
  93 +               state->jr_mid[i].liodn_ms =
  94 +                       rd_reg32(&ctrl->jr_mid[i].liodn_ms);
  95 +               state->jr_mid[i].liodn_ls =
  96 +                       rd_reg32(&ctrl->jr_mid[i].liodn_ls);
  97 +       }
  98 +}
  99 +
 100 +static void caam_state_restore(const struct device *dev)
 101 +{
 102 +       const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
 103 +       const struct caam_ctl_state *state = &ctrlpriv->state;
 104 +       struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 105 +       u32 deco_inst, jr_inst;
 106 +       int i;
 107 +
 108 +       wr_reg32(&ctrl->mcr, state->mcr);
 109 +       wr_reg32(&ctrl->scfgr, state->scfgr);
 110 +
 111 +       deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
 112 +                    CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
 113 +       for (i = 0; i < deco_inst; i++) {
 114 +               wr_reg32(&ctrl->deco_mid[i].liodn_ms,
 115 +                        state->deco_mid[i].liodn_ms);
 116 +               wr_reg32(&ctrl->deco_mid[i].liodn_ls,
 117 +                        state->deco_mid[i].liodn_ls);
 118 +       }
 119 +
 120 +       jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
 121 +                  CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
 122 +       for (i = 0; i < ctrlpriv->total_jobrs; i++) {
 123 +               wr_reg32(&ctrl->jr_mid[i].liodn_ms,
 124 +                        state->jr_mid[i].liodn_ms);
 125 +               wr_reg32(&ctrl->jr_mid[i].liodn_ls,
 126 +                        state->jr_mid[i].liodn_ls);
 127 +       }
 128 +
 129 +       if (ctrlpriv->virt_en == 1)
 130 +               clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 131 +                             JRSTART_JR1_START | JRSTART_JR2_START |
 132 +                             JRSTART_JR3_START);
 133 +}
 134 +
 135 +static int caam_ctrl_suspend(struct device *dev)
 136 +{
 137 +       const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
 138 +
 139 +       if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en &&
 140 +           !ctrlpriv->optee_en)
 141 +               caam_state_save(dev);
 142 +
 143 +       return 0;
 144 +}
 145 +
 146 +static int caam_ctrl_resume(struct device *dev)
 147 +{
 148 +       struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
 149 +       int ret = 0;
 150 +
 151 +       if (ctrlpriv->caam_off_during_pm && !ctrlpriv->scu_en &&
 152 +           !ctrlpriv->optee_en) {
 153 +               caam_state_restore(dev);
 154 +
 155 +               /* HW and rng will be reset so deinstantiation can be removed */
 156 +               devm_remove_action(dev, devm_deinstantiate_rng, dev);
 157 +               ret = caam_ctrl_rng_init(dev);
 158 +       }
 159 +
 160 +       return ret;
 161 +}
 162 +
 163 +SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume);
 164 +
 165 +#endif /* CONFIG_PM_SLEEP */
 166 +
 167  /* Probe routine for CAAM top (controller) level */
 168  static int caam_probe(struct platform_device *pdev)
 169  {
 170 @@ -701,6 +810,10 @@ static int caam_probe(struct platform_de
 171         imx_soc_match = soc_device_match(caam_imx_soc_table);
 172         caam_imx = (bool)imx_soc_match;
 173
 174 +#ifdef CONFIG_PM_SLEEP
 175 +       ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm();
 176 +#endif
 177 +
 178         if (imx_soc_match) {
 179                 np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu");
 180                 ctrlpriv->scu_en = !!np;
 181 @@ -1049,6 +1162,9 @@ static struct platform_driver caam_drive
 182         .driver = {
 183                 .name = "caam",
 184                 .of_match_table = caam_match,
 185 +#ifdef CONFIG_PM_SLEEP
 186 +               .pm = &caam_ctrl_pm_ops,
 187 +#endif
 188         },
 189         .probe       = caam_probe,
 190  };
 191 --- a/drivers/crypto/caam/intern.h
 192 +++ b/drivers/crypto/caam/intern.h
 193 @@ -38,6 +38,18 @@ struct caam_jrentry_info {
 194         u32 desc_size;  /* Stored size for postprocessing, header derived */
 195  };
 196
 197 +#ifdef CONFIG_PM_SLEEP
 198 +struct caam_jr_state {
 199 +       dma_addr_t inpbusaddr;
 200 +       dma_addr_t outbusaddr;
 201 +};
 202 +#endif
 203 +
 204 +struct caam_jr_dequeue_params {
 205 +       struct device *dev;
 206 +       int enable_itr;
 207 +};
 208 +
 209  /* Private sub-storage for a single JobR */
 210  struct caam_drv_private_jr {
 211         struct list_head        list_node;      /* Job Ring device list */
 212 @@ -45,6 +57,7 @@ struct caam_drv_private_jr {
 213         int ridx;
 214         struct caam_job_ring __iomem *rregs;    /* JobR's register space */
 215         struct tasklet_struct irqtask;
 216 +       struct caam_jr_dequeue_params tasklet_params;
 217         int irq;                        /* One per queue */
 218
 219         /* Number of scatterlist crypt transforms active on the JobR */
 220 @@ -60,7 +73,20 @@ struct caam_drv_private_jr {
 221         int out_ring_read_index;        /* Output index "tail" */
 222         int tail;                       /* entinfo (s/w ring) tail index */
 223         void *outring;                  /* Base of output ring, DMA-safe */
 224 +
 225 +#ifdef CONFIG_PM_SLEEP
 226 +       struct caam_jr_state state;     /* State of the JR during PM */
 227 +#endif
 228 +};
 229 +
 230 +#ifdef CONFIG_PM_SLEEP
 231 +struct caam_ctl_state {
 232 +       struct masterid deco_mid[16];
 233 +       struct masterid jr_mid[4];
 234 +       u32 mcr;
 235 +       u32 scfgr;
 236  };
 237 +#endif
 238
 239  /*
 240   * Driver-private storage for a single CAAM block instance
 241 @@ -109,6 +135,11 @@ struct caam_drv_private {
 242         struct dentry *ctl; /* controller dir */
 243         struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
 244  #endif
 245 +
 246 +#ifdef CONFIG_PM_SLEEP
 247 +       int caam_off_during_pm;         /* If the CAAM is reset after suspend */
 248 +       struct caam_ctl_state state;    /* State of the CTL during PM */
 249 +#endif
 250  };
 251
 252  #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API
 253 --- a/drivers/crypto/caam/jr.c
 254 +++ b/drivers/crypto/caam/jr.c
 255 @@ -72,19 +72,27 @@ int caam_jr_driver_probed(void)
 256  }
 257  EXPORT_SYMBOL(caam_jr_driver_probed);
 258
 259 -static int caam_reset_hw_jr(struct device *dev)
 260 +/*
 261 + * Put the CAAM in quiesce, ie stop
 262 + *
 263 + * Must be called with itr disabled
 264 + */
 265 +static int caam_jr_stop_processing(struct device *dev, u32 jrcr_bits)
 266  {
 267         struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
 268         unsigned int timeout = 100000;
 269
 270 -       /*
 271 -        * mask interrupts since we are going to poll
 272 -        * for reset completion status
 273 -        */
 274 -       clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK);
 275 +       /* Check the current status */
 276 +       if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS)
 277 +               goto wait_quiesce_completion;
 278
 279 -       /* initiate flush (required prior to reset) */
 280 -       wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
 281 +       /* Reset the field */
 282 +       clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0);
 283 +
 284 +       /* initiate flush / park (required prior to reset) */
 285 +       wr_reg32(&jrp->rregs->jrcommand, jrcr_bits);
 286 +
 287 +wait_quiesce_completion:
 288         while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
 289                 JRINT_ERR_HALT_INPROGRESS) && --timeout)
 290                 cpu_relax();
 291 @@ -95,8 +103,56 @@ static int caam_reset_hw_jr(struct devic
 292                 return -EIO;
 293         }
 294
 295 +       return 0;
 296 +}
 297 +
 298 +/*
 299 + * Flush the job ring, so the jobs running will be stopped, jobs queued will be
 300 + * invalidated and the CAAM will no longer fetch fron input ring.
 301 + *
 302 + * Must be called with itr disabled
 303 + */
 304 +static int caam_jr_flush(struct device *dev)
 305 +{
 306 +       return caam_jr_stop_processing(dev, JRCR_RESET);
 307 +}
 308 +
 309 +#ifdef CONFIG_PM_SLEEP
 310 +/* The resume can be used after a park or a flush if CAAM has not been reset */
 311 +static int caam_jr_restart_processing(struct device *dev)
 312 +{
 313 +       struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
 314 +       u32 halt_status = rd_reg32(&jrp->rregs->jrintstatus) &
 315 +                         JRINT_ERR_HALT_MASK;
 316 +
 317 +       /* Check that the flush/park is completed */
 318 +       if (halt_status != JRINT_ERR_HALT_COMPLETE)
 319 +               return -1;
 320 +
 321 +       /* Resume processing of jobs */
 322 +       clrsetbits_32(&jrp->rregs->jrintstatus, 0, JRINT_ERR_HALT_COMPLETE);
 323 +
 324 +       return 0;
 325 +}
 326 +#endif /* CONFIG_PM_SLEEP */
 327 +
 328 +static int caam_reset_hw_jr(struct device *dev)
 329 +{
 330 +       struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
 331 +       unsigned int timeout = 100000;
 332 +       int err;
 333 +
 334 +       /*
 335 +        * mask interrupts since we are going to poll
 336 +        * for reset completion status
 337 +        */
 338 +       clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK);
 339 +
 340 +       err = caam_jr_flush(dev);
 341 +       if (err)
 342 +               return err;
 343 +
 344         /* initiate reset */
 345 -       timeout = 100000;
 346         wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
 347         while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
 348                 cpu_relax();
 349 @@ -204,7 +260,8 @@ static irqreturn_t caam_jr_interrupt(int
 350  static void caam_jr_dequeue(unsigned long devarg)
 351  {
 352         int hw_idx, sw_idx, i, head, tail;
 353 -       struct device *dev = (struct device *)devarg;
 354 +       struct caam_jr_dequeue_params *params = (void *)devarg;
 355 +       struct device *dev = params->dev;
 356         struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
 357         void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg);
 358         u32 *userdesc, userstatus;
 359 @@ -278,8 +335,9 @@ static void caam_jr_dequeue(unsigned lon
 360                 outring_used--;
 361         }
 362
 363 -       /* reenable / unmask IRQs */
 364 -       clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
 365 +       if (params->enable_itr)
 366 +               /* reenable / unmask IRQs */
 367 +               clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
 368  }
 369
 370  /**
 371 @@ -467,6 +525,29 @@ int caam_jr_enqueue(struct device *dev,
 372  }
 373  EXPORT_SYMBOL(caam_jr_enqueue);
 374
 375 +static void caam_jr_init_hw(struct device *dev, dma_addr_t inpbusaddr,
 376 +                           dma_addr_t outbusaddr)
 377 +{
 378 +       struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
 379 +
 380 +       wr_reg64(&jrp->rregs->inpring_base, inpbusaddr);
 381 +       wr_reg64(&jrp->rregs->outring_base, outbusaddr);
 382 +       wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);
 383 +       wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);
 384 +
 385 +       /* Select interrupt coalescing parameters */
 386 +       clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC |
 387 +                     (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) |
 388 +                     (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT));
 389 +}
 390 +
 391 +static void caam_jr_reset_index(struct caam_drv_private_jr *jrp)
 392 +{
 393 +       jrp->out_ring_read_index = 0;
 394 +       jrp->head = 0;
 395 +       jrp->tail = 0;
 396 +}
 397 +
 398  /*
 399   * Init JobR independent of platform property detection
 400   */
 401 @@ -503,25 +584,16 @@ static int caam_jr_init(struct device *d
 402                 jrp->entinfo[i].desc_addr_dma = !0;
 403
 404         /* Setup rings */
 405 -       jrp->out_ring_read_index = 0;
 406 -       jrp->head = 0;
 407 -       jrp->tail = 0;
 408 -
 409 -       wr_reg64(&jrp->rregs->inpring_base, inpbusaddr);
 410 -       wr_reg64(&jrp->rregs->outring_base, outbusaddr);
 411 -       wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);
 412 -       wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);
 413 -
 414 +       caam_jr_reset_index(jrp);
 415         jrp->inpring_avail = JOBR_DEPTH;
 416 +       caam_jr_init_hw(dev, inpbusaddr, outbusaddr);
 417
 418         spin_lock_init(&jrp->inplock);
 419
 420 -       /* Select interrupt coalescing parameters */
 421 -       clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC |
 422 -                     (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) |
 423 -                     (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT));
 424 -
 425 -       tasklet_init(&jrp->irqtask, caam_jr_dequeue, (unsigned long)dev);
 426 +       jrp->tasklet_params.dev = dev;
 427 +       jrp->tasklet_params.enable_itr = 1;
 428 +       tasklet_init(&jrp->irqtask, caam_jr_dequeue,
 429 +                    (unsigned long)&jrp->tasklet_params);
 430
 431         /* Connect job ring interrupt handler. */
 432         error = devm_request_irq(dev, jrp->irq, caam_jr_interrupt, IRQF_SHARED,
 433 @@ -620,14 +692,48 @@ static int caam_jr_probe(struct platform
 434         return 0;
 435  }
 436
 437 -#ifdef CONFIG_PM
 438 +#ifdef CONFIG_PM_SLEEP
 439 +static void caam_jr_get_hw_state(struct device *dev)
 440 +{
 441 +       struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
 442 +
 443 +       jrp->state.inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
 444 +       jrp->state.outbusaddr = rd_reg64(&jrp->rregs->outring_base);
 445 +}
 446 +
 447  static int caam_jr_suspend(struct device *dev)
 448  {
 449         struct platform_device *pdev = to_platform_device(dev);
 450         struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev);
 451 +       struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent);
 452 +       struct caam_jr_dequeue_params suspend_params = {
 453 +               .dev = dev,
 454 +               .enable_itr = 0,
 455 +       };
 456 +
 457 +       if (ctrlpriv->caam_off_during_pm) {
 458 +               int err;
 459 +
 460 +               tasklet_disable(&jrpriv->irqtask);
 461 +
 462 +               /* mask itr to call flush */
 463 +               clrsetbits_32(&jrpriv->rregs->rconfig_lo, 0, JRCFG_IMSK);
 464 +
 465 +               /* Invalid job in process */
 466 +               err = caam_jr_flush(dev);
 467 +               if (err) {
 468 +                       dev_err(dev, "Failed to flush\n");
 469 +                       return err;
 470 +               }
 471 +
 472 +               /* Dequeing jobs flushed */
 473 +               caam_jr_dequeue((unsigned long)&suspend_params);
 474
 475 -       if (device_may_wakeup(&pdev->dev))
 476 +               /* Save state */
 477 +               caam_jr_get_hw_state(dev);
 478 +       } else if (device_may_wakeup(&pdev->dev)) {
 479                 enable_irq_wake(jrpriv->irq);
 480 +       }
 481
 482         return 0;
 483  }
 484 @@ -636,16 +742,61 @@ static int caam_jr_resume(struct device
 485  {
 486         struct platform_device *pdev = to_platform_device(dev);
 487         struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev);
 488 +       struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev->parent);
 489
 490 -       if (device_may_wakeup(&pdev->dev))
 491 +       if (ctrlpriv->caam_off_during_pm) {
 492 +               u64 inp_addr;
 493 +               int err;
 494 +
 495 +               /*
 496 +                * Check if the CAAM has been resetted checking the address of
 497 +                * the input ring
 498 +                */
 499 +               inp_addr = rd_reg64(&jrpriv->rregs->inpring_base);
 500 +               if (inp_addr != 0) {
 501 +                       /* JR still has some configuration */
 502 +                       if (inp_addr == jrpriv->state.inpbusaddr) {
 503 +                               /* JR has not been resetted */
 504 +                               err = caam_jr_restart_processing(dev);
 505 +                               if (err) {
 506 +                                       dev_err(dev,
 507 +                                               "Restart processing failed\n");
 508 +                                       return err;
 509 +                               }
 510 +
 511 +                               tasklet_enable(&jrpriv->irqtask);
 512 +
 513 +                               clrsetbits_32(&jrpriv->rregs->rconfig_lo,
 514 +                                             JRCFG_IMSK, 0);
 515 +
 516 +                               return 0;
 517 +                       } else if (ctrlpriv->optee_en) {
 518 +                               /* JR has been used by OPTEE, reset it */
 519 +                               err = caam_reset_hw_jr(dev);
 520 +                               if (err) {
 521 +                                       dev_err(dev, "Failed to reset JR\n");
 522 +                                       return err;
 523 +                               }
 524 +                       } else {
 525 +                               /* No explanation, return error */
 526 +                               return -EIO;
 527 +                       }
 528 +               }
 529 +
 530 +               caam_jr_reset_index(jrpriv);
 531 +               caam_jr_init_hw(dev, jrpriv->state.inpbusaddr,
 532 +                               jrpriv->state.outbusaddr);
 533 +
 534 +               tasklet_enable(&jrpriv->irqtask);
 535 +       } else if (device_may_wakeup(&pdev->dev)) {
 536                 disable_irq_wake(jrpriv->irq);
 537 +       }
 538
 539         return 0;
 540  }
 541
 542 -static SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend,
 543 -                        caam_jr_resume);
 544 -#endif
 545 +SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend, caam_jr_resume);
 546 +#endif /* CONFIG_PM_SLEEP */
 547
 548  static const struct of_device_id caam_jr_match[] = {
 549         {
 550 @@ -662,7 +813,7 @@ static struct platform_driver caam_jr_dr
 551         .driver = {
 552                 .name = "caam_jr",
 553                 .of_match_table = caam_jr_match,
 554 -#ifdef CONFIG_PM
 555 +#ifdef CONFIG_PM_SLEEP
 556                 .pm = &caam_jr_pm_ops,
 557  #endif
 558         },
 559 --- a/drivers/crypto/caam/regs.h
 560 +++ b/drivers/crypto/caam/regs.h
 561 @@ -631,8 +631,7 @@ struct caam_ctrl {
 562         u32 deco_rsr;                   /* DECORSR - Deco Request Source */
 563         u32 rsvd11;
 564         u32 deco_rq;                    /* DECORR - DECO Request */
 565 -       struct masterid deco_mid[5];    /* DECOxLIODNR - 1 per DECO */
 566 -       u32 rsvd5[22];
 567 +       struct masterid deco_mid[16];   /* DECOxLIODNR - 1 per DECO */
 568
 569         /* DECO Availability/Reset Section                      120-3ff */
 570         u32 deco_avail;         /* DAR - DECO availability */