target/linux/layerscape/patches-5.4/803-clock-0001-clk-ls1028a-Add-clock-driver-for-Display-output-inte.patch

   1 From e9e60d44268e2cfba73efeb7c3e68c355940f2c3 Mon Sep 17 00:00:00 2001
   2 From: Wen He <wen.he_1@nxp.com>
   3 Date: Wed, 27 Nov 2019 11:19:26 +0800
   4 Subject: [PATCH] clk: ls1028a: Add clock driver for Display output interface
   5
   6 Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
   7 as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
   8 integer division and range of the display output pixel clock's 27-594MHz.
   9
  10 Signed-off-by: Wen He <wen.he_1@nxp.com>
  11 Signed-off-by: Michael Walle <michael@walle.cc>
  12 ---
  13  drivers/clk/Kconfig      |  10 ++
  14  drivers/clk/Makefile     |   1 +
  15  drivers/clk/clk-plldig.c | 301 +++++++++++++++++++++++++++++++++++++++++++++++
  16  3 files changed, 312 insertions(+)
  17  create mode 100644 drivers/clk/clk-plldig.c
  18
  19 --- a/drivers/clk/Kconfig
  20 +++ b/drivers/clk/Kconfig
  21 @@ -218,6 +218,16 @@ config CLK_QORIQ
  22           This adds the clock driver support for Freescale QorIQ platforms
  23           using common clock framework.
  24
  25 +config CLK_LS1028A_PLLDIG
  26 +        tristate "Clock driver for LS1028A Display output"
  27 +        depends on ARCH_LAYERSCAPE || COMPILE_TEST
  28 +        default ARCH_LAYERSCAPE
  29 +        help
  30 +          This driver support the Display output interfaces(LCD, DPHY) pixel clocks
  31 +          of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
  32 +          features of the PLL are currently supported by the driver. By default,
  33 +          configured bypass mode with this PLL.
  34 +
  35  config COMMON_CLK_XGENE
  36         bool "Clock driver for APM XGene SoC"
  37         default ARCH_XGENE
  38 --- a/drivers/clk/Makefile
  39 +++ b/drivers/clk/Makefile
  40 @@ -43,6 +43,7 @@ obj-$(CONFIG_ARCH_NPCM7XX)            += clk-n
  41  obj-$(CONFIG_ARCH_NSPIRE)              += clk-nspire.o
  42  obj-$(CONFIG_COMMON_CLK_OXNAS)         += clk-oxnas.o
  43  obj-$(CONFIG_COMMON_CLK_PALMAS)                += clk-palmas.o
  44 +obj-$(CONFIG_CLK_LS1028A_PLLDIG)       += clk-plldig.o
  45  obj-$(CONFIG_COMMON_CLK_PWM)           += clk-pwm.o
  46  obj-$(CONFIG_CLK_QORIQ)                        += clk-qoriq.o
  47  obj-$(CONFIG_COMMON_CLK_RK808)         += clk-rk808.o
  48 --- /dev/null
  49 +++ b/drivers/clk/clk-plldig.c
  50 @@ -0,0 +1,301 @@
  51 +// SPDX-License-Identifier: GPL-2.0
  52 +/*
  53 + * Copyright 2019 NXP
  54 + *
  55 + * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
  56 + */
  57 +
  58 +#include <linux/clk-provider.h>
  59 +#include <linux/device.h>
  60 +#include <linux/module.h>
  61 +#include <linux/err.h>
  62 +#include <linux/io.h>
  63 +#include <linux/iopoll.h>
  64 +#include <linux/of.h>
  65 +#include <linux/of_address.h>
  66 +#include <linux/of_device.h>
  67 +#include <linux/platform_device.h>
  68 +#include <linux/slab.h>
  69 +#include <linux/bitfield.h>
  70 +
  71 +/* PLLDIG register offsets and bit masks */
  72 +#define PLLDIG_REG_PLLSR            0x24
  73 +#define PLLDIG_LOCK_MASK            BIT(2)
  74 +#define PLLDIG_REG_PLLDV            0x28
  75 +#define PLLDIG_MFD_MASK             GENMASK(7, 0)
  76 +#define PLLDIG_RFDPHI1_MASK         GENMASK(30, 25)
  77 +#define PLLDIG_REG_PLLFM            0x2c
  78 +#define PLLDIG_SSCGBYP_ENABLE       BIT(30)
  79 +#define PLLDIG_REG_PLLFD            0x30
  80 +#define PLLDIG_FDEN                 BIT(30)
  81 +#define PLLDIG_FRAC_MASK            GENMASK(15, 0)
  82 +#define PLLDIG_DTH_MASK             GENMASK(17, 16)
  83 +#define PLLDIG_DTH_DISABLE          3
  84 +#define PLLDIG_REG_PLLCAL1          0x38
  85 +#define PLLDIG_REG_PLLCAL2          0x3c
  86 +
  87 +/* Range of the VCO frequencies, in Hz */
  88 +#define PLLDIG_MIN_VCO_FREQ         650000000
  89 +#define PLLDIG_MAX_VCO_FREQ         1300000000
  90 +
  91 +/* Range of the output frequencies, in Hz */
  92 +#define PHI1_MIN_FREQ               27000000
  93 +#define PHI1_MAX_FREQ               600000000
  94 +
  95 +/* Maximum value of the reduced frequency divider */
  96 +#define MAX_RFDPHI1          63UL
  97 +
  98 +/* Best value of multiplication factor divider */
  99 +#define PLLDIG_DEFAULT_MFD   44
 100 +
 101 +/*
 102 + * Denominator part of the fractional part of the
 103 + * loop multiplication factor.
 104 + */
 105 +#define MFDEN          20480
 106 +
 107 +static const struct clk_parent_data parent_data[] = {
 108 +       {.index = 0},
 109 +};
 110 +
 111 +struct clk_plldig {
 112 +       struct clk_hw hw;
 113 +       void __iomem *regs;
 114 +       unsigned int vco_freq;
 115 +};
 116 +
 117 +#define to_clk_plldig(_hw)     container_of(_hw, struct clk_plldig, hw)
 118 +
 119 +static int plldig_enable(struct clk_hw *hw)
 120 +{
 121 +       struct clk_plldig *data = to_clk_plldig(hw);
 122 +       u32 val;
 123 +
 124 +       val = readl(data->regs + PLLDIG_REG_PLLFM);
 125 +       /*
 126 +        * Use Bypass mode with PLL off by default, the frequency overshoot
 127 +        * detector output was disable. SSCG Bypass mode should be enable.
 128 +        */
 129 +       val |= PLLDIG_SSCGBYP_ENABLE;
 130 +       writel(val, data->regs + PLLDIG_REG_PLLFM);
 131 +
 132 +       return 0;
 133 +}
 134 +
 135 +static void plldig_disable(struct clk_hw *hw)
 136 +{
 137 +       struct clk_plldig *data = to_clk_plldig(hw);
 138 +       u32 val;
 139 +
 140 +       val = readl(data->regs + PLLDIG_REG_PLLFM);
 141 +
 142 +       val &= ~PLLDIG_SSCGBYP_ENABLE;
 143 +       val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0);
 144 +
 145 +       writel(val, data->regs + PLLDIG_REG_PLLFM);
 146 +}
 147 +
 148 +static int plldig_is_enabled(struct clk_hw *hw)
 149 +{
 150 +       struct clk_plldig *data = to_clk_plldig(hw);
 151 +
 152 +       return (readl(data->regs + PLLDIG_REG_PLLFM) &
 153 +                             PLLDIG_SSCGBYP_ENABLE);
 154 +}
 155 +
 156 +static unsigned long plldig_recalc_rate(struct clk_hw *hw,
 157 +                                       unsigned long parent_rate)
 158 +{
 159 +       struct clk_plldig *data = to_clk_plldig(hw);
 160 +       u32 val, rfdphi1;
 161 +
 162 +       val = readl(data->regs + PLLDIG_REG_PLLDV);
 163 +
 164 +       /* Check if PLL is bypassed */
 165 +       if (val & PLLDIG_SSCGBYP_ENABLE)
 166 +               return parent_rate;
 167 +
 168 +       rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val);
 169 +
 170 +       /*
 171 +        * If RFDPHI1 has a value of 1 the VCO frequency is also divided by
 172 +        * one.
 173 +        */
 174 +       if (!rfdphi1)
 175 +               rfdphi1 = 1;
 176 +
 177 +       return DIV_ROUND_UP(data->vco_freq, rfdphi1);
 178 +}
 179 +
 180 +static unsigned long plldig_calc_target_div(unsigned long vco_freq,
 181 +                                           unsigned long target_rate)
 182 +{
 183 +       unsigned long div;
 184 +
 185 +       div = DIV_ROUND_CLOSEST(vco_freq, target_rate);
 186 +       div = max(1UL, div);
 187 +       div = min(div, MAX_RFDPHI1);
 188 +
 189 +       return div;
 190 +}
 191 +
 192 +static int plldig_determine_rate(struct clk_hw *hw,
 193 +                                struct clk_rate_request *req)
 194 +{
 195 +       struct clk_plldig *data = to_clk_plldig(hw);
 196 +       unsigned int div;
 197 +
 198 +       if (req->rate < PHI1_MIN_FREQ)
 199 +               req->rate = PHI1_MIN_FREQ;
 200 +       if (req->rate > PHI1_MAX_FREQ)
 201 +               req->rate = PHI1_MAX_FREQ;
 202 +
 203 +       div = plldig_calc_target_div(data->vco_freq, req->rate);
 204 +       req->rate = DIV_ROUND_UP(data->vco_freq, div);
 205 +
 206 +       return 0;
 207 +}
 208 +
 209 +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
 210 +               unsigned long parent_rate)
 211 +{
 212 +       struct clk_plldig *data = to_clk_plldig(hw);
 213 +       unsigned int val, cond;
 214 +       unsigned int rfdphi1;
 215 +
 216 +       if (rate < PHI1_MIN_FREQ)
 217 +               rate = PHI1_MIN_FREQ;
 218 +       if (rate > PHI1_MAX_FREQ)
 219 +               rate = PHI1_MAX_FREQ;
 220 +
 221 +       rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);
 222 +
 223 +       /* update the divider value */
 224 +       val = readl(data->regs + PLLDIG_REG_PLLDV);
 225 +       val &= ~PLLDIG_RFDPHI1_MASK;
 226 +       val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1);
 227 +       writel(val, data->regs + PLLDIG_REG_PLLDV);
 228 +
 229 +       /* delay 200us make sure that old lock state is cleared */
 230 +       udelay(200);
 231 +
 232 +       /* Wait until PLL is locked or timeout (maximum 1000 usecs) */
 233 +       return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
 234 +                                        cond & PLLDIG_LOCK_MASK, 0,
 235 +                                        USEC_PER_MSEC);
 236 +}
 237 +
 238 +static const struct clk_ops plldig_clk_ops = {
 239 +       .enable = plldig_enable,
 240 +       .disable = plldig_disable,
 241 +       .is_enabled = plldig_is_enabled,
 242 +       .recalc_rate = plldig_recalc_rate,
 243 +       .determine_rate = plldig_determine_rate,
 244 +       .set_rate = plldig_set_rate,
 245 +};
 246 +
 247 +static int plldig_init(struct clk_hw *hw)
 248 +{
 249 +       struct clk_plldig *data = to_clk_plldig(hw);
 250 +       struct clk_hw *parent = clk_hw_get_parent(hw);
 251 +       unsigned long parent_rate = clk_hw_get_rate(parent);
 252 +       unsigned long val;
 253 +       unsigned long long lltmp;
 254 +       unsigned int mfd, fracdiv = 0;
 255 +
 256 +       if (!parent)
 257 +               return -EINVAL;
 258 +
 259 +       if (data->vco_freq) {
 260 +               mfd = data->vco_freq / parent_rate;
 261 +               lltmp = data->vco_freq % parent_rate;
 262 +               lltmp *= MFDEN;
 263 +               do_div(lltmp, parent_rate);
 264 +               fracdiv = lltmp;
 265 +       } else {
 266 +               mfd = PLLDIG_DEFAULT_MFD;
 267 +               data->vco_freq = parent_rate * mfd;
 268 +       }
 269 +
 270 +       val = FIELD_PREP(PLLDIG_MFD_MASK, mfd);
 271 +       writel(val, data->regs + PLLDIG_REG_PLLDV);
 272 +
 273 +       if (fracdiv) {
 274 +               val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv);
 275 +               /* Enable fractional divider */
 276 +               val |= PLLDIG_FDEN;
 277 +               /* Disable dither */
 278 +               val |= FIELD_PREP(PLLDIG_DTH_MASK, PLLDIG_DTH_DISABLE);
 279 +               writel(val, data->regs + PLLDIG_REG_PLLFD);
 280 +       }
 281 +
 282 +       return 0;
 283 +}
 284 +
 285 +static int plldig_clk_probe(struct platform_device *pdev)
 286 +{
 287 +       struct clk_plldig *data;
 288 +       struct resource *mem;
 289 +       struct device *dev = &pdev->dev;
 290 +       int ret;
 291 +
 292 +       data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 293 +       if (!data)
 294 +               return -ENOMEM;
 295 +
 296 +       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 297 +       data->regs = devm_ioremap_resource(dev, mem);
 298 +       if (IS_ERR(data->regs))
 299 +               return PTR_ERR(data->regs);
 300 +
 301 +       data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
 302 +                                                parent_data,
 303 +                                                &plldig_clk_ops,
 304 +                                                0);
 305 +
 306 +       ret = devm_clk_hw_register(dev, &data->hw);
 307 +       if (ret) {
 308 +               dev_err(dev, "failed to register %s clock\n",
 309 +                                               dev->of_node->name);
 310 +               return ret;
 311 +       }
 312 +
 313 +       ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
 314 +                                         &data->hw);
 315 +       if (ret) {
 316 +               dev_err(dev, "unable to add clk provider\n");
 317 +               return ret;
 318 +       }
 319 +
 320 +       /*
 321 +        * The frequency of the VCO cannot be changed during runtime.
 322 +        * Therefore, let the user specify a desired frequency.
 323 +        */
 324 +       if (!of_property_read_u32(dev->of_node, "vco-frequency",
 325 +                                 &data->vco_freq)) {
 326 +               if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||
 327 +                   data->vco_freq > PLLDIG_MAX_VCO_FREQ)
 328 +                       return -EINVAL;
 329 +       }
 330 +
 331 +       return plldig_init(&data->hw);
 332 +}
 333 +
 334 +static const struct of_device_id plldig_clk_id[] = {
 335 +       { .compatible = "fsl,ls1028a-plldig"},
 336 +       { }
 337 +};
 338 +MODULE_DEVICE_TABLE(of, plldig_clk_id);
 339 +
 340 +static struct platform_driver plldig_clk_driver = {
 341 +       .driver = {
 342 +               .name = "plldig-clock",
 343 +               .of_match_table = plldig_clk_id,
 344 +       },
 345 +       .probe = plldig_clk_probe,
 346 +};
 347 +module_platform_driver(plldig_clk_driver);
 348 +
 349 +MODULE_LICENSE("GPL v2");
 350 +MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>");
 351 +MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");