ath79/mikrotik: use routerbootpart partitions
[oweals/openwrt.git] / target / linux / layerscape / patches-5.4 / 801-audio-0019-MLK-13609-ASoC-fsl_sai-fix-for-synchronize-mode.patch
1 From 7b5c62dc6c1de58ee1d527059ae69152ed1380f2 Mon Sep 17 00:00:00 2001
2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
3 Date: Mon, 12 Dec 2016 11:52:24 +0800
4 Subject: [PATCH] MLK-13609: ASoC: fsl_sai: fix for synchronize mode
5
6 TX synchronous with receiver: the RMR should not be changed and
7 the RCSR.RE should be set in playback.
8 RX synchronous with transmitter: the TMR should not be changed and
9 the TCSR.TE should be set in recording.
10
11 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
12 ---
13  sound/soc/fsl/fsl_sai.c | 15 ++++++++-------
14  1 file changed, 8 insertions(+), 7 deletions(-)
15
16 --- a/sound/soc/fsl/fsl_sai.c
17 +++ b/sound/soc/fsl/fsl_sai.c
18 @@ -527,8 +527,6 @@ static int fsl_sai_hw_params(struct snd_
19                         regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
20                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
21                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
22 -                       regmap_write(sai->regmap, FSL_SAI_TMR,
23 -                               ~0UL - ((1 << channels) - 1));
24                 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
25                         regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
26                                 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
27 @@ -536,8 +534,6 @@ static int fsl_sai_hw_params(struct snd_
28                         regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
29                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
30                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
31 -                       regmap_write(sai->regmap, FSL_SAI_RMR,
32 -                               ~0UL - ((1 << channels) - 1));
33                 }
34         }
35  
36 @@ -626,12 +622,17 @@ static int fsl_sai_trigger(struct snd_pc
37                 if (tx)
38                         udelay(10);
39  
40 -               regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
41 -                                  FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
42 -               regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
43 +               regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
44                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
45                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
46                                    FSL_SAI_CSR_SE, FSL_SAI_CSR_SE);
47 +               if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
48 +                       regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx)),
49 +                                  FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
50 +               } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
51 +                       regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx)),
52 +                                  FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
53 +               }
54  
55                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
56                                    FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);