target/linux/layerscape/patches-5.4/701-net-0331-drivers-net-phy-aquantia-enable-AQR112-and-AQR412.patch

   1 From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001
   2 From: Alex Marginean <alexandru.marginean@nxp.com>
   3 Date: Tue, 27 Aug 2019 15:16:56 +0300
   4 Subject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412
   5
   6 Adds support for AQR112 and AQR412 which is mostly based on existing code
   7 with the addition of code configuring the protocol on system side.
   8 This allows changing the system side protocol without having to deploy a
   9 different firmware on the PHY.
  10
  11 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  12 ---
  13  drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
  14  1 file changed, 88 insertions(+)
  15
  16 --- a/drivers/net/phy/aquantia_main.c
  17 +++ b/drivers/net/phy/aquantia_main.c
  18 @@ -22,6 +22,8 @@
  19  #define PHY_ID_AQR107  0x03a1b4e0
  20  #define PHY_ID_AQCS109 0x03a1b5c2
  21  #define PHY_ID_AQR405  0x03a1b4b0
  22 +#define PHY_ID_AQR112  0x03a1b662
  23 +#define PHY_ID_AQR412  0x03a1b712
  24
  25  #define MDIO_PHYXS_VEND_IF_STATUS              0xe812
  26  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK    GENMASK(7, 3)
  27 @@ -121,6 +123,29 @@
  28  #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2     BIT(1)
  29  #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3     BIT(0)
  30
  31 +/* registers in MDIO_MMD_VEND1 region */
  32 +#define AQUANTIA_VND1_GLOBAL_SC                        0x000
  33 +#define  AQUANTIA_VND1_GLOBAL_SC_LP            BIT(0xb)
  34 +
  35 +/* global start rate, the protocol associated with this speed is used by default
  36 + * on SI.
  37 + */
  38 +#define AQUANTIA_VND1_GSTART_RATE              0x31a
  39 +#define  AQUANTIA_VND1_GSTART_RATE_OFF         0
  40 +#define  AQUANTIA_VND1_GSTART_RATE_100M                1
  41 +#define  AQUANTIA_VND1_GSTART_RATE_1G          2
  42 +#define  AQUANTIA_VND1_GSTART_RATE_10G         3
  43 +#define  AQUANTIA_VND1_GSTART_RATE_2_5G                4
  44 +#define  AQUANTIA_VND1_GSTART_RATE_5G          5
  45 +
  46 +/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  47 +#define AQUANTIA_VND1_GSYSCFG_BASE             0x31b
  48 +#define AQUANTIA_VND1_GSYSCFG_100M             0
  49 +#define AQUANTIA_VND1_GSYSCFG_1G               1
  50 +#define AQUANTIA_VND1_GSYSCFG_2_5G             2
  51 +#define AQUANTIA_VND1_GSYSCFG_5G               3
  52 +#define AQUANTIA_VND1_GSYSCFG_10G              4
  53 +
  54  struct aqr107_hw_stat {
  55         const char *name;
  56         int reg;
  57 @@ -241,6 +266,51 @@ static int aqr_config_aneg(struct phy_de
  58         return genphy_c45_check_and_restart_aneg(phydev, changed);
  59  }
  60
  61 +static struct {
  62 +       u16 syscfg;
  63 +       int cnt;
  64 +       u16 start_rate;
  65 +} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
  66 +       [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
  67 +                                          AQUANTIA_VND1_GSTART_RATE_1G},
  68 +       [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
  69 +                                          AQUANTIA_VND1_GSTART_RATE_2_5G},
  70 +       [PHY_INTERFACE_MODE_XGMII] =      {0x100, AQUANTIA_VND1_GSYSCFG_10G,
  71 +                                          AQUANTIA_VND1_GSTART_RATE_10G},
  72 +       [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
  73 +                                          AQUANTIA_VND1_GSTART_RATE_10G},
  74 +};
  75 +
  76 +/* Sets up protocol on system side before calling aqr_config_aneg */
  77 +static int aqr_config_aneg_set_prot(struct phy_device *phydev)
  78 +{
  79 +       int if_type = phydev->interface;
  80 +       int i;
  81 +
  82 +       if (!aquantia_syscfg[if_type].cnt)
  83 +               return 0;
  84 +
  85 +       /* set PHY in low power mode so we can configure protocols */
  86 +       phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
  87 +                     AQUANTIA_VND1_GLOBAL_SC_LP);
  88 +       mdelay(10);
  89 +
  90 +       /* set the default rate to enable the SI link */
  91 +       phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  92 +                     aquantia_syscfg[if_type].start_rate);
  93 +
  94 +       for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)
  95 +               phy_write_mmd(phydev, MDIO_MMD_VEND1,
  96 +                             AQUANTIA_VND1_GSYSCFG_BASE + i,
  97 +                             aquantia_syscfg[if_type].syscfg);
  98 +
  99 +       /* wake PHY back up */
 100 +       phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
 101 +       mdelay(10);
 102 +
 103 +       return aqr_config_aneg(phydev);
 104 +}
 105 +
 106  static int aqr_config_intr(struct phy_device *phydev)
 107  {
 108         bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
 109 @@ -682,6 +752,22 @@ static struct phy_driver aqr_driver[] =
 110         .ack_interrupt  = aqr_ack_interrupt,
 111         .read_status    = aqr_read_status,
 112  },
 113 +{
 114 +       PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
 115 +       .name           = "Aquantia AQR112",
 116 +       .config_aneg    = aqr_config_aneg_set_prot,
 117 +       .config_intr    = aqr_config_intr,
 118 +       .ack_interrupt  = aqr_ack_interrupt,
 119 +       .read_status    = aqr_read_status,
 120 +},
 121 +{
 122 +       PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
 123 +       .name           = "Aquantia AQR412",
 124 +       .config_aneg    = aqr_config_aneg_set_prot,
 125 +       .config_intr    = aqr_config_intr,
 126 +       .ack_interrupt  = aqr_ack_interrupt,
 127 +       .read_status    = aqr_read_status,
 128 +},
 129  };
 130
 131  module_phy_driver(aqr_driver);
 132 @@ -694,6 +780,8 @@ static struct mdio_device_id __maybe_unu
 133         { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
 134         { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
 135         { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
 136 +       { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
 137 +       { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
 138         { }
 139  };
 140