target/linux/layerscape/patches-5.4/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch

   1 From a5009b362d65c24e7b2a40824e351903d75a47dc Mon Sep 17 00:00:00 2001
   2 From: Alex Marginean <alexandru.marginean@nxp.com>
   3 Date: Mon, 6 Jan 2020 16:36:44 +0200
   4 Subject: [PATCH] arm64: dts: fsl-ls1028a: prepare dts for overlay
   5
   6 Named the ports node of the Felix Eth switch so it can be used in DT
   7 overlays to associate the ports with proper PHYs.
   8 Ports are now by default disabled in dtsi, so if the board dts doesn't
   9 do anything about them they stay disabled.
  10 Updated RDB and QDS dts files to match.
  11 Replaced all 'phy-connection-type' with 'phy-mode'.
  12 The set-up for protocol 7777 on QDS was changed to a single quad port card
  13 in slot 1.  This requires a QDS board with no lane B rework and a AQR412
  14 or similar PHY card without any lane rework done on it.
  15
  16 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  17 ---
  18  .../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi   | 58 ++++++++++-----------
  19  .../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi   | 59 ++++++++++------------
  20  .../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi   | 51 ++++++++++++-------
  21  .../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi   | 43 ++++++++++------
  22  arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts  | 44 +++++++++-------
  23  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi     | 27 +++++++---
  24  6 files changed, 161 insertions(+), 121 deletions(-)
  25
  26 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
  27 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
  28 @@ -7,50 +7,50 @@
  29   */
  30
  31  &mdio_slot1 {
  32 -       /* two ports on AQR412 */
  33 -       slot1_sxgmii2: ethernet-phy@2 {
  34 -               reg = <0x2>;
  35 +       slot1_sxgmii0: ethernet-phy@0 {
  36 +               reg = <0x0>;
  37                 compatible = "ethernet-phy-ieee802.3-c45";
  38         };
  39 -       slot1_sxgmii3: ethernet-phy@3 {
  40 -               reg = <0x3>;
  41 +
  42 +       slot1_sxgmii1: ethernet-phy@1 {
  43 +               reg = <0x1>;
  44                 compatible = "ethernet-phy-ieee802.3-c45";
  45         };
  46 -};
  47
  48 -&mdio_slot2 {
  49 -       slot2_sxgmii0: ethernet-phy@2 {
  50 -               /* AQR112 */
  51 +       slot1_sxgmii2: ethernet-phy@2 {
  52                 reg = <0x2>;
  53                 compatible = "ethernet-phy-ieee802.3-c45";
  54         };
  55 -};
  56
  57 -&mdio_slot3 {
  58 -       slot3_sxgmii0: ethernet-phy@2 {
  59 -               /* AQR112 */
  60 -               reg = <0x2>;
  61 +       slot1_sxgmii3: ethernet-phy@3 {
  62 +               reg = <0x3>;
  63                 compatible = "ethernet-phy-ieee802.3-c45";
  64         };
  65  };
  66
  67  /* l2switch ports */
  68 -&switch_port0 {
  69 -       phy-handle = <&slot1_sxgmii2>;
  70 -       phy-connection-type = "2500base-x";
  71 -};
  72 +&mscc_felix_ports {
  73 +       port@0 {
  74 +               status = "okay";
  75 +               phy-handle = <&slot1_sxgmii0>;
  76 +               phy-mode = "2500base-x";
  77 +       };
  78
  79 -&switch_port1 {
  80 -       phy-handle = <&slot2_sxgmii0>;
  81 -       phy-connection-type = "2500base-x";
  82 -};
  83 +       port@1 {
  84 +               status = "okay";
  85 +               phy-handle = <&slot1_sxgmii1>;
  86 +               phy-mode = "2500base-x";
  87 +       };
  88
  89 -&switch_port2 {
  90 -       phy-handle = <&slot3_sxgmii0>;
  91 -       phy-connection-type = "2500base-x";
  92 -};
  93 +       port@2 {
  94 +               status = "okay";
  95 +               phy-handle = <&slot1_sxgmii2>;
  96 +               phy-mode = "2500base-x";
  97 +       };
  98
  99 -&switch_port3 {
 100 -       phy-handle = <&slot1_sxgmii3>;
 101 -       phy-connection-type = "2500base-x";
 102 +       port@3 {
 103 +               status = "okay";
 104 +               phy-handle = <&slot1_sxgmii3>;
 105 +               phy-mode = "2500base-x";
 106 +       };
 107  };
 108 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
 109 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
 110 @@ -11,50 +11,47 @@
 111         slot1_sgmii0: ethernet-phy@1c {
 112                 reg = <0x1c>;
 113         };
 114 +
 115         slot1_sgmii1: ethernet-phy@1d {
 116                 reg = <0x1d>;
 117         };
 118 +
 119         slot1_sgmii2: ethernet-phy@1e {
 120                 reg = <0x1e>;
 121         };
 122 -       slot1_sgmii3: ethernet-phy@1f {
 123 -               reg = <0x1f>;
 124 -       };
 125 -};
 126
 127 -&mdio_slot2 {
 128 -       /* VSC8234 */
 129 -       slot2_sgmii0: ethernet-phy@1c {
 130 -               reg = <0x1c>;
 131 -       };
 132 -       slot2_sgmii1: ethernet-phy@1d {
 133 -               reg = <0x1d>;
 134 -       };
 135 -       slot2_sgmii2: ethernet-phy@1e {
 136 -               reg = <0x1e>;
 137 -       };
 138 -       slot2_sgmii3: ethernet-phy@1f {
 139 +       slot1_sgmii3: ethernet-phy@1f {
 140                 reg = <0x1f>;
 141         };
 142  };
 143
 144  /* l2switch ports */
 145 -&switch_port0 {
 146 -       phy-handle = <&slot1_sgmii0>;
 147 -       phy-connection-type = "sgmii";
 148 -};
 149 +&mscc_felix_ports {
 150 +       port@0 {
 151 +               status = "okay";
 152 +               phy-handle = <&slot1_sgmii0>;
 153 +               phy-mode = "sgmii";
 154 +               managed = "in-band-status";
 155 +       };
 156
 157 -&switch_port1 {
 158 -       phy-handle = <&slot2_sgmii0>;
 159 -       phy-connection-type = "sgmii";
 160 -};
 161 +       port@1 {
 162 +               status = "okay";
 163 +               phy-handle = <&slot1_sgmii1>;
 164 +               phy-mode = "sgmii";
 165 +               managed = "in-band-status";
 166 +       };
 167
 168 -&switch_port2 {
 169 -       phy-handle = <&slot1_sgmii2>;
 170 -       phy-connection-type = "sgmii";
 171 -};
 172 +       port@2 {
 173 +               status = "okay";
 174 +               phy-handle = <&slot1_sgmii2>;
 175 +               phy-mode = "sgmii";
 176 +               managed = "in-band-status";
 177 +       };
 178
 179 -&switch_port3 {
 180 -       phy-handle = <&slot1_sgmii3>;
 181 -       phy-connection-type = "sgmii";
 182 +       port@3 {
 183 +               status = "okay";
 184 +               phy-handle = <&slot1_sgmii3>;
 185 +               phy-mode = "sgmii";
 186 +               managed = "in-band-status";
 187 +       };
 188  };
 189 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
 190 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
 191 @@ -8,41 +8,54 @@
 192
 193  &mdio_slot2 {
 194         /* 4 ports on AQR412 */
 195 -       slot2_qsgmii0: ethernet-phy@0 {
 196 +       slot2_qxgmii0: ethernet-phy@0 {
 197                 reg = <0x0>;
 198                 compatible = "ethernet-phy-ieee802.3-c45";
 199         };
 200 -       slot2_qsgmii1: ethernet-phy@1 {
 201 +
 202 +       slot2_qxgmii1: ethernet-phy@1 {
 203                 reg = <0x1>;
 204                 compatible = "ethernet-phy-ieee802.3-c45";
 205         };
 206 -       slot2_qsgmii2: ethernet-phy@2 {
 207 +
 208 +       slot2_qxgmii2: ethernet-phy@2 {
 209                 reg = <0x2>;
 210                 compatible = "ethernet-phy-ieee802.3-c45";
 211         };
 212 -       slot2_qsgmii3: ethernet-phy@3 {
 213 +
 214 +       slot2_qxgmii3: ethernet-phy@3 {
 215                 reg = <0x3>;
 216                 compatible = "ethernet-phy-ieee802.3-c45";
 217         };
 218  };
 219
 220  /* l2switch ports */
 221 -&switch_port0 {
 222 -       phy-handle = <&slot2_qsgmii0>;
 223 -       phy-connection-type = "usxgmii";
 224 -};
 225 +&mscc_felix_ports {
 226 +       port@0 {
 227 +               status = "okay";
 228 +               phy-handle = <&slot2_qxgmii0>;
 229 +               phy-mode = "usxgmii";
 230 +               managed = "in-band-status";
 231 +       };
 232
 233 -&switch_port1 {
 234 -       phy-handle = <&slot2_qsgmii1>;
 235 -       phy-connection-type = "usxgmii";
 236 -};
 237 +       port@1 {
 238 +               status = "okay";
 239 +               phy-handle = <&slot2_qxgmii1>;
 240 +               phy-mode = "usxgmii";
 241 +               managed = "in-band-status";
 242 +       };
 243
 244 -&switch_port2 {
 245 -       phy-handle = <&slot2_qsgmii2>;
 246 -       phy-connection-type = "usxgmii";
 247 -};
 248 +       port@2 {
 249 +               status = "okay";
 250 +               phy-handle = <&slot2_qxgmii2>;
 251 +               phy-mode = "usxgmii";
 252 +               managed = "in-band-status";
 253 +       };
 254
 255 -&switch_port3 {
 256 -       phy-handle = <&slot2_qsgmii3>;
 257 -       phy-connection-type = "usxgmii";
 258 +       port@3 {
 259 +               status = "okay";
 260 +               phy-handle = <&slot2_qxgmii3>;
 261 +               phy-mode = "usxgmii";
 262 +               managed = "in-band-status";
 263 +       };
 264  };
 265 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
 266 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
 267 @@ -11,34 +11,47 @@
 268         slot2_qsgmii0: ethernet-phy@8 {
 269                 reg = <0x8>;
 270         };
 271 +
 272         slot2_qsgmii1: ethernet-phy@9 {
 273                 reg = <0x9>;
 274         };
 275 +
 276         slot2_qsgmii2: ethernet-phy@a {
 277                 reg = <0xa>;
 278         };
 279 +
 280         slot2_qsgmii3: ethernet-phy@b {
 281                 reg = <0xb>;
 282         };
 283  };
 284
 285  /* l2switch ports */
 286 -&switch_port0 {
 287 -       phy-handle = <&slot2_qsgmii0>;
 288 -       phy-connection-type = "qsgmii";
 289 -};
 290 +&mscc_felix_ports {
 291 +       port@0 {
 292 +               status = "okay";
 293 +               phy-handle = <&slot2_qsgmii0>;
 294 +               phy-mode = "qsgmii";
 295 +               managed = "in-band-status";
 296 +       };
 297
 298 -&switch_port1 {
 299 -       phy-handle = <&slot2_qsgmii1>;
 300 -       phy-connection-type = "qsgmii";
 301 -};
 302 +       port@1 {
 303 +               status = "okay";
 304 +               phy-handle = <&slot2_qsgmii1>;
 305 +               phy-mode = "qsgmii";
 306 +               managed = "in-band-status";
 307 +       };
 308
 309 -&switch_port2 {
 310 -       phy-handle = <&slot2_qsgmii2>;
 311 -       phy-connection-type = "qsgmii";
 312 -};
 313 +       port@2 {
 314 +               status = "okay";
 315 +               phy-handle = <&slot2_qsgmii2>;
 316 +               phy-mode = "qsgmii";
 317 +               managed = "in-band-status";
 318 +       };
 319
 320 -&switch_port3 {
 321 -       phy-handle = <&slot2_qsgmii3>;
 322 -       phy-connection-type = "qsgmii";
 323 +       port@3 {
 324 +               status = "okay";
 325 +               phy-handle = <&slot2_qsgmii3>;
 326 +               phy-mode = "qsgmii";
 327 +               managed = "in-band-status";
 328 +       };
 329  };
 330 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
 331 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
 332 @@ -233,28 +233,34 @@
 333  };
 334
 335  /* l2switch ports */
 336 -&switch_port0 {
 337 -       phy-handle = <&qsgmii_phy1>;
 338 -       phy-connection-type = "qsgmii";
 339 -       managed = "in-band-status";
 340 -};
 341 +&mscc_felix_ports {
 342 +       port@0 {
 343 +               status = "okay";
 344 +               phy-handle = <&qsgmii_phy1>;
 345 +               phy-mode = "qsgmii";
 346 +               managed = "in-band-status";
 347 +       };
 348
 349 -&switch_port1 {
 350 -       phy-handle = <&qsgmii_phy2>;
 351 -       phy-connection-type = "qsgmii";
 352 -       managed = "in-band-status";
 353 -};
 354 +       port@1 {
 355 +               status = "okay";
 356 +               phy-handle = <&qsgmii_phy2>;
 357 +               phy-mode = "qsgmii";
 358 +               managed = "in-band-status";
 359 +       };
 360
 361 -&switch_port2 {
 362 -       phy-handle = <&qsgmii_phy3>;
 363 -       phy-connection-type = "qsgmii";
 364 -       managed = "in-band-status";
 365 -};
 366 +       port@2 {
 367 +               status = "okay";
 368 +               phy-handle = <&qsgmii_phy3>;
 369 +               phy-mode = "qsgmii";
 370 +               managed = "in-band-status";
 371 +       };
 372
 373 -&switch_port3 {
 374 -       phy-handle = <&qsgmii_phy4>;
 375 -       phy-connection-type = "qsgmii";
 376 -       managed = "in-band-status";
 377 +       port@3 {
 378 +               status = "okay";
 379 +               phy-handle = <&qsgmii_phy4>;
 380 +               phy-mode = "qsgmii";
 381 +               managed = "in-band-status";
 382 +       };
 383  };
 384
 385  &sai4 {
 386 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
 387 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
 388 @@ -774,30 +774,39 @@
 389                                 clocks = <&clockgen 4 0>;
 390                                 little-endian;
 391                         };
 392 -                       switch@0,5 {
 393 +
 394 +                       ethernet-switch@0,5 {
 395                                 reg = <0x000500 0 0 0 0>;
 396                                 /* IEP INT_B */
 397                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 398
 399 -                               ports {
 400 +                               mscc_felix_ports: ports {
 401                                         #address-cells = <1>;
 402                                         #size-cells = <0>;
 403
 404                                         /* external ports */
 405 -                                       switch_port0: port@0 {
 406 +                                       mscc_felix_port0: port@0 {
 407                                                 reg = <0>;
 408 +                                               status = "disabled";
 409                                         };
 410 -                                       switch_port1: port@1 {
 411 +
 412 +                                       mscc_felix_port1: port@1 {
 413                                                 reg = <1>;
 414 +                                               status = "disabled";
 415                                         };
 416 -                                       switch_port2: port@2 {
 417 +
 418 +                                       mscc_felix_port2: port@2 {
 419                                                 reg = <2>;
 420 +                                               status = "disabled";
 421                                         };
 422 -                                       switch_port3: port@3 {
 423 +
 424 +                                       mscc_felix_port3: port@3 {
 425                                                 reg = <3>;
 426 +                                               status = "disabled";
 427                                         };
 428 +
 429                                         /* internal to-cpu ports */
 430 -                                       port@4 {
 431 +                                       mscc_felix_port4: port@4 {
 432                                                 reg = <4>;
 433                                                 ethernet = <&enetc_port2>;
 434                                                 phy-mode = "gmii";
 435 @@ -807,7 +816,8 @@
 436                                                         full-duplex;
 437                                                 };
 438                                         };
 439 -                                       port@5 {
 440 +
 441 +                                       mscc_felix_port5: port@5 {
 442                                                 reg = <5>;
 443                                                 phy-mode = "gmii";
 444                                                 status = "disabled";
 445 @@ -819,6 +829,7 @@
 446                                         };
 447                                 };
 448                         };
 449 +
 450                         enetc_port3: ethernet@0,6 {
 451                                 compatible = "fsl,enetc";
 452                                 reg = <0x000600 0 0 0 0>;