target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch

   1 From c9be87f17c64d08c06e4858589a0014f73868867 Mon Sep 17 00:00:00 2001
   2 From: Pankaj Bansal <pankaj.bansal@nxp.com>
   3 Date: Thu, 28 Feb 2019 17:28:36 +0530
   4 Subject: [PATCH] arm64: dts: lx2160aqds: Add mdio mux nodes
   5
   6 The two external MDIO buses used to communicate with phy devices that are
   7 external to SOC are muxed in LX2160AQDS board.
   8 These buses can be routed to any one of the eight IO slots on LX2160AQDS
   9 board depending on value in fpga register 0x54.
  10 Additionally the external MDIO1 is used to communicate to the onboard
  11 RGMII phy devices.
  12 The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is
  13 controlled by bits 4-7 of fpga register.
  14
  15 Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
  16 ---
  17  arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++++++
  18  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |   8 ++
  19  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi    |  24 ++--
  20  3 files changed, 165 insertions(+), 12 deletions(-)
  21
  22 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
  23 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
  24 @@ -29,6 +29,130 @@
  25                 regulator-boot-on;
  26                 regulator-always-on;
  27         };
  28 +
  29 +       mdio-mux-1 {
  30 +               compatible = "mdio-mux-multiplexer";
  31 +               mux-controls = <&mux 0>;
  32 +               mdio-parent-bus = <&emdio1>;
  33 +               #address-cells=<1>;
  34 +               #size-cells = <0>;
  35 +
  36 +               mdio@0 { /* On-board PHY #1 RGMI1*/
  37 +                       reg = <0x00>;
  38 +                       #address-cells = <1>;
  39 +                       #size-cells = <0>;
  40 +               };
  41 +
  42 +               mdio@8 { /* On-board PHY #2 RGMI2*/
  43 +                       reg = <0x8>;
  44 +                       #address-cells = <1>;
  45 +                       #size-cells = <0>;
  46 +               };
  47 +
  48 +               mdio@18 { /* Slot #1 */
  49 +                       reg = <0x18>;
  50 +                       #address-cells = <1>;
  51 +                       #size-cells = <0>;
  52 +               };
  53 +
  54 +               mdio@19 { /* Slot #2 */
  55 +                       reg = <0x19>;
  56 +                       #address-cells = <1>;
  57 +                       #size-cells = <0>;
  58 +               };
  59 +
  60 +               mdio@1a { /* Slot #3 */
  61 +                       reg = <0x1a>;
  62 +                       #address-cells = <1>;
  63 +                       #size-cells = <0>;
  64 +               };
  65 +
  66 +               mdio@1b { /* Slot #4 */
  67 +                       reg = <0x1b>;
  68 +                       #address-cells = <1>;
  69 +                       #size-cells = <0>;
  70 +               };
  71 +
  72 +               mdio@1c { /* Slot #5 */
  73 +                       reg = <0x1c>;
  74 +                       #address-cells = <1>;
  75 +                       #size-cells = <0>;
  76 +               };
  77 +
  78 +               mdio@1d { /* Slot #6 */
  79 +                       reg = <0x1d>;
  80 +                       #address-cells = <1>;
  81 +                       #size-cells = <0>;
  82 +               };
  83 +
  84 +               mdio@1e { /* Slot #7 */
  85 +                       reg = <0x1e>;
  86 +                       #address-cells = <1>;
  87 +                       #size-cells = <0>;
  88 +               };
  89 +
  90 +               mdio@1f { /* Slot #8 */
  91 +                       reg = <0x1f>;
  92 +                       #address-cells = <1>;
  93 +                       #size-cells = <0>;
  94 +               };
  95 +       };
  96 +
  97 +       mdio-mux-2 {
  98 +               compatible = "mdio-mux-multiplexer";
  99 +               mux-controls = <&mux 1>;
 100 +               mdio-parent-bus = <&emdio2>;
 101 +               #address-cells=<1>;
 102 +               #size-cells = <0>;
 103 +
 104 +               mdio@0 { /* Slot #1 (secondary EMI) */
 105 +                       reg = <0x00>;
 106 +                       #address-cells = <1>;
 107 +                       #size-cells = <0>;
 108 +               };
 109 +
 110 +               mdio@1 { /* Slot #2 (secondary EMI) */
 111 +                       reg = <0x01>;
 112 +                       #address-cells = <1>;
 113 +                       #size-cells = <0>;
 114 +               };
 115 +
 116 +               mdio@2 { /* Slot #3 (secondary EMI) */
 117 +                       reg = <0x02>;
 118 +                       #address-cells = <1>;
 119 +                       #size-cells = <0>;
 120 +               };
 121 +
 122 +               mdio@3 { /* Slot #4 (secondary EMI) */
 123 +                       reg = <0x03>;
 124 +                       #address-cells = <1>;
 125 +                       #size-cells = <0>;
 126 +               };
 127 +
 128 +               mdio@4 { /* Slot #5 (secondary EMI) */
 129 +                       reg = <0x04>;
 130 +                       #address-cells = <1>;
 131 +                       #size-cells = <0>;
 132 +               };
 133 +
 134 +               mdio@5 { /* Slot #6 (secondary EMI) */
 135 +                       reg = <0x05>;
 136 +                       #address-cells = <1>;
 137 +                       #size-cells = <0>;
 138 +               };
 139 +
 140 +               mdio@6 { /* Slot #7 (secondary EMI) */
 141 +                       reg = <0x06>;
 142 +                       #address-cells = <1>;
 143 +                       #size-cells = <0>;
 144 +               };
 145 +
 146 +               mdio@7 { /* Slot #8 (secondary EMI) */
 147 +                       reg = <0x07>;
 148 +                       #address-cells = <1>;
 149 +                       #size-cells = <0>;
 150 +               };
 151 +       };
 152  };
 153
 154  &crypto {
 155 @@ -71,6 +195,14 @@
 156         };
 157  };
 158
 159 +&emdio1 {
 160 +       status = "okay";
 161 +};
 162 +
 163 +&emdio2 {
 164 +       status = "okay";
 165 +};
 166 +
 167  &esdhc0 {
 168         status = "okay";
 169  };
 170 @@ -82,6 +214,19 @@
 171  &i2c0 {
 172         status = "okay";
 173
 174 +       fpga@66 {
 175 +               compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
 176 +                            "simple-mfd";
 177 +               reg = <0x66>;
 178 +
 179 +               mux: mux-controller {
 180 +                       compatible = "reg-mux";
 181 +                       #mux-control-cells = <1>;
 182 +                       mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
 183 +                                       <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
 184 +               };
 185 +       };
 186 +
 187         i2c-mux@77 {
 188                 compatible = "nxp,pca9547";
 189                 reg = <0x77>;
 190 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
 191 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
 192 @@ -35,6 +35,14 @@
 193         status = "okay";
 194  };
 195
 196 +&emdio1 {
 197 +       status = "okay";
 198 +};
 199 +
 200 +&emdio2 {
 201 +       status = "okay";
 202 +};
 203 +
 204  &esdhc0 {
 205         sd-uhs-sdr104;
 206         sd-uhs-sdr50;
 207 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
 208 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
 209 @@ -478,26 +478,26 @@
 210                         little-endian;
 211                 };
 212
 213 -               /* TODO: WRIOP (CCSR?) */
 214 -               emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
 215 +               /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
 216 +               emdio1: mdio@8b96000 {
 217                         compatible = "fsl,fman-memac-mdio";
 218 -                       reg = <0x0 0x8B96000 0x0 0x1000>;
 219 -                       device_type = "mdio";                   /* TODO: is this necessary? */
 220 -                       little-endian;  /* force the driver in LE mode */
 221 -
 222 -                       /* Not necessary on the QDS, but needed on the RDB */
 223 +                       reg = <0x0 0x8b96000 0x0 0x1000>;
 224 +                       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227 +                       little-endian;  /* force the driver in LE mode */
 228 +                       status = "disabled";
 229                 };
 230
 231 -               emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
 232 +               /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
 233 +               emdio2: mdio@8b97000 {
 234                         compatible = "fsl,fman-memac-mdio";
 235 -                       reg = <0x0 0x8B97000 0x0 0x1000>;
 236 -                       device_type = "mdio";                   /* TODO: is this necessary? */
 237 -                       little-endian;  /* force the driver in LE mode */
 238 -
 239 +                       reg = <0x0 0x8b97000 0x0 0x1000>;
 240 +                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243 +                       little-endian;  /* force the driver in LE mode */
 244 +                       status = "disabled";
 245                 };
 246
 247                 pcs_mdio1: mdio@0x8c07000 {