target/linux/layerscape/patches-5.4/302-dts-0010-arm64-dts-ls208xa-accumulated-change-to-ls208xa-boar.patch

   1 From 9d8de47b617baa4fa92d9a1502904c0373f80384 Mon Sep 17 00:00:00 2001
   2 From: Li Yang <leoyang.li@nxp.com>
   3 Date: Thu, 2 May 2019 16:12:40 -0500
   4 Subject: [PATCH] arm64: dts: ls208xa: accumulated change to ls208xa boards
   5
   6 commit 46123df3a174f0d76c8b954a0386e64841453836
   7 Author: Florinel Iordache <florinel.iordache@nxp.com>
   8 Date:   Thu Aug 9 12:29:18 2018 +0300
   9
  10     arm64: dts: updates for Unified Backplane driver
  11
  12     Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
  13
  14 commit 76a741dbb9b93ea9ab2f6122b8df5bc4f0db7676
  15 Author: Nipun Gupta <nipun.gupta@nxp.com>
  16 Date:   Sat Apr 28 00:20:16 2018 +0530
  17
  18     arm64: dts: ls208x: add dma-cohernet property in fsl-mc node
  19
  20     Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
  21
  22 commit f6309e9dc8e0c6171a43fd6759123b5de1c574aa
  23 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
  24 Date:   Mon Apr 2 16:27:23 2018 +0800
  25
  26     arm64: dts: ls208xa: add dts entry for A-010650
  27
  28     Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
  29
  30 commit 8c37bad2038a210a4f0a369fd946aaae4317eac4
  31 Author: Nipun Gupta <nipun.gupta@nxp.com>
  32 Date:   Fri Apr 20 17:14:10 2018 +0530
  33
  34     arm64: dts: ls208x: add dma ranges property
  35
  36     Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
  37
  38 commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
  39 Author: Changming Huang <jerry.huang@nxp.com>
  40 Date:   Wed Apr 19 12:49:50 2017 +0800
  41
  42     arm/arm64: dts: Add property snps incr burst type adjustment for
  43 INCR burst type for dwc3
  44
  45     Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
  46     Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  47
  48 commit dbb65ea8ee1d46067e756c6d64c7fe66a0058f49
  49 Author: Pankaj Bansal <pankaj.bansal@nxp.com>
  50 Date:   Mon Mar 5 12:37:04 2018 +0530
  51
  52     arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.
  53
  54     NXP Erratum A008585 affects A57 core cluster used in LS2085rev1.
  55     However this problem has been fixed in A72 core cluster used in
  56 LS2088.
  57     Therefore remove the erratum from LS2088A. Keeping it only in
  58 LS2085.
  59
  60     Cc: <stable@vger.kernel.org> # 4.14
  61     Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
  62     Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com>
  63     Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
  64
  65 commit 85f41b0f6abe6b9d7d303790bb3712ed559890e9
  66 Author: Nipun Gupta <nipun.gupta@nxp.com>
  67 Date:   Mon Feb 26 10:39:54 2018 +0530
  68
  69     arm64: dts: ls208xa: add dma coherent property in smmu node
  70
  71     Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
  72
  73 commit e910d8b78b823a625451b1da7ae7499dadde2ae9
  74 Author: Suresh Gupta <suresh.gupta@nxp.com>
  75 Date:   Thu Feb 1 23:49:56 2018 +0530
  76
  77     arm64: dts: freescale: ls208xa: Modify DT nodes for qspi
  78
  79     Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
  80
  81 commit 7654ef78c8c85de3a43dfa0dffd572d589ea1332
  82 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
  83 Date:   Wed Nov 1 10:34:04 2017 +0800
  84
  85     arm64: dts: ls208xa: correct the i2c clock to 1/2 platform pll
  86
  87     Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
  88
  89 commit efdb129228baa6a999c06072338b979d783d7b60
  90 Author: Bharat Bhushan <Bharat.Bhushan@nxp.com>
  91 Date:   Thu Aug 31 14:45:02 2017 +0530
  92
  93     arm64: dts: ls208xa: Add iommu-map property for pci
  94
  95     This patch adds iommu-map property for PCIe, which enables
  96     SMMU for these devices on LS208xA devices.
  97
  98     Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
  99
 100 commit 45af5d025eafaf4a85000e16e5f47992de663ff6
 101 Author: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
 102 Date:   Mon Aug 21 11:46:59 2017 +0300
 103
 104     arm64: dts: ls2088a: update backplane support with dpmac connections
 105
 106     Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
 107
 108 commit b2ede6c088a883fceb348e8659253b2c7cdeeff8
 109 Author: Santan Kumar <santan.kumar@nxp.com>
 110 Date:   Thu Jun 22 13:04:00 2017 +0530
 111
 112     arm64: dts: ls2088ardb: Update nodes for QSPI
 113
 114     -As per board design, different QSPI flash is connected on
 115       boards, hence change QSPI flash node from s25fl256s1 to s25fs512ss
 116 in
 117       device tree.
 118     -Enable fast-read support in QSPI node.
 119
 120     Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
 121
 122 commit d5324a75c56e9f9210113e51cffa846a86b50fbd
 123 Author: Santan Kumar <santan.kumar@nxp.com>
 124 Date:   Mon Jun 19 15:26:03 2017 +0530
 125
 126     arm64: dts: ls2081ardb: Update nodes for QSPI, SATA, INA220
 127
 128     Update ls2081ardb.dts for below nodes:
 129      -As per updated board design, different QSPI flash is connected on
 130       boards, hence change QSPI flash node from n25q512a to s25fs512ss
 131 in
 132       device tree.
 133      -Enable dual flash support in QSPI node.
 134      -Add DTS node for INA220.
 135      -Enable SATA node.
 136
 137     Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
 138     Signed-off-by: Tao Yang <b31903@freescale.com>
 139     Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
 140
 141 commit 43d506fa19e1e50e4c2e4f9689ad3c60d9a06d71
 142 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
 143 Date:   Thu May 11 08:42:19 2017 +0800
 144
 145     arm64: dts: ls208x: add property for PCA954x Mux device
 146
 147     PCA954x Mux device should never be turned-off after power-on. if
 148     device tree contians "i2c-mux-never-disable" property for pca954x
 149     device node, it can ensure that skip disabling PCA954x Mux device.
 150
 151     Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
 152
 153 commit 6d3a96446a7ffccb0b9936b616d855c8d5572bce
 154 Author: Bogdan Purcareata <bogdan.purcareata@nxp.com>
 155 Date:   Wed May 3 14:26:35 2017 +0000
 156
 157     arm64: dts: fsl/ls1088,ls208x: Add mdio and phy nodes
 158
 159     Add mdio and phy nodes for the following FSL platforms:
 160     - LS1088A RDB
 161     - LS2080A QDS & RDB
 162     - LS2088A QDS, RDB & simu
 163
 164     Contains contributions from patches by the following authors:
 165     Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
 166     Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
 167     Signed-off-by: Pratiyush Mohan Srivastava
 168 <pratiyush.srivastava@nxp.com>
 169     Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
 170     Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
 171     Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
 172     Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
 173     Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
 174     Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
 175     Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
 176
 177 commit 0443625ea24bc4ea315c30b718712254c588bd18
 178 Author: Suresh Gupta <suresh.gupta@nxp.com>
 179 Date:   Fri May 5 13:54:22 2017 +0530
 180
 181     arm64: dts: ls208xa: Add QSPI Flash node for RDB
 182
 183     This is temporary patch, will rewrite for open source
 184
 185     Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
 186
 187 commit ed0ce1d49aa72d12ea54f82d3771a377c68af37e
 188 Author: Priyanka Jain <priyanka.jain@nxp.com>
 189 Date:   Thu Apr 13 16:49:40 2017 +0530
 190
 191     arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
 192
 193     This patch add support for NXP LS2081ARDB board which has
 194     LS2081A SoC.
 195
 196     LS2081A SoC is 40-pin derivative of LS2088A SoC
 197     So, from functional perspective both are same.
 198     Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
 199
 200     Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
 201
 202 commit e4fb842554a5e7b8c3f6e3c243222dbe4515aee3
 203 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
 204 Date:   Thu Apr 27 15:01:54 2017 +0800
 205
 206     arm64: dts: ls208xa: add ftm0 nodes
 207
 208     Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
 209
 210 commit 64c3e2c3a7ddc89c3c23c012ee364f2c014524d2
 211 Author: costi <constantin.tudor@freescale.com>
 212 Date:   Fri Mar 3 18:08:28 2017 +0200
 213
 214     arm64: dts: fsl-ls2088: Add mdio/phy devices
 215
 216     Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
 217
 218 commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
 219 Author: Po Liu <po.liu@nxp.com>
 220 Date:   Fri Sep 30 17:11:36 2016 +0800
 221
 222     arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
 223
 224     Some platforms(NXP Layerscape for example) aer/pme interrupts was
 225 not
 226     MSI/MSI-X/INTx but using interrupt line independently. This patch
 227     add "aer", "pme" interrupt-names for aer/pme interrupt.
 228
 229     With the interrupt-names "aer", "pme" code could probe aer/pme
 230 interrupt
 231     line for pcie root port, replace the aer/pme interrupt service irqs.
 232
 233     This is intend to fixup the Layerscape platforms which aer/pmes
 234 interrupts
 235     was not MSI/MSI-X/INTx, but using interrupt line independently.
 236
 237     Since the interrupt-names "intr" never been used. Remove it.
 238
 239     Signed-off-by: Po Liu <po.liu@nxp.com>
 240     Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
 241
 242 commit 64d859836d3d194e8bc926bb951fd21859689824
 243 Author: Nipun Gupta <nipun.gupta@nxp.com>
 244 Date:   Mon Dec 5 05:20:51 2016 +0530
 245
 246     arm64: dts: ls208xa: Comply with the new iommu binding for fsl_mc
 247
 248     fsl-mc bus support the new iommu-map property. Comply to this
 249 binding
 250     for fsl_mc bus.
 251
 252     Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
 253 ---
 254  arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  |  62 +++++++++
 255  arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts  |  80 +++++++++++
 256  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi     |  12 ++
 257  arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts  | 120 ++++++++++++++++
 258  arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts  |  80 +++++++++++
 259  arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi |   1 +
 260  arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi |  11 +-
 261  arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi     | 155 +++++++++++++++++++--
 262  8 files changed, 505 insertions(+), 16 deletions(-)
 263
 264 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
 265 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
 266 @@ -23,3 +23,65 @@
 267                 stdout-path = "serial0:115200n8";
 268         };
 269  };
 270 +
 271 +&ifc {
 272 +       boardctrl: board-control@3,0 {
 273 +               #address-cells = <1>;
 274 +               #size-cells = <1>;
 275 +               compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
 276 +               reg = <3 0 0x300>;              /* TODO check address */
 277 +               ranges = <0 3 0 0x300>;
 278 +
 279 +               mdio_mux_emi1 {
 280 +                       compatible = "mdio-mux-mmioreg", "mdio-mux";
 281 +                       mdio-parent-bus = <&emdio1>;
 282 +                       reg = <0x54 1>;         /* BRDCFG4 */
 283 +                       mux-mask = <0xe0>;      /* EMI1_MDIO */
 284 +
 285 +                       #address-cells=<1>;
 286 +                       #size-cells = <0>;
 287 +
 288 +                       /* Child MDIO buses, one for each riser card:
 289 +                        * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
 290 +                        * VSC8234 PHYs on the riser cards.
 291 +                        */
 292 +
 293 +                       mdio_mux3: mdio@60 {
 294 +                               reg = <0x60>;
 295 +                               #address-cells = <1>;
 296 +                               #size-cells = <0>;
 297 +
 298 +                               mdio0_phy12: mdio_phy0@1c {
 299 +                                       reg = <0x1c>;
 300 +                                       phy-connection-type = "sgmii";
 301 +                               };
 302 +                               mdio0_phy13: mdio_phy1@1d {
 303 +                                       reg = <0x1d>;
 304 +                                       phy-connection-type = "sgmii";
 305 +                               };
 306 +                               mdio0_phy14: mdio_phy2@1e {
 307 +                                       reg = <0x1e>;
 308 +                                       phy-connection-type = "sgmii";
 309 +                               };
 310 +                               mdio0_phy15: mdio_phy3@1f {
 311 +                                       reg = <0x1f>;
 312 +                                       phy-connection-type = "sgmii";
 313 +                               };
 314 +                       };
 315 +               };
 316 +       };
 317 +};
 318 +
 319 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
 320 +&dpmac9 {
 321 +       phy-handle = <&mdio0_phy12>;
 322 +};
 323 +&dpmac10 {
 324 +       phy-handle = <&mdio0_phy13>;
 325 +};
 326 +&dpmac11 {
 327 +       phy-handle = <&mdio0_phy14>;
 328 +};
 329 +&dpmac12 {
 330 +       phy-handle = <&mdio0_phy15>;
 331 +};
 332 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
 333 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
 334 @@ -23,3 +23,83 @@
 335                 stdout-path = "serial1:115200n8";
 336         };
 337  };
 338 +
 339 +&emdio1 {
 340 +       status = "disabled";
 341 +       /* CS4340 PHYs */
 342 +       mdio1_phy1: emdio1_phy@1 {
 343 +               reg = <0x10>;
 344 +               phy-connection-type = "xfi";
 345 +       };
 346 +       mdio1_phy2: emdio1_phy@2 {
 347 +               reg = <0x11>;
 348 +               phy-connection-type = "xfi";
 349 +       };
 350 +       mdio1_phy3: emdio1_phy@3 {
 351 +               reg = <0x12>;
 352 +               phy-connection-type = "xfi";
 353 +       };
 354 +       mdio1_phy4: emdio1_phy@4 {
 355 +               reg = <0x13>;
 356 +               phy-connection-type = "xfi";
 357 +       };
 358 +};
 359 +
 360 +&emdio2 {
 361 +       /* AQR405 PHYs */
 362 +       mdio2_phy1: emdio2_phy@1 {
 363 +               compatible = "ethernet-phy-ieee802.3-c45";
 364 +               interrupts = <0 1 0x4>; /* Level high type */
 365 +               reg = <0x0>;
 366 +               phy-connection-type = "xfi";
 367 +       };
 368 +       mdio2_phy2: emdio2_phy@2 {
 369 +               compatible = "ethernet-phy-ieee802.3-c45";
 370 +               interrupts = <0 2 0x4>; /* Level high type */
 371 +               reg = <0x1>;
 372 +               phy-connection-type = "xfi";
 373 +       };
 374 +       mdio2_phy3: emdio2_phy@3 {
 375 +               compatible = "ethernet-phy-ieee802.3-c45";
 376 +               interrupts = <0 4 0x4>; /* Level high type */
 377 +               reg = <0x2>;
 378 +               phy-connection-type = "xfi";
 379 +       };
 380 +       mdio2_phy4: emdio2_phy@4 {
 381 +               compatible = "ethernet-phy-ieee802.3-c45";
 382 +               interrupts = <0 5 0x4>; /* Level high type */
 383 +               reg = <0x3>;
 384 +               phy-connection-type = "xfi";
 385 +       };
 386 +};
 387 +
 388 +/* Update DPMAC connections to external PHYs, under the assumption of
 389 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
 390 + */
 391 +/* Leave Cortina nodes commented out until driver is integrated
 392 + *&dpmac1 {
 393 + *     phy-handle = <&mdio1_phy1>;
 394 + *};
 395 + *&dpmac2 {
 396 + *     phy-handle = <&mdio1_phy2>;
 397 + *};
 398 + *&dpmac3 {
 399 + *     phy-handle = <&mdio1_phy3>;
 400 + *};
 401 + *&dpmac4 {
 402 + *     phy-handle = <&mdio1_phy4>;
 403 + *};
 404 + */
 405 +
 406 +&dpmac5 {
 407 +       phy-handle = <&mdio2_phy1>;
 408 +};
 409 +&dpmac6 {
 410 +       phy-handle = <&mdio2_phy2>;
 411 +};
 412 +&dpmac7 {
 413 +       phy-handle = <&mdio2_phy3>;
 414 +};
 415 +&dpmac8 {
 416 +       phy-handle = <&mdio2_phy4>;
 417 +};
 418 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
 419 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
 420 @@ -118,6 +118,18 @@
 421         };
 422  };
 423
 424 +&timer {
 425 +       fsl,erratum-a008585;
 426 +};
 427 +
 428 +&usb0 {
 429 +       snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 430 +};
 431 +
 432 +&usb1 {
 433 +       snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 434 +};
 435 +
 436  &pcie1 {
 437         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 438                0x10 0x00000000 0x0 0x00002000>; /* configuration space */
 439 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
 440 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
 441 @@ -22,3 +22,123 @@
 442                 stdout-path = "serial0:115200n8";
 443         };
 444  };
 445 +
 446 +&ifc {
 447 +       boardctrl: board-control@3,0 {
 448 +               #address-cells = <1>;
 449 +               #size-cells = <1>;
 450 +               compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
 451 +               reg = <3 0 0x300>;              /* TODO check address */
 452 +               ranges = <0 3 0 0x300>;
 453 +
 454 +               mdio_mux_emi1 {
 455 +                       compatible = "mdio-mux-mmioreg", "mdio-mux";
 456 +                       mdio-parent-bus = <&emdio1>;
 457 +                       reg = <0x54 1>;         /* BRDCFG4 */
 458 +                       mux-mask = <0xe0>;      /* EMI1_MDIO */
 459 +
 460 +                       #address-cells=<1>;
 461 +                       #size-cells = <0>;
 462 +
 463 +                       /* Child MDIO buses, one for each riser card:
 464 +                        * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
 465 +                        * VSC8234 PHYs on the riser cards.
 466 +                        */
 467 +
 468 +                       mdio_mux3: mdio@60 {
 469 +                               reg = <0x60>;
 470 +                               #address-cells = <1>;
 471 +                               #size-cells = <0>;
 472 +
 473 +                               mdio0_phy12: mdio_phy0@1c {
 474 +                                       reg = <0x1c>;
 475 +                                       phy-connection-type = "sgmii";
 476 +                               };
 477 +                               mdio0_phy13: mdio_phy1@1d {
 478 +                                       reg = <0x1d>;
 479 +                                       phy-connection-type = "sgmii";
 480 +                               };
 481 +                               mdio0_phy14: mdio_phy2@1e {
 482 +                                       reg = <0x1e>;
 483 +                                       phy-connection-type = "sgmii";
 484 +                               };
 485 +                               mdio0_phy15: mdio_phy3@1f {
 486 +                                       reg = <0x1f>;
 487 +                                       phy-connection-type = "sgmii";
 488 +                               };
 489 +                       };
 490 +               };
 491 +       };
 492 +};
 493 +
 494 +&pcs_mdio1 {
 495 +               pcs_phy1: ethernet-phy@0 {
 496 +               backplane-mode = "10gbase-kr";
 497 +               compatible = "ethernet-phy-ieee802.3-c45";
 498 +               reg = <0x0>;
 499 +               fsl,lane-handle = <&serdes1>;
 500 +               fsl,lane-reg = <0x9C0 0x40>;/* lane H */
 501 +       };
 502 +};
 503 +
 504 +&pcs_mdio2 {
 505 +               pcs_phy2: ethernet-phy@0 {
 506 +               backplane-mode = "10gbase-kr";
 507 +               compatible = "ethernet-phy-ieee802.3-c45";
 508 +               reg = <0x0>;
 509 +               fsl,lane-handle = <&serdes1>;
 510 +               fsl,lane-reg = <0x980 0x40>;/* lane G */
 511 +       };
 512 +};
 513 +
 514 +&pcs_mdio3 {
 515 +               pcs_phy3: ethernet-phy@0 {
 516 +               backplane-mode = "10gbase-kr";
 517 +               compatible = "ethernet-phy-ieee802.3-c45";
 518 +               reg = <0x0>;
 519 +               fsl,lane-handle = <&serdes1>;
 520 +               fsl,lane-reg = <0x940 0x40>;/* lane F */
 521 +       };
 522 +};
 523 +
 524 +&pcs_mdio4 {
 525 +               pcs_phy4: ethernet-phy@0 {
 526 +               backplane-mode = "10gbase-kr";
 527 +               compatible = "ethernet-phy-ieee802.3-c45";
 528 +               reg = <0x0>;
 529 +               fsl,lane-handle = <&serdes1>;
 530 +               fsl,lane-reg = <0x900 0x40>;/* lane E */
 531 +       };
 532 +};
 533 +
 534 +/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
 535 + * &dpmac1 {
 536 + *     phy-handle = <&pcs_phy1>;
 537 + * };
 538 + *
 539 + * &dpmac2 {
 540 + *     phy-handle = <&pcs_phy2>;
 541 + * };
 542 + *
 543 + * &dpmac3 {
 544 + *     phy-handle = <&pcs_phy3>;
 545 + * };
 546 + *
 547 + * &dpmac4 {
 548 + *     phy-handle = <&pcs_phy4>;
 549 + * };
 550 + */
 551 +
 552 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
 553 +&dpmac9 {
 554 +       phy-handle = <&mdio0_phy12>;
 555 +};
 556 +&dpmac10 {
 557 +       phy-handle = <&mdio0_phy13>;
 558 +};
 559 +&dpmac11 {
 560 +       phy-handle = <&mdio0_phy14>;
 561 +};
 562 +&dpmac12 {
 563 +       phy-handle = <&mdio0_phy15>;
 564 +};
 565 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
 566 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
 567 @@ -22,3 +22,83 @@
 568                 stdout-path = "serial1:115200n8";
 569         };
 570  };
 571 +
 572 +&emdio1 {
 573 +       status = "disabled";
 574 +       /* CS4340 PHYs */
 575 +       mdio1_phy1: emdio1_phy@1 {
 576 +               reg = <0x10>;
 577 +               phy-connection-type = "xfi";
 578 +       };
 579 +       mdio1_phy2: emdio1_phy@2 {
 580 +               reg = <0x11>;
 581 +               phy-connection-type = "xfi";
 582 +       };
 583 +       mdio1_phy3: emdio1_phy@3 {
 584 +               reg = <0x12>;
 585 +               phy-connection-type = "xfi";
 586 +       };
 587 +       mdio1_phy4: emdio1_phy@4 {
 588 +               reg = <0x13>;
 589 +               phy-connection-type = "xfi";
 590 +       };
 591 +};
 592 +
 593 +&emdio2 {
 594 +       /* AQR405 PHYs */
 595 +       mdio2_phy1: emdio2_phy@1 {
 596 +               compatible = "ethernet-phy-ieee802.3-c45";
 597 +               interrupts = <0 1 0x4>; /* Level high type */
 598 +               reg = <0x0>;
 599 +               phy-connection-type = "xfi";
 600 +       };
 601 +       mdio2_phy2: emdio2_phy@2 {
 602 +               compatible = "ethernet-phy-ieee802.3-c45";
 603 +               interrupts = <0 2 0x4>; /* Level high type */
 604 +               reg = <0x1>;
 605 +               phy-connection-type = "xfi";
 606 +       };
 607 +       mdio2_phy3: emdio2_phy@3 {
 608 +               compatible = "ethernet-phy-ieee802.3-c45";
 609 +               interrupts = <0 4 0x4>; /* Level high type */
 610 +               reg = <0x2>;
 611 +               phy-connection-type = "xfi";
 612 +       };
 613 +       mdio2_phy4: emdio2_phy@4 {
 614 +               compatible = "ethernet-phy-ieee802.3-c45";
 615 +               interrupts = <0 5 0x4>; /* Level high type */
 616 +               reg = <0x3>;
 617 +               phy-connection-type = "xfi";
 618 +       };
 619 +};
 620 +
 621 +/* Update DPMAC connections to external PHYs, under the assumption of
 622 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
 623 + */
 624 +/* Leave Cortina PHYs commented out until proper driver is integrated
 625 + *&dpmac1 {
 626 + *     phy-handle = <&mdio1_phy1>;
 627 + *};
 628 + *&dpmac2 {
 629 + *     phy-handle = <&mdio1_phy2>;
 630 + *};
 631 + *&dpmac3 {
 632 + *     phy-handle = <&mdio1_phy3>;
 633 + *};
 634 + *&dpmac4 {
 635 + *     phy-handle = <&mdio1_phy4>;
 636 + *};
 637 + */
 638 +
 639 +&dpmac5 {
 640 +       phy-handle = <&mdio2_phy1>;
 641 +};
 642 +&dpmac6 {
 643 +       phy-handle = <&mdio2_phy2>;
 644 +};
 645 +&dpmac7 {
 646 +       phy-handle = <&mdio2_phy3>;
 647 +};
 648 +&dpmac8 {
 649 +       phy-handle = <&mdio2_phy4>;
 650 +};
 651 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
 652 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
 653 @@ -129,6 +129,7 @@
 654
 655  &qspi {
 656         status = "okay";
 657 +       fsl,qspi-has-second-chip;
 658         flash0: s25fl256s1@0 {
 659                 #address-cells = <1>;
 660                 #size-cells = <1>;
 661 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
 662 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
 663 @@ -49,6 +49,7 @@
 664                 reg = <0x75>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667 +               i2c-mux-never-disable;
 668                 i2c@1 {
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671 @@ -108,7 +109,15 @@
 672  };
 673
 674  &qspi {
 675 -       status = "disabled";
 676 +       status = "okay";
 677 +       flash0: s25fs512s@0 {
 678 +               #address-cells = <1>;
 679 +               #size-cells = <1>;
 680 +               compatible = "spansion,m25p80";
 681 +               m25p,fast-read;
 682 +               spi-max-frequency = <20000000>;
 683 +               reg = <0>;
 684 +       };
 685  };
 686
 687  &sata0 {
 688 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
 689 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
 690 @@ -114,13 +114,12 @@
 691                 };
 692         };
 693
 694 -       timer {
 695 +       timer: timer {
 696                 compatible = "arm,armv8-timer";
 697                 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
 698                              <1 14 4>, /* Physical Non-Secure PPI, active-low */
 699                              <1 11 4>, /* Virtual PPI, active-low */
 700                              <1 10 4>; /* Hypervisor PPI, active-low */
 701 -               fsl,erratum-a008585;
 702         };
 703
 704         pmu {
 705 @@ -560,15 +559,126 @@
 706                         #interrupt-cells = <2>;
 707                 };
 708
 709 +               /* TODO: WRIOP (CCSR?) */
 710 +               emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
 711 +                                         * E-MDIO1: 0x1_6000
 712 +                                         */
 713 +                       compatible = "fsl,fman-memac-mdio";
 714 +                       reg = <0x0 0x8B96000 0x0 0x1000>;
 715 +                       device_type = "mdio";   /* TODO: is this necessary? */
 716 +                       little-endian;  /* force the driver in LE mode */
 717 +
 718 +                       /* Not necessary on the QDS, but needed on the RDB */
 719 +                       #address-cells = <1>;
 720 +                       #size-cells = <0>;
 721 +               };
 722 +
 723 +               emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
 724 +                                         * E-MDIO2: 0x1_7000
 725 +                                         */
 726 +                       compatible = "fsl,fman-memac-mdio";
 727 +                       reg = <0x0 0x8B97000 0x0 0x1000>;
 728 +                       device_type = "mdio";   /* TODO: is this necessary? */
 729 +                       little-endian;  /* force the driver in LE mode */
 730 +
 731 +                       #address-cells = <1>;
 732 +                       #size-cells = <0>;
 733 +               };
 734 +
 735 +               pcs_mdio1: mdio@0x8c07000 {
 736 +                       compatible = "fsl,fman-memac-mdio";
 737 +                       reg = <0x0 0x8c07000 0x0 0x1000>;
 738 +                       device_type = "mdio";
 739 +                       little-endian;
 740 +
 741 +                       #address-cells = <1>;
 742 +                       #size-cells = <0>;
 743 +               };
 744 +
 745 +               pcs_mdio2: mdio@0x8c0b000 {
 746 +                       compatible = "fsl,fman-memac-mdio";
 747 +                       reg = <0x0 0x8c0b000 0x0 0x1000>;
 748 +                       device_type = "mdio";
 749 +                       little-endian;
 750 +
 751 +                       #address-cells = <1>;
 752 +                       #size-cells = <0>;
 753 +               };
 754 +
 755 +               pcs_mdio3: mdio@0x8c0f000 {
 756 +                       compatible = "fsl,fman-memac-mdio";
 757 +                       reg = <0x0 0x8c0f000 0x0 0x1000>;
 758 +                       device_type = "mdio";
 759 +                       little-endian;
 760 +
 761 +                       #address-cells = <1>;
 762 +                       #size-cells = <0>;
 763 +               };
 764 +
 765 +               pcs_mdio4: mdio@0x8c13000 {
 766 +                       compatible = "fsl,fman-memac-mdio";
 767 +                       reg = <0x0 0x8c13000 0x0 0x1000>;
 768 +                       device_type = "mdio";
 769 +                       little-endian;
 770 +
 771 +                       #address-cells = <1>;
 772 +                       #size-cells = <0>;
 773 +               };
 774 +
 775 +               pcs_mdio5: mdio@0x8c17000 {
 776 +                       status = "disabled";
 777 +                       compatible = "fsl,fman-memac-mdio";
 778 +                       reg = <0x0 0x8c17000 0x0 0x1000>;
 779 +                       device_type = "mdio";
 780 +                       little-endian;
 781 +
 782 +                       #address-cells = <1>;
 783 +                       #size-cells = <0>;
 784 +               };
 785 +
 786 +               pcs_mdio6: mdio@0x8c1b000 {
 787 +                       status = "disabled";
 788 +                       compatible = "fsl,fman-memac-mdio";
 789 +                       reg = <0x0 0x8c1b000 0x0 0x1000>;
 790 +                       device_type = "mdio";
 791 +                       little-endian;
 792 +
 793 +                       #address-cells = <1>;
 794 +                       #size-cells = <0>;
 795 +               };
 796 +
 797 +               pcs_mdio7: mdio@0x8c1f000 {
 798 +                       status = "disabled";
 799 +                       compatible = "fsl,fman-memac-mdio";
 800 +                       reg = <0x0 0x8c1f000 0x0 0x1000>;
 801 +                       device_type = "mdio";
 802 +                       little-endian;
 803 +
 804 +                       #address-cells = <1>;
 805 +                       #size-cells = <0>;
 806 +               };
 807 +
 808 +               pcs_mdio8: mdio@0x8c23000 {
 809 +                       status = "disabled";
 810 +                       compatible = "fsl,fman-memac-mdio";
 811 +                       reg = <0x0 0x8c23000 0x0 0x1000>;
 812 +                       device_type = "mdio";
 813 +                       little-endian;
 814 +
 815 +                       #address-cells = <1>;
 816 +                       #size-cells = <0>;
 817 +               };
 818 +
 819                 i2c0: i2c@2000000 {
 820                         status = "disabled";
 821 -                       compatible = "fsl,vf610-i2c";
 822 +                       compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
 823                         #address-cells = <1>;
 824                         #size-cells = <0>;
 825                         reg = <0x0 0x2000000 0x0 0x10000>;
 826                         interrupts = <0 34 0x4>; /* Level high type */
 827                         clock-names = "i2c";
 828 -                       clocks = <&clockgen 4 3>;
 829 +                       clocks = <&clockgen 4 1>;
 830 +                       scl-gpios = <&gpio3 10 0>;
 831                 };
 832
 833                 i2c1: i2c@2010000 {
 834 @@ -579,7 +689,7 @@
 835                         reg = <0x0 0x2010000 0x0 0x10000>;
 836                         interrupts = <0 34 0x4>; /* Level high type */
 837                         clock-names = "i2c";
 838 -                       clocks = <&clockgen 4 3>;
 839 +                       clocks = <&clockgen 4 1>;
 840                 };
 841
 842                 i2c2: i2c@2020000 {
 843 @@ -590,7 +700,7 @@
 844                         reg = <0x0 0x2020000 0x0 0x10000>;
 845                         interrupts = <0 35 0x4>; /* Level high type */
 846                         clock-names = "i2c";
 847 -                       clocks = <&clockgen 4 3>;
 848 +                       clocks = <&clockgen 4 1>;
 849                 };
 850
 851                 i2c3: i2c@2030000 {
 852 @@ -601,7 +711,7 @@
 853                         reg = <0x0 0x2030000 0x0 0x10000>;
 854                         interrupts = <0 35 0x4>; /* Level high type */
 855                         clock-names = "i2c";
 856 -                       clocks = <&clockgen 4 3>;
 857 +                       clocks = <&clockgen 4 1>;
 858                 };
 859
 860                 ifc: ifc@2240000 {
 861 @@ -633,8 +743,8 @@
 862                 pcie1: pcie@3400000 {
 863                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
 864                         reg-names = "regs", "config";
 865 -                       interrupts = <0 108 0x4>; /* Level high type */
 866 -                       interrupt-names = "intr";
 867 +                       interrupts = <0 108 0x4>; /* aer interrupt */
 868 +                       interrupt-names = "aer";
 869                         #address-cells = <3>;
 870                         #size-cells = <2>;
 871                         device_type = "pci";
 872 @@ -642,6 +752,7 @@
 873                         num-viewport = <6>;
 874                         bus-range = <0x0 0xff>;
 875                         msi-parent = <&its>;
 876 +                       iommu-map = <0 &smmu 0 1>;      /* This is fixed-up by u-boot */
 877                         #interrupt-cells = <1>;
 878                         interrupt-map-mask = <0 0 0 7>;
 879                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
 880 @@ -654,8 +765,8 @@
 881                 pcie2: pcie@3500000 {
 882                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
 883                         reg-names = "regs", "config";
 884 -                       interrupts = <0 113 0x4>; /* Level high type */
 885 -                       interrupt-names = "intr";
 886 +                       interrupts = <0 113 0x4>; /* aer interrupt */
 887 +                       interrupt-names = "aer";
 888                         #address-cells = <3>;
 889                         #size-cells = <2>;
 890                         device_type = "pci";
 891 @@ -663,6 +774,7 @@
 892                         num-viewport = <6>;
 893                         bus-range = <0x0 0xff>;
 894                         msi-parent = <&its>;
 895 +                       iommu-map = <0 &smmu 0 1>;      /* This is fixed-up by u-boot */
 896                         #interrupt-cells = <1>;
 897                         interrupt-map-mask = <0 0 0 7>;
 898                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
 899 @@ -675,8 +787,8 @@
 900                 pcie3: pcie@3600000 {
 901                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
 902                         reg-names = "regs", "config";
 903 -                       interrupts = <0 118 0x4>; /* Level high type */
 904 -                       interrupt-names = "intr";
 905 +                       interrupts = <0 118 0x4>; /* aer interrupt */
 906 +                       interrupt-names = "aer";
 907                         #address-cells = <3>;
 908                         #size-cells = <2>;
 909                         device_type = "pci";
 910 @@ -684,6 +796,7 @@
 911                         num-viewport = <256>;
 912                         bus-range = <0x0 0xff>;
 913                         msi-parent = <&its>;
 914 +                       iommu-map = <0 &smmu 0 1>;      /* This is fixed-up by u-boot */
 915                         #interrupt-cells = <1>;
 916                         interrupt-map-mask = <0 0 0 7>;
 917                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
 918 @@ -696,8 +809,8 @@
 919                 pcie4: pcie@3700000 {
 920                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
 921                         reg-names = "regs", "config";
 922 -                       interrupts = <0 123 0x4>; /* Level high type */
 923 -                       interrupt-names = "intr";
 924 +                       interrupts = <0 123 0x4>; /* aer interrupt */
 925 +                       interrupt-names = "aer";
 926                         #address-cells = <3>;
 927                         #size-cells = <2>;
 928                         device_type = "pci";
 929 @@ -705,6 +818,7 @@
 930                         num-viewport = <6>;
 931                         bus-range = <0x0 0xff>;
 932                         msi-parent = <&its>;
 933 +                       iommu-map = <0 &smmu 0 1>;      /* This is fixed-up by u-boot */
 934                         #interrupt-cells = <1>;
 935                         interrupt-map-mask = <0 0 0 7>;
 936                         interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
 937 @@ -754,11 +868,22 @@
 938                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 939                 };
 940
 941 +               serdes1: serdes@1ea0000 {
 942 +                               reg = <0x0 0x1ea0000 0 0x00002000>;
 943 +                               compatible = "fsl,serdes-10g";
 944 +               };
 945 +
 946                 ccn@4000000 {
 947                         compatible = "arm,ccn-504";
 948                         reg = <0x0 0x04000000 0x0 0x01000000>;
 949                         interrupts = <0 12 4>;
 950                 };
 951 +
 952 +               ftm0: ftm0@2800000 {
 953 +                       compatible = "fsl,ftm-alarm";
 954 +                       reg = <0x0 0x2800000 0x0 0x10000>;
 955 +                       interrupts = <0 44 4>;
 956 +               };
 957         };
 958
 959         ddr1: memory-controller@1080000 {