target/linux/layerscape/patches-4.14/818-qspi-support-layerscape.patch

   1 From fe21ef44284a3aa6fd80448e4ab2e1e8a55fb926 Mon Sep 17 00:00:00 2001
   2 From: Biwen Li <biwen.li@nxp.com>
   3 Date: Wed, 17 Apr 2019 18:58:59 +0800
   4 Subject: [PATCH] qspi: support layerscape
   5
   6 This is an integrated patch of qspi for layerscape
   7
   8 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
   9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
  10 Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
  11 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
  12 Signed-off-by: Mark Brown <broonie@kernel.org>
  13 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
  14 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  15 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
  16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  17 Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  18 ---
  19  drivers/mtd/spi-nor/fsl-quadspi.c | 444 +++++++++++++++++++-----------
  20  drivers/mtd/spi-nor/spi-nor.c     |   5 +
  21  drivers/spi/spi-fsl-dspi.c        |   4 +-
  22  3 files changed, 291 insertions(+), 162 deletions(-)
  23
  24 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
  25 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
  26 @@ -41,6 +41,7 @@
  27  #define QUADSPI_QUIRK_TKT253890                (1 << 2)
  28  /* Controller cannot wake up from wait mode, TKT245618 */
  29  #define QUADSPI_QUIRK_TKT245618         (1 << 3)
  30 +#define QUADSPI_ADDR_REMAP             (1 << 4)
  31
  32  /* The registers */
  33  #define QUADSPI_MCR                    0x00
  34 @@ -183,7 +184,7 @@
  35
  36  /* Macros for constructing the LUT register. */
  37  #define LUT0(ins, pad, opr)                                            \
  38 -               (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
  39 +               (((opr) << OPRND0_SHIFT) | ((pad) << PAD0_SHIFT) | \
  40                 ((LUT_##ins) << INSTR0_SHIFT))
  41
  42  #define LUT1(ins, pad, opr)    (LUT0(ins, pad, opr) << OPRND1_SHIFT)
  43 @@ -193,27 +194,29 @@
  44  #define QUADSPI_LUT_NUM                64
  45
  46  /* SEQID -- we can have 16 seqids at most. */
  47 -#define SEQID_READ             0
  48 -#define SEQID_WREN             1
  49 -#define SEQID_WRDI             2
  50 -#define SEQID_RDSR             3
  51 -#define SEQID_SE               4
  52 -#define SEQID_CHIP_ERASE       5
  53 -#define SEQID_PP               6
  54 -#define SEQID_RDID             7
  55 -#define SEQID_WRSR             8
  56 -#define SEQID_RDCR             9
  57 -#define SEQID_EN4B             10
  58 -#define SEQID_BRWR             11
  59 +/* LUT0 programmed by bootloader, for run-time create entry for LUT seqid 1 */
  60 +#define SEQID_LUT0_BOOTLOADER  0
  61 +#define SEQID_LUT1_RUNTIME     1
  62 +#define SEQID_LUT2_AHBREAD     2
  63
  64  #define QUADSPI_MIN_IOMAP SZ_4M
  65
  66 +enum fsl_qspi_ops {
  67 +       FSL_QSPI_OPS_READ = 0,
  68 +       FSL_QSPI_OPS_WRITE,
  69 +       FSL_QSPI_OPS_ERASE,
  70 +       FSL_QSPI_OPS_READ_REG,
  71 +       FSL_QSPI_OPS_WRITE_REG,
  72 +       FSL_QSPI_OPS_WRITE_BUF_REG,
  73 +};
  74 +
  75  enum fsl_qspi_devtype {
  76         FSL_QUADSPI_VYBRID,
  77         FSL_QUADSPI_IMX6SX,
  78         FSL_QUADSPI_IMX7D,
  79         FSL_QUADSPI_IMX6UL,
  80         FSL_QUADSPI_LS1021A,
  81 +       FSL_QUADSPI_LS2080A,
  82  };
  83
  84  struct fsl_qspi_devtype_data {
  85 @@ -267,6 +270,15 @@ static struct fsl_qspi_devtype_data ls10
  86         .driver_data = 0,
  87  };
  88
  89 +static const struct fsl_qspi_devtype_data ls2080a_data = {
  90 +       .devtype = FSL_QUADSPI_LS2080A,
  91 +       .rxfifo = 128,
  92 +       .txfifo = 64,
  93 +       .ahb_buf_size = 1024,
  94 +       .driver_data = QUADSPI_QUIRK_TKT253890 | QUADSPI_ADDR_REMAP,
  95 +};
  96 +
  97 +
  98  #define FSL_QSPI_MAX_CHIP      4
  99  struct fsl_qspi {
 100         struct spi_nor nor[FSL_QSPI_MAX_CHIP];
 101 @@ -310,6 +322,22 @@ static inline int needs_wakeup_wait_mode
 102  }
 103
 104  /*
 105 + * QSPI memory regions split into two parts: a 256MB region that is located
 106 + * in the least significant 4GB of the SoC address space and a 3.75GB region
 107 + * that is located above the least significant 4GB of the SoC address space.
 108 + *
 109 + * The 4GB QSPI address space map is shown below.
 110 + *
 111 + * SoC Address                    QSPI Address
 112 + * 0x00_2000_0000-0x00_2FFF_FFFF   0x00_0000_0000-0x00_0FFF_FFFF       First 256MB
 113 + * 0x04_1000_0000-0x04_FFFF_FFFF   0x00_1000_0000-0x00_FFFF_FFFF       Last 3.75GB
 114 + */
 115 +static inline int need_address_remap(struct fsl_qspi *q)
 116 +{
 117 +       return q->devtype_data->driver_data & QUADSPI_ADDR_REMAP;
 118 +}
 119 +
 120 +/*
 121   * R/W functions for big- or little-endian registers:
 122   * The qSPI controller's endian is independent of the CPU core's endian.
 123   * So far, although the CPU core is little-endian but the qSPI have two
 124 @@ -368,137 +396,160 @@ static irqreturn_t fsl_qspi_irq_handler(
 125         return IRQ_HANDLED;
 126  }
 127
 128 -static void fsl_qspi_init_lut(struct fsl_qspi *q)
 129 +static inline s8 pad_count(s8 pad_val)
 130  {
 131 +       s8 count = -1;
 132 +
 133 +       if (!pad_val)
 134 +               return 0;
 135 +
 136 +       while (pad_val) {
 137 +               pad_val >>= 1;
 138 +               count++;
 139 +       }
 140 +       return count;
 141 +}
 142 +
 143 +/*
 144 + * Prepare LUT entry for the input cmd.
 145 + * Protocol info is present in instance of struct spi_nor, using which fields
 146 + * like cmd, data, addrlen along with pad info etc can be parsed.
 147 + */
 148 +static void fsl_qspi_prepare_lut(struct spi_nor *nor,
 149 +                                enum fsl_qspi_ops ops, u8 cmd)
 150 +{
 151 +       struct fsl_qspi *q = nor->priv;
 152         void __iomem *base = q->iobase;
 153         int rxfifo = q->devtype_data->rxfifo;
 154 +       int txfifo = q->devtype_data->txfifo;
 155         u32 lut_base;
 156 -       int i;
 157 +       u8 cmd_pad, addr_pad, data_pad, dummy_pad;
 158 +       enum spi_nor_protocol protocol = 0;
 159 +       u8 addrlen = 0;
 160 +       u8 read_dm, opcode;
 161 +       int stop_lut;
 162 +
 163 +       read_dm = opcode = cmd_pad = addr_pad = data_pad = dummy_pad = 0;
 164 +
 165 +       switch (ops) {
 166 +       case FSL_QSPI_OPS_READ_REG:
 167 +       case FSL_QSPI_OPS_WRITE_REG:
 168 +       case FSL_QSPI_OPS_WRITE_BUF_REG:
 169 +               opcode = cmd;
 170 +               protocol = nor->reg_proto;
 171 +               break;
 172 +       case FSL_QSPI_OPS_READ:
 173 +               opcode = cmd;
 174 +               read_dm = nor->read_dummy;
 175 +               protocol = nor->read_proto;
 176 +               break;
 177 +       case FSL_QSPI_OPS_WRITE:
 178 +               opcode = cmd;
 179 +               protocol = nor->write_proto;
 180 +               break;
 181 +       case FSL_QSPI_OPS_ERASE:
 182 +               opcode = cmd;
 183 +               break;
 184 +       default:
 185 +               dev_err(q->dev, "Unsupported operation 0x%.2x\n", ops);
 186 +               return;
 187 +       }
 188 +
 189 +       if (protocol) {
 190 +               cmd_pad = spi_nor_get_protocol_inst_nbits(protocol);
 191 +               addr_pad = spi_nor_get_protocol_addr_nbits(protocol);
 192 +               data_pad = spi_nor_get_protocol_data_nbits(protocol);
 193 +       }
 194 +
 195 +       dummy_pad = data_pad;
 196
 197 -       struct spi_nor *nor = &q->nor[0];
 198 -       u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
 199 -       u8 read_op = nor->read_opcode;
 200 -       u8 read_dm = nor->read_dummy;
 201 +       dev_dbg(q->dev, "ops:%x opcode:%x pad[cmd:%d, addr:%d, data:%d]\n",
 202 +                       ops, opcode, cmd_pad, addr_pad, data_pad);
 203
 204         fsl_qspi_unlock_lut(q);
 205
 206 -       /* Clear all the LUT table */
 207 -       for (i = 0; i < QUADSPI_LUT_NUM; i++)
 208 -               qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 209 -
 210 -       /* Read */
 211 -       lut_base = SEQID_READ * 4;
 212 -
 213 -       qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
 214 -                       base + QUADSPI_LUT(lut_base));
 215 -       qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
 216 -                   LUT1(FSL_READ, PAD4, rxfifo),
 217 -                       base + QUADSPI_LUT(lut_base + 1));
 218 -
 219 -       /* Write enable */
 220 -       lut_base = SEQID_WREN * 4;
 221 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
 222 -                       base + QUADSPI_LUT(lut_base));
 223 -
 224 -       /* Page Program */
 225 -       lut_base = SEQID_PP * 4;
 226 -
 227 -       qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
 228 -                   LUT1(ADDR, PAD1, addrlen),
 229 -                       base + QUADSPI_LUT(lut_base));
 230 -       qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
 231 -                       base + QUADSPI_LUT(lut_base + 1));
 232 -
 233 -       /* Read Status */
 234 -       lut_base = SEQID_RDSR * 4;
 235 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
 236 -                       LUT1(FSL_READ, PAD1, 0x1),
 237 -                       base + QUADSPI_LUT(lut_base));
 238 -
 239 -       /* Erase a sector */
 240 -       lut_base = SEQID_SE * 4;
 241 -
 242 -       qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
 243 -                   LUT1(ADDR, PAD1, addrlen),
 244 -                       base + QUADSPI_LUT(lut_base));
 245 -
 246 -       /* Erase the whole chip */
 247 -       lut_base = SEQID_CHIP_ERASE * 4;
 248 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
 249 -                       base + QUADSPI_LUT(lut_base));
 250 -
 251 -       /* READ ID */
 252 -       lut_base = SEQID_RDID * 4;
 253 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
 254 -                       LUT1(FSL_READ, PAD1, 0x8),
 255 -                       base + QUADSPI_LUT(lut_base));
 256 -
 257 -       /* Write Register */
 258 -       lut_base = SEQID_WRSR * 4;
 259 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
 260 -                       LUT1(FSL_WRITE, PAD1, 0x2),
 261 -                       base + QUADSPI_LUT(lut_base));
 262 -
 263 -       /* Read Configuration Register */
 264 -       lut_base = SEQID_RDCR * 4;
 265 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
 266 -                       LUT1(FSL_READ, PAD1, 0x1),
 267 -                       base + QUADSPI_LUT(lut_base));
 268 -
 269 -       /* Write disable */
 270 -       lut_base = SEQID_WRDI * 4;
 271 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
 272 -                       base + QUADSPI_LUT(lut_base));
 273 -
 274 -       /* Enter 4 Byte Mode (Micron) */
 275 -       lut_base = SEQID_EN4B * 4;
 276 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
 277 -                       base + QUADSPI_LUT(lut_base));
 278 -
 279 -       /* Enter 4 Byte Mode (Spansion) */
 280 -       lut_base = SEQID_BRWR * 4;
 281 -       qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
 282 -                       base + QUADSPI_LUT(lut_base));
 283 +       /* Dynamic LUT */
 284 +       lut_base = SEQID_LUT1_RUNTIME * 4;
 285 +       if (ops == FSL_QSPI_OPS_READ)
 286 +               lut_base = SEQID_LUT2_AHBREAD * 4;
 287 +
 288 +       /* default, STOP instruction to be programmed in (lut_base + 1) reg */
 289 +       stop_lut = 1;
 290 +       switch (ops) {
 291 +       case FSL_QSPI_OPS_READ_REG:
 292 +               qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
 293 +                         LUT1(FSL_READ, pad_count(data_pad), rxfifo),
 294 +                         base + QUADSPI_LUT(lut_base));
 295 +               break;
 296 +       case FSL_QSPI_OPS_WRITE_REG:
 297 +               qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode),
 298 +                         base + QUADSPI_LUT(lut_base));
 299 +               break;
 300 +       case FSL_QSPI_OPS_WRITE_BUF_REG:
 301 +               qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
 302 +                         LUT1(FSL_WRITE, pad_count(data_pad), txfifo),
 303 +                         base + QUADSPI_LUT(lut_base));
 304 +               break;
 305 +       case FSL_QSPI_OPS_READ:
 306 +       case FSL_QSPI_OPS_WRITE:
 307 +       case FSL_QSPI_OPS_ERASE:
 308 +               /* Common for Read, Write and Erase ops. */
 309 +
 310 +               addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
 311 +
 312 +               qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
 313 +                               LUT1(ADDR, pad_count(addr_pad), addrlen),
 314 +                               base + QUADSPI_LUT(lut_base));
 315 +               /*
 316 +                * For Erase ops - Data and Dummy not required.
 317 +                * For Write ops - Dummy not required.
 318 +                */
 319
 320 -       fsl_qspi_lock_lut(q);
 321 -}
 322 +               if (ops == FSL_QSPI_OPS_READ) {
 323
 324 -/* Get the SEQID for the command */
 325 -static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 326 -{
 327 -       switch (cmd) {
 328 -       case SPINOR_OP_READ_1_1_4:
 329 -       case SPINOR_OP_READ_1_1_4_4B:
 330 -               return SEQID_READ;
 331 -       case SPINOR_OP_WREN:
 332 -               return SEQID_WREN;
 333 -       case SPINOR_OP_WRDI:
 334 -               return SEQID_WRDI;
 335 -       case SPINOR_OP_RDSR:
 336 -               return SEQID_RDSR;
 337 -       case SPINOR_OP_SE:
 338 -               return SEQID_SE;
 339 -       case SPINOR_OP_CHIP_ERASE:
 340 -               return SEQID_CHIP_ERASE;
 341 -       case SPINOR_OP_PP:
 342 -               return SEQID_PP;
 343 -       case SPINOR_OP_RDID:
 344 -               return SEQID_RDID;
 345 -       case SPINOR_OP_WRSR:
 346 -               return SEQID_WRSR;
 347 -       case SPINOR_OP_RDCR:
 348 -               return SEQID_RDCR;
 349 -       case SPINOR_OP_EN4B:
 350 -               return SEQID_EN4B;
 351 -       case SPINOR_OP_BRWR:
 352 -               return SEQID_BRWR;
 353 +                       /*
 354 +                        * For cmds SPINOR_OP_READ and SPINOR_OP_READ_4B value
 355 +                        * of dummy cycles are 0.
 356 +                        */
 357 +                       if (read_dm)
 358 +                               qspi_writel(q,
 359 +                                           LUT0(DUMMY, pad_count(dummy_pad),
 360 +                                           read_dm) |
 361 +                                           LUT1(FSL_READ, pad_count(data_pad),
 362 +                                           rxfifo),
 363 +                                           base + QUADSPI_LUT(lut_base + 1));
 364 +                       else
 365 +                               qspi_writel(q,
 366 +                                           LUT0(FSL_READ, pad_count(data_pad),
 367 +                                           rxfifo),
 368 +                                           base + QUADSPI_LUT(lut_base + 1));
 369 +
 370 +                       stop_lut = 2;
 371 +
 372 +                       /* TODO Add condition to check if READ is IP/AHB. */
 373 +
 374 +                       /* For AHB read, add seqid in BFGENCR register. */
 375 +                       qspi_writel(q,
 376 +                                   SEQID_LUT2_AHBREAD <<
 377 +                                   QUADSPI_BFGENCR_SEQID_SHIFT,
 378 +                                   q->iobase + QUADSPI_BFGENCR);
 379 +               }
 380 +
 381 +               if (ops == FSL_QSPI_OPS_WRITE) {
 382 +                       qspi_writel(q, LUT0(FSL_WRITE, pad_count(data_pad), 0),
 383 +                                       base + QUADSPI_LUT(lut_base + 1));
 384 +                       stop_lut = 2;
 385 +               }
 386 +               break;
 387         default:
 388 -               if (cmd == q->nor[0].erase_opcode)
 389 -                       return SEQID_SE;
 390 -               dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
 391 +               dev_err(q->dev, "Unsupported operation 0x%.2x\n", ops);
 392                 break;
 393         }
 394 -       return -EINVAL;
 395 +
 396 +       /* prepare LUT for STOP instruction. */
 397 +       qspi_writel(q, 0, base +  QUADSPI_LUT(lut_base + stop_lut));
 398 +
 399 +       fsl_qspi_lock_lut(q);
 400  }
 401
 402  static int
 403 @@ -508,6 +559,10 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
 404         int seqid;
 405         u32 reg, reg2;
 406         int err;
 407 +       u32 memmap_phyadd = q->memmap_phy;
 408 +
 409 +       if (need_address_remap(q))
 410 +               memmap_phyadd = 0;
 411
 412         init_completion(&q->c);
 413         dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
 414 @@ -516,7 +571,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
 415         /* save the reg */
 416         reg = qspi_readl(q, base + QUADSPI_MCR);
 417
 418 -       qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
 419 +       qspi_writel(q, memmap_phyadd + q->chip_base_addr + addr,
 420                         base + QUADSPI_SFAR);
 421         qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
 422                         base + QUADSPI_RBCT);
 423 @@ -533,7 +588,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
 424         } while (1);
 425
 426         /* trigger the LUT now */
 427 -       seqid = fsl_qspi_get_seqid(q, cmd);
 428 +       seqid = SEQID_LUT1_RUNTIME;
 429         qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
 430                         base + QUADSPI_IPCR);
 431
 432 @@ -609,6 +664,7 @@ static ssize_t fsl_qspi_nor_write(struct
 433  {
 434         int ret, i, j;
 435         u32 tmp;
 436 +       u8 byts;
 437
 438         dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
 439                 q->chip_base_addr, to, count);
 440 @@ -618,10 +674,18 @@ static ssize_t fsl_qspi_nor_write(struct
 441         qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
 442
 443         /* fill the TX data to the FIFO */
 444 +       byts = count;
 445         for (j = 0, i = ((count + 3) / 4); j < i; j++) {
 446 -               tmp = fsl_qspi_endian_xchg(q, *txbuf);
 447 +               if(byts >= 4)
 448 +                       tmp = fsl_qspi_endian_xchg(q, *txbuf);
 449 +               else {
 450 +                       memcpy(&tmp, txbuf, byts);
 451 +                       tmp = fsl_qspi_endian_xchg(q, tmp);
 452 +               }
 453 +
 454                 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
 455                 txbuf++;
 456 +               byts -= 4;
 457         }
 458
 459         /* fill the TXFIFO upto 16 bytes for i.MX7d */
 460 @@ -642,11 +706,15 @@ static void fsl_qspi_set_map_addr(struct
 461  {
 462         int nor_size = q->nor_size;
 463         void __iomem *base = q->iobase;
 464 +       u32 memmap_phyadd = q->memmap_phy;
 465 +
 466 +       if (need_address_remap(q))
 467 +               memmap_phyadd = 0;
 468
 469 -       qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
 470 -       qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
 471 -       qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
 472 -       qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
 473 +       qspi_writel(q, nor_size + memmap_phyadd, base + QUADSPI_SFA1AD);
 474 +       qspi_writel(q, nor_size * 2 + memmap_phyadd, base + QUADSPI_SFA2AD);
 475 +       qspi_writel(q, nor_size * 3 + memmap_phyadd, base + QUADSPI_SFB1AD);
 476 +       qspi_writel(q, nor_size * 4 + memmap_phyadd, base + QUADSPI_SFB2AD);
 477  }
 478
 479  /*
 480 @@ -662,7 +730,7 @@ static void fsl_qspi_set_map_addr(struct
 481   * causes the controller to clear the buffer, and use the sequence pointed
 482   * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 483   */
 484 -static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
 485 +static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
 486  {
 487         void __iomem *base = q->iobase;
 488         int seqid;
 489 @@ -685,8 +753,8 @@ static void fsl_qspi_init_abh_read(struc
 490         qspi_writel(q, 0, base + QUADSPI_BUF1IND);
 491         qspi_writel(q, 0, base + QUADSPI_BUF2IND);
 492
 493 -       /* Set the default lut sequence for AHB Read. */
 494 -       seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
 495 +       /* Set dynamic LUT entry as lut sequence for AHB Read . */
 496 +       seqid = SEQID_LUT2_AHBREAD;
 497         qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
 498                 q->iobase + QUADSPI_BFGENCR);
 499  }
 500 @@ -729,7 +797,6 @@ static int fsl_qspi_nor_setup(struct fsl
 501         void __iomem *base = q->iobase;
 502         u32 reg;
 503         int ret;
 504 -
 505         /* disable and unprepare clock to avoid glitch pass to controller */
 506         fsl_qspi_clk_disable_unprep(q);
 507
 508 @@ -747,9 +814,6 @@ static int fsl_qspi_nor_setup(struct fsl
 509                 base + QUADSPI_MCR);
 510         udelay(1);
 511
 512 -       /* Init the LUT table. */
 513 -       fsl_qspi_init_lut(q);
 514 -
 515         /* Disable the module */
 516         qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
 517                         base + QUADSPI_MCR);
 518 @@ -770,6 +834,9 @@ static int fsl_qspi_nor_setup(struct fsl
 519         /* enable the interrupt */
 520         qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
 521
 522 +       /* Init for AHB read */
 523 +       fsl_qspi_init_ahb_read(q);
 524 +
 525         return 0;
 526  }
 527
 528 @@ -792,12 +859,6 @@ static int fsl_qspi_nor_setup_last(struc
 529         if (ret)
 530                 return ret;
 531
 532 -       /* Init the LUT table again. */
 533 -       fsl_qspi_init_lut(q);
 534 -
 535 -       /* Init for AHB read */
 536 -       fsl_qspi_init_abh_read(q);
 537 -
 538         return 0;
 539  }
 540
 541 @@ -807,6 +868,7 @@ static const struct of_device_id fsl_qsp
 542         { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
 543         { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
 544         { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
 545 +       { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
 546         { /* sentinel */ }
 547  };
 548  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
 549 @@ -821,6 +883,7 @@ static int fsl_qspi_read_reg(struct spi_
 550         int ret;
 551         struct fsl_qspi *q = nor->priv;
 552
 553 +       fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ_REG, opcode);
 554         ret = fsl_qspi_runcmd(q, opcode, 0, len);
 555         if (ret)
 556                 return ret;
 557 @@ -835,6 +898,8 @@ static int fsl_qspi_write_reg(struct spi
 558         int ret;
 559
 560         if (!buf) {
 561 +               /* Prepare LUT for WRITE_REG cmd with input BUF as NULL. */
 562 +               fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE_REG, opcode);
 563                 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
 564                 if (ret)
 565                         return ret;
 566 @@ -843,6 +908,8 @@ static int fsl_qspi_write_reg(struct spi
 567                         fsl_qspi_invalid(q);
 568
 569         } else if (len > 0) {
 570 +               /* Prepare LUT for WRITE_REG cmd with input BUF non-NULL. */
 571 +               fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE_BUF_REG, opcode);
 572                 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
 573                                         (u32 *)buf, len);
 574                 if (ret > 0)
 575 @@ -859,8 +926,11 @@ static ssize_t fsl_qspi_write(struct spi
 576                               size_t len, const u_char *buf)
 577  {
 578         struct fsl_qspi *q = nor->priv;
 579 -       ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
 580 -                                        (u32 *)buf, len);
 581 +       ssize_t ret;
 582 +
 583 +       fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE, nor->program_opcode);
 584 +       ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
 585 +                                (u32 *)buf, len);
 586
 587         /* invalid the data in the AHB buffer. */
 588         fsl_qspi_invalid(q);
 589 @@ -873,6 +943,8 @@ static ssize_t fsl_qspi_read(struct spi_
 590         struct fsl_qspi *q = nor->priv;
 591         u8 cmd = nor->read_opcode;
 592
 593 +       fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ, nor->read_opcode);
 594 +
 595         /* if necessary,ioremap buffer before AHB read, */
 596         if (!q->ahb_addr) {
 597                 q->memmap_offs = q->chip_base_addr + from;
 598 @@ -907,8 +979,9 @@ static ssize_t fsl_qspi_read(struct spi_
 599                 len);
 600
 601         /* Read out the data directly from the AHB buffer.*/
 602 -       memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
 603 -               len);
 604 +       memcpy_fromio(buf,
 605 +                     q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
 606 +                     len);
 607
 608         return len;
 609  }
 610 @@ -921,6 +994,7 @@ static int fsl_qspi_erase(struct spi_nor
 611         dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
 612                 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
 613
 614 +       fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_ERASE, nor->erase_opcode);
 615         ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
 616         if (ret)
 617                 return ret;
 618 @@ -958,17 +1032,14 @@ static void fsl_qspi_unprep(struct spi_n
 619
 620  static int fsl_qspi_probe(struct platform_device *pdev)
 621  {
 622 -       const struct spi_nor_hwcaps hwcaps = {
 623 -               .mask = SNOR_HWCAPS_READ_1_1_4 |
 624 -                       SNOR_HWCAPS_PP,
 625 -       };
 626 +       struct spi_nor_hwcaps hwcaps;
 627         struct device_node *np = pdev->dev.of_node;
 628         struct device *dev = &pdev->dev;
 629         struct fsl_qspi *q;
 630         struct resource *res;
 631         struct spi_nor *nor;
 632         struct mtd_info *mtd;
 633 -       int ret, i = 0;
 634 +       int ret, i = 0, value;
 635
 636         q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
 637         if (!q)
 638 @@ -1041,6 +1112,10 @@ static int fsl_qspi_probe(struct platfor
 639
 640         /* iterate the subnodes. */
 641         for_each_available_child_of_node(dev->of_node, np) {
 642 +               /* Reset hwcaps mask to minimal caps for the slave node. */
 643 +               hwcaps.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP;
 644 +               value = 0;
 645 +
 646                 /* skip the holes */
 647                 if (!q->has_second_chip)
 648                         i *= 2;
 649 @@ -1070,6 +1145,51 @@ static int fsl_qspi_probe(struct platfor
 650                 /* set the chip address for READID */
 651                 fsl_qspi_set_base_addr(q, nor);
 652
 653 +               /*
 654 +                * If spi-rx-bus-width and spi-tx-bus-width not defined assign
 655 +                * default hardware capabilities SNOR_HWCAPS_READ_1_1_4 and
 656 +                * SNOR_HWCAPS_PP supported by the Quad-SPI controller.
 657 +                */
 658 +               if (!of_property_read_u32(np, "spi-rx-bus-width", &value)) {
 659 +                       switch (value) {
 660 +                       case 1:
 661 +                               hwcaps.mask |= SNOR_HWCAPS_READ |
 662 +                                              SNOR_HWCAPS_READ_FAST;
 663 +                               break;
 664 +                       case 2:
 665 +                               hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2 |
 666 +                                              SNOR_HWCAPS_READ_1_2_2;
 667 +                               break;
 668 +                       case 4:
 669 +                               hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4 |
 670 +                                              SNOR_HWCAPS_READ_1_4_4;
 671 +                               break;
 672 +                       default:
 673 +                               dev_err(dev,
 674 +                                       "spi-rx-bus-width %d not supported\n",
 675 +                                       value);
 676 +                               break;
 677 +                       }
 678 +               } else
 679 +                       hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 680 +
 681 +               if (!of_property_read_u32(np, "spi-tx-bus-width", &value)) {
 682 +                       switch (value) {
 683 +                       case 1:
 684 +                               hwcaps.mask |= SNOR_HWCAPS_PP;
 685 +                               break;
 686 +                       case 4:
 687 +                               hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4 |
 688 +                                              SNOR_HWCAPS_PP_1_4_4;
 689 +                               break;
 690 +                       default:
 691 +                               dev_err(dev,
 692 +                                       "spi-tx-bus-width %d not supported\n",
 693 +                                       value);
 694 +                               break;
 695 +                       }
 696 +               }
 697 +
 698                 ret = spi_nor_scan(nor, NULL, &hwcaps);
 699                 if (ret)
 700                         goto mutex_failed;
 701 @@ -1098,6 +1218,8 @@ static int fsl_qspi_probe(struct platfor
 702                 if (nor->page_size > q->devtype_data->txfifo)
 703                         nor->page_size = q->devtype_data->txfifo;
 704
 705 +               /*required for memory mapped AHB read*/
 706 +               fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ, nor->read_opcode);
 707                 i++;
 708         }
 709
 710 @@ -1106,6 +1228,8 @@ static int fsl_qspi_probe(struct platfor
 711         if (ret)
 712                 goto last_init_failed;
 713
 714 +
 715 +
 716         fsl_qspi_clk_disable_unprep(q);
 717         return 0;
 718
 719 --- a/drivers/mtd/spi-nor/spi-nor.c
 720 +++ b/drivers/mtd/spi-nor/spi-nor.c
 721 @@ -1154,6 +1154,11 @@ static const struct flash_info spi_nor_i
 722         { "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
 723         { "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
 724         { "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
 725 +       {
 726 +               "w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
 727 +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 728 +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 729 +       },
 730         { "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
 731         { "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
 732         { "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
 733 --- a/drivers/spi/spi-fsl-dspi.c
 734 +++ b/drivers/spi/spi-fsl-dspi.c
 735 @@ -1024,8 +1024,8 @@ static int dspi_probe(struct platform_de
 736                 goto out_clk_put;
 737         }
 738
 739 -       ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
 740 -                       pdev->name, dspi);
 741 +       ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
 742 +                                  IRQF_SHARED, pdev->name, dspi);
 743         if (ret < 0) {
 744                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
 745                 goto out_clk_put;