target/linux/layerscape/patches-4.14/806-rtc-support-layerscape.patch

   1 From f8d89482075e2a4a62fc5cbacf6bea6baf4dc65f Mon Sep 17 00:00:00 2001
   2 From: Biwen Li <biwen.li@nxp.com>
   3 Date: Tue, 30 Oct 2018 18:27:31 +0800
   4 Subject: [PATCH 23/40] rtc: support layerscape
   5 This is an integrated patch of rtc for layerscape
   6
   7 Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
   8 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
   9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
  10 ---
  11  .../devicetree/bindings/rtc/nxp,pcf85263.txt  |  42 ++
  12  drivers/rtc/Kconfig                           |   8 +
  13  drivers/rtc/Makefile                          |   1 +
  14  drivers/rtc/rtc-pcf85263.c                    | 664 ++++++++++++++++++
  15  include/dt-bindings/rtc/nxp,pcf85263.h        |  14 +
  16  5 files changed, 729 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85263.txt
  18  create mode 100644 drivers/rtc/rtc-pcf85263.c
  19  create mode 100644 include/dt-bindings/rtc/nxp,pcf85263.h
  20
  21 --- /dev/null
  22 +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85263.txt
  23 @@ -0,0 +1,42 @@
  24 +NXP PCF85263 I2C Real Time Clock
  25 +
  26 +Required properties:
  27 +- compatible: must be: "nxp,rtc-pcf85263"
  28 +- reg: must be the I2C address
  29 +
  30 +Optional properties:
  31 +- interrupt-names: Which interrupt signal is used must be "INTA" or "INTB"
  32 +    Defaults to "INTA"
  33 +
  34 +- quartz-load-capacitance: The internal capacitor to select for the quartz:
  35 +       PCF85263_QUARTZCAP_7pF          [0]
  36 +       PCF85263_QUARTZCAP_6pF          [1]
  37 +       PCF85263_QUARTZCAP_12p5pF       [2] DEFAULT
  38 +
  39 +- quartz-drive-strength: Drive strength for the quartz:
  40 +       PCF85263_QUARTZDRIVE_NORMAL     [0] DEFAULT
  41 +       PCF85263_QUARTZDRIVE_LOW        [1]
  42 +       PCF85263_QUARTZDRIVE_HIGH       [2]
  43 +
  44 +- quartz-low-jitter: Boolean property, if present enables low jitter mode
  45 +which
  46 +    reduces jitter at the cost of increased power consumption.
  47 +
  48 +- wakeup-source: mark the chip as a wakeup source, independently of
  49 +    the availability of an IRQ line connected to the SoC.
  50 +    This is useful if the IRQ line is connected to a PMIC or other circuit
  51 +    that can power up the device rather than to a normal SOC interrupt.
  52 +
  53 +Example:
  54 +
  55 +rtc@51 {
  56 +       compatible = "nxp,pcf85263";
  57 +       reg = <0x51>;
  58 +
  59 +       interrupt-parent = <&gpio4>;
  60 +       interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
  61 +       interrupt-names = "INTB";
  62 +
  63 +       quartz-load-capacitance = <PCF85263_QUARTZCAP_12p5pF>;
  64 +       quartz-drive-strength = <PCF85263_QUARTZDRIVE_LOW>;
  65 +};
  66 --- a/drivers/rtc/Kconfig
  67 +++ b/drivers/rtc/Kconfig
  68 @@ -433,6 +433,14 @@ config RTC_DRV_PCF85063
  69           This driver can also be built as a module. If so, the module
  70           will be called rtc-pcf85063.
  71
  72 +config RTC_DRV_PCF85263
  73 +       tristate "NXP PCF85263"
  74 +       help
  75 +         If you say yes here you get support for the PCF85263 RTC chip
  76 +
  77 +         This driver can also be built as a module. If so, the module
  78 +         will be called rtc-pcf85263.
  79 +
  80  config RTC_DRV_PCF8563
  81         tristate "Philips PCF8563/Epson RTC8564"
  82         help
  83 --- a/drivers/rtc/Makefile
  84 +++ b/drivers/rtc/Makefile
  85 @@ -115,6 +115,7 @@ obj-$(CONFIG_RTC_DRV_PCF2127)       += rtc-pcf
  86  obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
  87  obj-$(CONFIG_RTC_DRV_PCF85063) += rtc-pcf85063.o
  88  obj-$(CONFIG_RTC_DRV_PCF8523)  += rtc-pcf8523.o
  89 +obj-$(CONFIG_RTC_DRV_PCF85263) += rtc-pcf85263.o
  90  obj-$(CONFIG_RTC_DRV_PCF8563)  += rtc-pcf8563.o
  91  obj-$(CONFIG_RTC_DRV_PCF8583)  += rtc-pcf8583.o
  92  obj-$(CONFIG_RTC_DRV_PIC32)    += rtc-pic32.o
  93 --- /dev/null
  94 +++ b/drivers/rtc/rtc-pcf85263.c
  95 @@ -0,0 +1,664 @@
  96 +/*
  97 + * rtc-pcf85263 Driver for the NXP PCF85263 RTC
  98 + * Copyright 2016 Parkeon
  99 + *
 100 + * This program is free software; you can redistribute it and/or modify
 101 + * it under the terms of the GNU General Public License version 2 as
 102 + * published by the Free Software Foundation.
 103 + */
 104 +
 105 +#include <linux/module.h>
 106 +#include <linux/mutex.h>
 107 +#include <linux/rtc.h>
 108 +#include <linux/i2c.h>
 109 +#include <linux/bcd.h>
 110 +#include <linux/of.h>
 111 +#include <linux/of_device.h>
 112 +#include <linux/regmap.h>
 113 +
 114 +
 115 +#define DRV_NAME "rtc-pcf85263"
 116 +
 117 +/* Quartz capacitance */
 118 +#define PCF85263_QUARTZCAP_7pF         0
 119 +#define PCF85263_QUARTZCAP_6pF         1
 120 +#define PCF85263_QUARTZCAP_12p5pF      2
 121 +
 122 +/* Quartz drive strength */
 123 +#define PCF85263_QUARTZDRIVE_NORMAL    0
 124 +#define PCF85263_QUARTZDRIVE_LOW       1
 125 +#define PCF85263_QUARTZDRIVE_HIGH      2
 126 +
 127 +
 128 +#define PCF85263_REG_RTC_SC    0x01    /* Seconds */
 129 +#define PCF85263_REG_RTC_SC_OS         BIT(7)  /* Oscilator stopped flag */
 130 +
 131 +#define PCF85263_REG_RTC_MN    0x02    /* Minutes */
 132 +#define PCF85263_REG_RTC_HR    0x03    /* Hours */
 133 +#define PCF85263_REG_RTC_DT    0x04    /* Day of month 1-31 */
 134 +#define PCF85263_REG_RTC_DW    0x05    /* Day of week 0-6 */
 135 +#define PCF85263_REG_RTC_MO    0x06    /* Month 1-12 */
 136 +#define PCF85263_REG_RTC_YR    0x07    /* Year 0-99 */
 137 +
 138 +#define PCF85263_REG_ALM1_SC   0x08    /* Seconds */
 139 +#define PCF85263_REG_ALM1_MN   0x09    /* Minutes */
 140 +#define PCF85263_REG_ALM1_HR   0x0a    /* Hours */
 141 +#define PCF85263_REG_ALM1_DT   0x0b    /* Day of month 1-31 */
 142 +#define PCF85263_REG_ALM1_MO   0x0c    /* Month 1-12 */
 143 +
 144 +#define PCF85263_REG_ALM_CTL   0x10
 145 +#define PCF85263_REG_ALM_CTL_ALL_A1E   0x1f /* sec,min,hr,day,mon alarm 1 */
 146 +
 147 +#define PCF85263_REG_OSC       0x25
 148 +#define PCF85263_REG_OSC_CL_MASK       (BIT(0) | BIT(1))
 149 +#define PCF85263_REG_OSC_CL_SHIFT      0
 150 +#define PCF85263_REG_OSC_OSCD_MASK     (BIT(2) | BIT(3))
 151 +#define PCF85263_REG_OSC_OSCD_SHIFT    2
 152 +#define PCF85263_REG_OSC_LOWJ          BIT(4)
 153 +#define PCF85263_REG_OSC_12H           BIT(5)
 154 +
 155 +#define PCF85263_REG_PINIO     0x27
 156 +#define PCF85263_REG_PINIO_INTAPM_MASK (BIT(0) | BIT(1))
 157 +#define PCF85263_REG_PINIO_INTAPM_SHIFT        0
 158 +#define PCF85263_INTAPM_INTA   (0x2 << PCF85263_REG_PINIO_INTAPM_SHIFT)
 159 +#define PCF85263_INTAPM_HIGHZ  (0x3 << PCF85263_REG_PINIO_INTAPM_SHIFT)
 160 +#define PCF85263_REG_PINIO_TSPM_MASK   (BIT(2) | BIT(3))
 161 +#define PCF85263_REG_PINIO_TSPM_SHIFT  2
 162 +#define PCF85263_TSPM_DISABLED         (0x0 << PCF85263_REG_PINIO_TSPM_SHIFT)
 163 +#define PCF85263_TSPM_INTB             (0x1 << PCF85263_REG_PINIO_TSPM_SHIFT)
 164 +#define PCF85263_REG_PINIO_CLKDISABLE  BIT(7)
 165 +
 166 +#define PCF85263_REG_FUNCTION  0x28
 167 +#define PCF85263_REG_FUNCTION_COF_MASK 0x7
 168 +#define PCF85263_REG_FUNCTION_COF_OFF  0x7     /* No clock output */
 169 +
 170 +#define PCF85263_REG_INTA_CTL  0x29
 171 +#define PCF85263_REG_INTB_CTL  0x2A
 172 +#define PCF85263_REG_INTx_CTL_A1E      BIT(4)  /* Alarm 1 */
 173 +#define PCF85263_REG_INTx_CTL_ILP      BIT(7)  /* 0=pulse, 1=level */
 174 +
 175 +#define PCF85263_REG_FLAGS     0x2B
 176 +#define PCF85263_REG_FLAGS_A1F         BIT(5)
 177 +
 178 +#define PCF85263_REG_RAM_BYTE  0x2c
 179 +
 180 +#define PCF85263_REG_STOPENABLE 0x2e
 181 +#define PCF85263_REG_STOPENABLE_STOP   BIT(0)
 182 +
 183 +#define PCF85263_REG_RESET     0x2f    /* Reset command */
 184 +#define PCF85263_REG_RESET_CMD_CPR     0xa4    /* Clear prescaler */
 185 +
 186 +#define PCF85263_MAX_REG 0x2f
 187 +
 188 +#define PCF85263_HR_PM         BIT(5)
 189 +
 190 +enum pcf85263_irqpin {
 191 +       PCF85263_IRQPIN_NONE,
 192 +       PCF85263_IRQPIN_INTA,
 193 +       PCF85263_IRQPIN_INTB
 194 +};
 195 +
 196 +static const char *const pcf85263_irqpin_names[] = {
 197 +       [PCF85263_IRQPIN_NONE] = "None",
 198 +       [PCF85263_IRQPIN_INTA] = "INTA",
 199 +       [PCF85263_IRQPIN_INTB] = "INTB"
 200 +};
 201 +
 202 +struct pcf85263 {
 203 +       struct device *dev;
 204 +       struct rtc_device *rtc;
 205 +       struct regmap *regmap;
 206 +       enum pcf85263_irqpin irq_pin;
 207 +       int irq;
 208 +       bool mode_12h;
 209 +};
 210 +
 211 +/*
 212 + * Helpers to convert 12h to 24h and vice versa.
 213 + * Values in register are stored in BCD with a PM flag in bit 5
 214 + *
 215 + * 23:00 <=> 11PM <=> 0x31
 216 + * 00:00 <=> 12AM <=> 0x12
 217 + * 01:00 <=> 1AM <=> 0x01
 218 + * 12:00 <=> 12PM <=> 0x32
 219 + * 13:00 <=> 1PM <=> 0x21
 220 + */
 221 +static int pcf85263_bcd12h_to_bin24h(int regval)
 222 +{
 223 +       int hr = bcd2bin(regval & 0x1f);
 224 +       bool pm = regval & PCF85263_HR_PM;
 225 +
 226 +       if (hr == 12)
 227 +               return pm ? 12 : 0;
 228 +
 229 +       return pm ? hr + 12 : hr;
 230 +}
 231 +
 232 +static int pcf85263_bin24h_to_bcd12h(int hr24)
 233 +{
 234 +       bool pm = hr24 >= 12;
 235 +       int hr12 = hr24 % 12;
 236 +
 237 +       if (!hr12)
 238 +               hr12++;
 239 +
 240 +       return bin2bcd(hr12) | pm ? 0 : PCF85263_HR_PM;
 241 +}
 242 +
 243 +static int pcf85263_read_time(struct device *dev, struct rtc_time *tm)
 244 +{
 245 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 246 +       const int first = PCF85263_REG_RTC_SC;
 247 +       const int last = PCF85263_REG_RTC_YR;
 248 +       const int len = last - first + 1;
 249 +       u8 regs[len];
 250 +       u8 hr_reg;
 251 +       int ret;
 252 +
 253 +       ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
 254 +       if (ret)
 255 +               return ret;
 256 +
 257 +       if (regs[PCF85263_REG_RTC_SC - first] & PCF85263_REG_RTC_SC_OS) {
 258 +               dev_warn(dev, "Oscillator stop detected, date/time is not reliable.\n");
 259 +               return -EINVAL;
 260 +       }
 261 +
 262 +       tm->tm_sec = bcd2bin(regs[PCF85263_REG_RTC_SC - first] & 0x7f);
 263 +       tm->tm_min = bcd2bin(regs[PCF85263_REG_RTC_MN - first] & 0x7f);
 264 +
 265 +       hr_reg = regs[PCF85263_REG_RTC_HR - first];
 266 +       if (pcf85263->mode_12h)
 267 +               tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
 268 +       else
 269 +               tm->tm_hour = bcd2bin(hr_reg & 0x3f);
 270 +
 271 +       tm->tm_mday = bcd2bin(regs[PCF85263_REG_RTC_DT - first]);
 272 +       tm->tm_wday = bcd2bin(regs[PCF85263_REG_RTC_DW - first]);
 273 +       tm->tm_mon  = bcd2bin(regs[PCF85263_REG_RTC_MO - first]) - 1;
 274 +       tm->tm_year = bcd2bin(regs[PCF85263_REG_RTC_YR - first]);
 275 +
 276 +       tm->tm_year += 100;  /* Assume 21st century */
 277 +
 278 +       return 0;
 279 +}
 280 +
 281 +static int pcf85263_set_time(struct device *dev, struct rtc_time *tm)
 282 +{
 283 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 284 +
 285 +       /*
 286 +        * Before setting time need to stop RTC and disable prescaler
 287 +        * Do this all in a single I2C transaction exploiting wraparound
 288 +        * as described in data sheet.
 289 +        * This means that the array below must be in register order
 290 +        */
 291 +       u8 regs[] = {
 292 +               PCF85263_REG_STOPENABLE_STOP,   /* STOP */
 293 +               PCF85263_REG_RESET_CMD_CPR,     /* Disable prescaler */
 294 +               /* Wrap around to register 0 (1/100s) */
 295 +               0,                              /* 1/100s always zero. */
 296 +               bin2bcd(tm->tm_sec),
 297 +               bin2bcd(tm->tm_min),
 298 +               bin2bcd(tm->tm_hour),           /* 24-hour */
 299 +               bin2bcd(tm->tm_mday),
 300 +               bin2bcd(tm->tm_wday + 1),
 301 +               bin2bcd(tm->tm_mon + 1),
 302 +               bin2bcd(tm->tm_year % 100)
 303 +       };
 304 +       int ret;
 305 +
 306 +       ret = regmap_bulk_write(pcf85263->regmap, PCF85263_REG_STOPENABLE,
 307 +                               regs, sizeof(regs));
 308 +       if (ret)
 309 +               return ret;
 310 +
 311 +       /* As we have set the time in 24H update the hardware for that */
 312 +       if (pcf85263->mode_12h) {
 313 +               pcf85263->mode_12h = false;
 314 +               ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_OSC,
 315 +                                        PCF85263_REG_OSC_12H, 0);
 316 +               if (ret)
 317 +                       return ret;
 318 +       }
 319 +
 320 +       /* Start it again */
 321 +       return regmap_write(pcf85263->regmap, PCF85263_REG_STOPENABLE, 0);
 322 +}
 323 +
 324 +static int pcf85263_enable_alarm(struct pcf85263 *pcf85263, bool enable)
 325 +{
 326 +       int reg;
 327 +       int ret;
 328 +
 329 +       ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_ALM_CTL,
 330 +                                PCF85263_REG_ALM_CTL_ALL_A1E,
 331 +                                enable ? PCF85263_REG_ALM_CTL_ALL_A1E : 0);
 332 +       if (ret)
 333 +               return ret;
 334 +
 335 +       switch (pcf85263->irq_pin) {
 336 +       case PCF85263_IRQPIN_NONE:
 337 +               return 0;
 338 +
 339 +       case PCF85263_IRQPIN_INTA:
 340 +               reg = PCF85263_REG_INTA_CTL;
 341 +               break;
 342 +
 343 +       case PCF85263_IRQPIN_INTB:
 344 +               reg = PCF85263_REG_INTB_CTL;
 345 +               break;
 346 +
 347 +       default:
 348 +               return -EINVAL;
 349 +       }
 350 +
 351 +       return regmap_update_bits(pcf85263->regmap, reg,
 352 +                                 PCF85263_REG_INTx_CTL_A1E,
 353 +                                 enable ? PCF85263_REG_INTx_CTL_A1E : 0);
 354 +}
 355 +
 356 +static int pcf85263_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 357 +{
 358 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 359 +       struct rtc_time *tm = &alarm->time;
 360 +       const int first = PCF85263_REG_ALM1_SC;
 361 +       const int last = PCF85263_REG_ALM1_MO;
 362 +       const int len = last - first + 1;
 363 +       u8 regs[len];
 364 +       u8 hr_reg;
 365 +       unsigned int regval;
 366 +       int ret;
 367 +
 368 +       ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
 369 +       if (ret)
 370 +               return ret;
 371 +
 372 +       tm->tm_sec = bcd2bin(regs[PCF85263_REG_ALM1_SC - first] & 0x7f);
 373 +       tm->tm_min = bcd2bin(regs[PCF85263_REG_ALM1_MN - first] & 0x7f);
 374 +
 375 +       hr_reg = regs[PCF85263_REG_ALM1_HR - first];
 376 +       if (pcf85263->mode_12h)
 377 +               tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
 378 +       else
 379 +               tm->tm_hour = bcd2bin(hr_reg & 0x3f);
 380 +
 381 +       tm->tm_mday = bcd2bin(regs[PCF85263_REG_ALM1_DT - first]);
 382 +       tm->tm_mon  = bcd2bin(regs[PCF85263_REG_ALM1_MO - first]) - 1;
 383 +       tm->tm_year = -1;
 384 +       tm->tm_wday = -1;
 385 +
 386 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_ALM_CTL, &regval);
 387 +       if (ret)
 388 +               return ret;
 389 +       alarm->enabled = !!(regval & PCF85263_REG_ALM_CTL_ALL_A1E);
 390 +
 391 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, &regval);
 392 +       if (ret)
 393 +               return ret;
 394 +       alarm->pending = !!(regval & PCF85263_REG_FLAGS_A1F);
 395 +
 396 +       return 0;
 397 +}
 398 +
 399 +static int pcf85263_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 400 +{
 401 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 402 +       struct rtc_time *tm = &alarm->time;
 403 +       const int first = PCF85263_REG_ALM1_SC;
 404 +       const int last = PCF85263_REG_ALM1_MO;
 405 +       const int len = last - first + 1;
 406 +       u8 regs[len];
 407 +       int ret;
 408 +
 409 +       /* Disable alarm comparison during update */
 410 +       ret = pcf85263_enable_alarm(pcf85263, false);
 411 +       if (ret)
 412 +               return ret;
 413 +
 414 +       /* Clear any pending alarm (write 0=>clr, 1=>no change) */
 415 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
 416 +                          (unsigned int)(~PCF85263_REG_FLAGS_A1F));
 417 +       if (ret)
 418 +               return ret;
 419 +
 420 +       /* Set the alarm time registers */
 421 +       regs[PCF85263_REG_ALM1_SC - first] = bin2bcd(tm->tm_sec);
 422 +       regs[PCF85263_REG_ALM1_MN - first] = bin2bcd(tm->tm_min);
 423 +       regs[PCF85263_REG_ALM1_HR - first] = pcf85263->mode_12h ?
 424 +                       pcf85263_bin24h_to_bcd12h(tm->tm_hour) :
 425 +                       bin2bcd(tm->tm_hour);
 426 +       regs[PCF85263_REG_ALM1_DT - first] = bin2bcd(tm->tm_mday);
 427 +       regs[PCF85263_REG_ALM1_MO - first] = bin2bcd(tm->tm_mon + 1);
 428 +
 429 +       ret = regmap_bulk_write(pcf85263->regmap, first, regs, sizeof(regs));
 430 +       if (ret)
 431 +               return ret;
 432 +
 433 +       if (alarm->enabled)
 434 +               ret = pcf85263_enable_alarm(pcf85263, true);
 435 +
 436 +       return ret;
 437 +}
 438 +
 439 +static int pcf85263_alarm_irq_enable(struct device *dev, unsigned int enable)
 440 +{
 441 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 442 +
 443 +       return pcf85263_enable_alarm(pcf85263, !!enable);
 444 +}
 445 +
 446 +static irqreturn_t pcf85263_irq(int irq, void *data)
 447 +{
 448 +       struct pcf85263 *pcf85263 = data;
 449 +       unsigned int regval;
 450 +       int ret;
 451 +
 452 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, &regval);
 453 +       if (ret)
 454 +               return IRQ_NONE;
 455 +
 456 +       if (regval & PCF85263_REG_FLAGS_A1F) {
 457 +               regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
 458 +                            (unsigned int)(~PCF85263_REG_FLAGS_A1F));
 459 +
 460 +               rtc_update_irq(pcf85263->rtc, 1, RTC_IRQF | RTC_AF);
 461 +
 462 +               return IRQ_HANDLED;
 463 +       }
 464 +
 465 +       return IRQ_NONE;
 466 +}
 467 +
 468 +static int pcf85263_check_osc_stopped(struct pcf85263 *pcf85263)
 469 +{
 470 +       unsigned int regval;
 471 +       int ret;
 472 +
 473 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_RTC_SC, &regval);
 474 +       if (ret)
 475 +               return ret;
 476 +
 477 +       ret = regval & PCF85263_REG_RTC_SC_OS ? 1 : 0;
 478 +       if (ret)
 479 +               dev_warn(pcf85263->dev, "Oscillator stop detected, date/time is not reliable.\n");
 480 +
 481 +       return ret;
 482 +}
 483 +
 484 +#ifdef CONFIG_RTC_INTF_DEV
 485 +static int pcf85263_ioctl(struct device *dev,
 486 +                         unsigned int cmd, unsigned long arg)
 487 +{
 488 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 489 +       int ret;
 490 +
 491 +       switch (cmd) {
 492 +       case RTC_VL_READ:
 493 +               ret = pcf85263_check_osc_stopped(pcf85263);
 494 +               if (ret < 0)
 495 +                       return ret;
 496 +
 497 +               if (copy_to_user((void __user *)arg, &ret, sizeof(int)))
 498 +                       return -EFAULT;
 499 +               return 0;
 500 +
 501 +       case RTC_VL_CLR:
 502 +               return regmap_update_bits(pcf85263->regmap,
 503 +                                         PCF85263_REG_RTC_SC,
 504 +                                         PCF85263_REG_RTC_SC_OS, 0);
 505 +       default:
 506 +               return -ENOIOCTLCMD;
 507 +       }
 508 +}
 509 +#else
 510 +#define pcf85263_ioctl NULL
 511 +#endif
 512 +
 513 +static int pcf85263_init_hw(struct pcf85263 *pcf85263)
 514 +{
 515 +       struct device_node *np = pcf85263->dev->of_node;
 516 +       unsigned int regval;
 517 +       u32 propval;
 518 +       int ret;
 519 +
 520 +       /* Determine if oscilator has been stopped (probably low power) */
 521 +       ret = pcf85263_check_osc_stopped(pcf85263);
 522 +       if (ret < 0) {
 523 +               /* Log here since this is the first hw access on probe */
 524 +               dev_err(pcf85263->dev, "Unable to read register\n");
 525 +
 526 +               return ret;
 527 +       }
 528 +
 529 +       /* Determine 12/24H mode */
 530 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_OSC, &regval);
 531 +       if (ret)
 532 +               return ret;
 533 +       pcf85263->mode_12h = !!(regval & PCF85263_REG_OSC_12H);
 534 +
 535 +       /* Set oscilator register */
 536 +       regval &= ~PCF85263_REG_OSC_12H; /* keep current 12/24 h setting */
 537 +
 538 +       propval = PCF85263_QUARTZCAP_12p5pF;
 539 +       of_property_read_u32(np, "quartz-load-capacitance", &propval);
 540 +       regval |= ((propval << PCF85263_REG_OSC_CL_SHIFT)
 541 +                   & PCF85263_REG_OSC_CL_MASK);
 542 +
 543 +       propval = PCF85263_QUARTZDRIVE_NORMAL;
 544 +       of_property_read_u32(np, "quartz-drive-strength", &propval);
 545 +       regval |= ((propval << PCF85263_REG_OSC_OSCD_SHIFT)
 546 +                   & PCF85263_REG_OSC_OSCD_MASK);
 547 +
 548 +       if (of_property_read_bool(np, "quartz-low-jitter"))
 549 +               regval |= PCF85263_REG_OSC_LOWJ;
 550 +
 551 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_OSC, regval);
 552 +       if (ret)
 553 +               return ret;
 554 +
 555 +       /* Set function register (RTC mode, 1s tick, clock output static) */
 556 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_FUNCTION,
 557 +                          PCF85263_REG_FUNCTION_COF_OFF);
 558 +       if (ret)
 559 +               return ret;
 560 +
 561 +       /* Set all interrupts to disabled, level mode */
 562 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTA_CTL,
 563 +                          PCF85263_REG_INTx_CTL_ILP);
 564 +       if (ret)
 565 +               return ret;
 566 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTB_CTL,
 567 +                          PCF85263_REG_INTx_CTL_ILP);
 568 +       if (ret)
 569 +               return ret;
 570 +
 571 +       /* Setup IO pin config register */
 572 +       regval = PCF85263_REG_PINIO_CLKDISABLE;
 573 +       switch (pcf85263->irq_pin) {
 574 +       case PCF85263_IRQPIN_INTA:
 575 +               regval |= (PCF85263_INTAPM_INTA | PCF85263_TSPM_DISABLED);
 576 +               break;
 577 +       case PCF85263_IRQPIN_INTB:
 578 +               regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_INTB);
 579 +               break;
 580 +       case PCF85263_IRQPIN_NONE:
 581 +               regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_DISABLED);
 582 +               break;
 583 +       }
 584 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_PINIO, regval);
 585 +
 586 +       return ret;
 587 +}
 588 +
 589 +static const struct rtc_class_ops rtc_ops = {
 590 +       .ioctl = pcf85263_ioctl,
 591 +       .read_time = pcf85263_read_time,
 592 +       .set_time = pcf85263_set_time,
 593 +       .read_alarm = pcf85263_read_alarm,
 594 +       .set_alarm = pcf85263_set_alarm,
 595 +       .alarm_irq_enable = pcf85263_alarm_irq_enable,
 596 +};
 597 +
 598 +static const struct regmap_config pcf85263_regmap_cfg = {
 599 +       .reg_bits = 8,
 600 +       .val_bits = 8,
 601 +       .max_register = PCF85263_MAX_REG,
 602 +};
 603 +
 604 +/*
 605 + * On some boards the interrupt line may not be wired to the CPU but only to
 606 + * a power supply circuit.
 607 + * In that case no interrupt will be specified in the device tree but the
 608 + * wakeup-source DT property may be used to enable wakeup programming in
 609 + * sysfs
 610 + */
 611 +static bool pcf85263_can_wakeup_machine(struct pcf85263 *pcf85263)
 612 +{
 613 +       return pcf85263->irq ||
 614 +               of_property_read_bool(pcf85263->dev->of_node, "wakeup-source");
 615 +}
 616 +
 617 +static int pcf85263_probe(struct i2c_client *client,
 618 +                               const struct i2c_device_id *id)
 619 +{
 620 +       struct device *dev = &client->dev;
 621 +       struct pcf85263 *pcf85263;
 622 +       int ret;
 623 +
 624 +       if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
 625 +                                    I2C_FUNC_SMBUS_BYTE_DATA |
 626 +                                    I2C_FUNC_SMBUS_I2C_BLOCK))
 627 +               return -ENODEV;
 628 +
 629 +       pcf85263 = devm_kzalloc(dev, sizeof(*pcf85263), GFP_KERNEL);
 630 +       if (!pcf85263)
 631 +               return -ENOMEM;
 632 +
 633 +       pcf85263->dev = dev;
 634 +       pcf85263->irq = client->irq;
 635 +       dev_set_drvdata(dev, pcf85263);
 636 +
 637 +       pcf85263->regmap = devm_regmap_init_i2c(client, &pcf85263_regmap_cfg);
 638 +       if (IS_ERR(pcf85263->regmap)) {
 639 +               ret = PTR_ERR(pcf85263->regmap);
 640 +               dev_err(dev, "regmap allocation failed (%d)\n", ret);
 641 +
 642 +               return ret;
 643 +       }
 644 +
 645 +       /* Determine which interrupt pin the board uses */
 646 +       if (pcf85263_can_wakeup_machine(pcf85263)) {
 647 +               if (of_property_match_string(dev->of_node,
 648 +                                            "interrupt-names", "INTB") >= 0)
 649 +                       pcf85263->irq_pin = PCF85263_IRQPIN_INTB;
 650 +               else
 651 +                       pcf85263->irq_pin = PCF85263_IRQPIN_INTA;
 652 +       } else {
 653 +               pcf85263->irq_pin = PCF85263_IRQPIN_NONE;
 654 +       }
 655 +
 656 +       ret = pcf85263_init_hw(pcf85263);
 657 +       if (ret)
 658 +               return ret;
 659 +
 660 +       if (pcf85263->irq) {
 661 +               ret = devm_request_threaded_irq(dev, pcf85263->irq, NULL,
 662 +                                               pcf85263_irq,
 663 +                                               IRQF_ONESHOT,
 664 +                                               dev->driver->name, pcf85263);
 665 +               if (ret) {
 666 +                       dev_err(dev, "irq %d unavailable (%d)\n",
 667 +                               pcf85263->irq, ret);
 668 +                       pcf85263->irq = 0;
 669 +               }
 670 +       }
 671 +
 672 +       if (pcf85263_can_wakeup_machine(pcf85263))
 673 +               device_init_wakeup(dev, true);
 674 +
 675 +       pcf85263->rtc = devm_rtc_device_register(dev, dev->driver->name,
 676 +                                                &rtc_ops, THIS_MODULE);
 677 +       ret = PTR_ERR_OR_ZERO(pcf85263->rtc);
 678 +       if (ret)
 679 +               return ret;
 680 +
 681 +       /* We cannot support UIE mode if we do not have an IRQ line */
 682 +       if (!pcf85263->irq)
 683 +               pcf85263->rtc->uie_unsupported = 1;
 684 +
 685 +       dev_info(pcf85263->dev,
 686 +                "PCF85263 RTC (irqpin=%s irq=%d)\n",
 687 +                pcf85263_irqpin_names[pcf85263->irq_pin],
 688 +                pcf85263->irq);
 689 +
 690 +       return 0;
 691 +}
 692 +
 693 +static int pcf85263_remove(struct i2c_client *client)
 694 +{
 695 +       struct pcf85263 *pcf85263 = i2c_get_clientdata(client);
 696 +
 697 +       if (pcf85263_can_wakeup_machine(pcf85263))
 698 +               device_init_wakeup(pcf85263->dev, false);
 699 +
 700 +       return 0;
 701 +}
 702 +
 703 +#ifdef CONFIG_PM_SLEEP
 704 +static int pcf85263_suspend(struct device *dev)
 705 +{
 706 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 707 +       int ret = 0;
 708 +
 709 +       if (device_may_wakeup(dev))
 710 +               ret = enable_irq_wake(pcf85263->irq);
 711 +
 712 +       return ret;
 713 +}
 714 +
 715 +static int pcf85263_resume(struct device *dev)
 716 +{
 717 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 718 +       int ret = 0;
 719 +
 720 +       if (device_may_wakeup(dev))
 721 +               ret = disable_irq_wake(pcf85263->irq);
 722 +
 723 +       return ret;
 724 +}
 725 +
 726 +#endif
 727 +
 728 +static const struct i2c_device_id pcf85263_id[] = {
 729 +       { "pcf85263", 0 },
 730 +       { }
 731 +};
 732 +MODULE_DEVICE_TABLE(i2c, pcf85263_id);
 733 +
 734 +#ifdef CONFIG_OF
 735 +static const struct of_device_id pcf85263_of_match[] = {
 736 +       { .compatible = "nxp,pcf85263" },
 737 +       {}
 738 +};
 739 +MODULE_DEVICE_TABLE(of, pcf85263_of_match);
 740 +#endif
 741 +
 742 +static SIMPLE_DEV_PM_OPS(pcf85263_pm_ops, pcf85263_suspend,  pcf85263_resume);
 743 +
 744 +static struct i2c_driver pcf85263_driver = {
 745 +       .driver         = {
 746 +               .name   = "rtc-pcf85263",
 747 +               .of_match_table = of_match_ptr(pcf85263_of_match),
 748 +               .pm = &pcf85263_pm_ops,
 749 +       },
 750 +       .probe          = pcf85263_probe,
 751 +       .remove         = pcf85263_remove,
 752 +       .id_table       = pcf85263_id,
 753 +};
 754 +
 755 +module_i2c_driver(pcf85263_driver);
 756 +
 757 +MODULE_AUTHOR("Martin Fuzzey <mfuzzey@parkeon.com>");
 758 +MODULE_DESCRIPTION("PCF85263 RTC Driver");
 759 +MODULE_LICENSE("GPL");
 760 --- /dev/null
 761 +++ b/include/dt-bindings/rtc/nxp,pcf85263.h
 762 @@ -0,0 +1,14 @@
 763 +#ifndef _DT_BINDINGS_RTC_NXP_PCF85263_H
 764 +#define _DT_BINDINGS_RTC_NXP_PCF85263_H
 765 +
 766 +/* Quartz capacitance */
 767 +#define PCF85263_QUARTZCAP_7pF         0
 768 +#define PCF85263_QUARTZCAP_6pF         1
 769 +#define PCF85263_QUARTZCAP_12p5pF      2
 770 +
 771 +/* Quartz drive strength */
 772 +#define PCF85263_QUARTZDRIVE_NORMAL    0
 773 +#define PCF85263_QUARTZDRIVE_LOW       1
 774 +#define PCF85263_QUARTZDRIVE_HIGH      2
 775 +
 776 +#endif /* _DT_BINDINGS_RTC_NXP_PCF85263_H */