target/linux/layerscape/patches-4.14/804-i2c-support-layerscape.patch

   1 From 3f7d59061c38287bdc2fec2e94b4df9e6e62dbc6 Mon Sep 17 00:00:00 2001
   2 From: Biwen Li <biwen.li@nxp.com>
   3 Date: Wed, 17 Apr 2019 18:58:39 +0800
   4 Subject: [PATCH] i2c: support layerscape
   5
   6 This is an integrated patch of i2c for layerscape
   7
   8 Signed-off-by: Biwen Li <biwen.li@nxp.com>
   9 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
  10 Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
  11 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
  12 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
  13 ---
  14  drivers/i2c/busses/i2c-imx.c        | 245 +++++++++++++++++++++++++---
  15  drivers/i2c/muxes/i2c-mux-pca954x.c |  44 ++++-
  16  2 files changed, 268 insertions(+), 21 deletions(-)
  17
  18 --- a/drivers/i2c/busses/i2c-imx.c
  19 +++ b/drivers/i2c/busses/i2c-imx.c
  20 @@ -53,6 +53,11 @@
  21  #include <linux/pm_runtime.h>
  22  #include <linux/sched.h>
  23  #include <linux/slab.h>
  24 +#include <linux/gpio.h>
  25 +#include <linux/of_address.h>
  26 +#include <linux/of.h>
  27 +#include <linux/of_device.h>
  28 +#include <linux/libata.h>
  29
  30  /* This will be the driver name the kernel reports */
  31  #define DRIVER_NAME "imx-i2c"
  32 @@ -117,6 +122,54 @@
  33
  34  #define I2C_PM_TIMEOUT         10 /* ms */
  35
  36 +enum pinmux_endian_type {
  37 +       BIG_ENDIAN,
  38 +       LITTLE_ENDIAN,
  39 +};
  40 +
  41 +struct pinmux_cfg {
  42 +       enum pinmux_endian_type endian; /* endian of RCWPMUXCR0 */
  43 +       u32 pmuxcr_offset;
  44 +       u32 pmuxcr_set_bit;                 /* pin mux of RCWPMUXCR0 */
  45 +};
  46 +
  47 +static struct pinmux_cfg ls1012a_pinmux_cfg = {
  48 +       .endian = BIG_ENDIAN,
  49 +       .pmuxcr_offset = 0x430,
  50 +       .pmuxcr_set_bit = 0x10,
  51 +};
  52 +
  53 +static struct pinmux_cfg ls1043a_pinmux_cfg = {
  54 +       .endian = BIG_ENDIAN,
  55 +       .pmuxcr_offset = 0x40C,
  56 +       .pmuxcr_set_bit = 0x10,
  57 +};
  58 +
  59 +static struct pinmux_cfg ls1046a_pinmux_cfg = {
  60 +       .endian = BIG_ENDIAN,
  61 +       .pmuxcr_offset = 0x40C,
  62 +       .pmuxcr_set_bit = 0x80000000,
  63 +};
  64 +
  65 +static const struct of_device_id pinmux_of_match[] = {
  66 +       { .compatible = "fsl,ls1012a-vf610-i2c", .data = &ls1012a_pinmux_cfg},
  67 +       { .compatible = "fsl,ls1043a-vf610-i2c", .data = &ls1043a_pinmux_cfg},
  68 +       { .compatible = "fsl,ls1046a-vf610-i2c", .data = &ls1046a_pinmux_cfg},
  69 +       {},
  70 +};
  71 +MODULE_DEVICE_TABLE(of, pinmux_of_match);
  72 +
  73 +/* The SCFG, Supplemental Configuration Unit, provides SoC specific
  74 + * configuration and status registers for the device. There is a
  75 + * SDHC IO VSEL control register on SCFG for some platforms. It's
  76 + * used to support SDHC IO voltage switching.
  77 + */
  78 +static const struct of_device_id scfg_device_ids[] = {
  79 +       { .compatible = "fsl,ls1012a-scfg", },
  80 +       { .compatible = "fsl,ls1043a-scfg", },
  81 +       { .compatible = "fsl,ls1046a-scfg", },
  82 +       {}
  83 +};
  84  /*
  85   * sorted list of clock divider, register value pairs
  86   * taken from table 26-5, p.26-9, Freescale i.MX
  87 @@ -210,6 +263,12 @@ struct imx_i2c_struct {
  88         struct pinctrl_state *pinctrl_pins_gpio;
  89
  90         struct imx_i2c_dma      *dma;
  91 +       int                     layerscape_bus_recover;
  92 +       int                     gpio;
  93 +       int                     need_set_pmuxcr;
  94 +       int                     pmuxcr_set;
  95 +       int                     pmuxcr_endian;
  96 +       void __iomem            *pmuxcr_addr;
  97  };
  98
  99  static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 100 @@ -281,8 +340,8 @@ static inline unsigned char imx_i2c_read
 101  }
 102
 103  /* Functions for DMA support */
 104 -static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 105 -                                               dma_addr_t phy_addr)
 106 +static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 107 +                              dma_addr_t phy_addr)
 108  {
 109         struct imx_i2c_dma *dma;
 110         struct dma_slave_config dma_sconfig;
 111 @@ -291,11 +350,13 @@ static void i2c_imx_dma_request(struct i
 112
 113         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 114         if (!dma)
 115 -               return;
 116 +               return -ENOMEM;
 117
 118 -       dma->chan_tx = dma_request_slave_channel(dev, "tx");
 119 -       if (!dma->chan_tx) {
 120 -               dev_dbg(dev, "can't request DMA tx channel\n");
 121 +       dma->chan_tx = dma_request_chan(dev, "tx");
 122 +       if (IS_ERR(dma->chan_tx)) {
 123 +               ret = PTR_ERR(dma->chan_tx);
 124 +               if (ret != -ENODEV && ret != -EPROBE_DEFER)
 125 +                       dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
 126                 goto fail_al;
 127         }
 128
 129 @@ -306,13 +367,15 @@ static void i2c_imx_dma_request(struct i
 130         dma_sconfig.direction = DMA_MEM_TO_DEV;
 131         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 132         if (ret < 0) {
 133 -               dev_dbg(dev, "can't configure tx channel\n");
 134 +               dev_err(dev, "can't configure tx channel (%d)\n", ret);
 135                 goto fail_tx;
 136         }
 137
 138 -       dma->chan_rx = dma_request_slave_channel(dev, "rx");
 139 -       if (!dma->chan_rx) {
 140 -               dev_dbg(dev, "can't request DMA rx channel\n");
 141 +       dma->chan_rx = dma_request_chan(dev, "rx");
 142 +       if (IS_ERR(dma->chan_rx)) {
 143 +               ret = PTR_ERR(dma->chan_rx);
 144 +               if (ret != -ENODEV && ret != -EPROBE_DEFER)
 145 +                       dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
 146                 goto fail_tx;
 147         }
 148
 149 @@ -323,7 +386,7 @@ static void i2c_imx_dma_request(struct i
 150         dma_sconfig.direction = DMA_DEV_TO_MEM;
 151         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 152         if (ret < 0) {
 153 -               dev_dbg(dev, "can't configure rx channel\n");
 154 +               dev_err(dev, "can't configure rx channel (%d)\n", ret);
 155                 goto fail_rx;
 156         }
 157
 158 @@ -332,7 +395,7 @@ static void i2c_imx_dma_request(struct i
 159         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 160                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 161
 162 -       return;
 163 +       return 0;
 164
 165  fail_rx:
 166         dma_release_channel(dma->chan_rx);
 167 @@ -340,7 +403,8 @@ fail_tx:
 168         dma_release_channel(dma->chan_tx);
 169  fail_al:
 170         devm_kfree(dev, dma);
 171 -       dev_info(dev, "can't use DMA, using PIO instead.\n");
 172 +       /* return successfully if there is no dma support */
 173 +       return ret == -ENODEV ? 0 : ret;
 174  }
 175
 176  static void i2c_imx_dma_callback(void *arg)
 177 @@ -878,6 +942,78 @@ static int i2c_imx_read(struct imx_i2c_s
 178         return 0;
 179  }
 180
 181 +/*
 182 + * Based on the I2C specification, if the data line (SDA) is
 183 + * stuck low, the master should send nine  * clock pulses.
 184 + * The I2C slave device that held the bus low should release it
 185 + * sometime within  * those nine clocks. Due to this erratum,
 186 + * the I2C controller cannot generate nine clock pulses.
 187 + */
 188 +static int i2c_imx_recovery_for_layerscape(struct imx_i2c_struct *i2c_imx)
 189 +{
 190 +       u32 pmuxcr = 0;
 191 +       int ret;
 192 +       unsigned int i, temp;
 193 +
 194 +       /* configure IICx_SCL/GPIO pin as a GPIO */
 195 +       if (i2c_imx->need_set_pmuxcr == 1) {
 196 +               pmuxcr = ioread32be(i2c_imx->pmuxcr_addr);
 197 +               if (i2c_imx->pmuxcr_endian == BIG_ENDIAN)
 198 +                       iowrite32be(i2c_imx->pmuxcr_set|pmuxcr,
 199 +                                   i2c_imx->pmuxcr_addr);
 200 +               else
 201 +                       iowrite32(i2c_imx->pmuxcr_set|pmuxcr,
 202 +                                 i2c_imx->pmuxcr_addr);
 203 +       }
 204 +
 205 +       ret = gpio_request(i2c_imx->gpio, i2c_imx->adapter.name);
 206 +       if (ret) {
 207 +               dev_err(&i2c_imx->adapter.dev,
 208 +                       "can't get gpio: %d\n", ret);
 209 +               return ret;
 210 +       }
 211 +
 212 +       /* Configure GPIO pin as an output and open drain. */
 213 +       gpio_direction_output(i2c_imx->gpio, 1);
 214 +       udelay(10);
 215 +
 216 +       /* Write data to generate 9 pulses */
 217 +       for (i = 0; i < 9; i++) {
 218 +               gpio_set_value(i2c_imx->gpio, 1);
 219 +               udelay(10);
 220 +               gpio_set_value(i2c_imx->gpio, 0);
 221 +               udelay(10);
 222 +       }
 223 +       /* ensure that the last level sent is always high */
 224 +       gpio_set_value(i2c_imx->gpio, 1);
 225 +
 226 +       /*
 227 +        * Set I2Cx_IBCR = 0h00 to generate a STOP and then
 228 +        * set I2Cx_IBCR = 0h80 to reset
 229 +        */
 230 +       temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 231 +       temp &= ~(I2CR_MSTA | I2CR_MTX);
 232 +       imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 233 +
 234 +       /* Restore the saved value of the register SCFG_RCWPMUXCR0 */
 235 +       if (i2c_imx->need_set_pmuxcr == 1) {
 236 +               if (i2c_imx->pmuxcr_endian == BIG_ENDIAN)
 237 +                       iowrite32be(pmuxcr, i2c_imx->pmuxcr_addr);
 238 +               else
 239 +                       iowrite32(pmuxcr, i2c_imx->pmuxcr_addr);
 240 +       }
 241 +       /*
 242 +        * Set I2C_IBSR[IBAL] to clear the IBAL bit if-
 243 +        * I2C_IBSR[IBAL] = 1
 244 +        */
 245 +       temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 246 +       if (temp & I2SR_IAL) {
 247 +               temp &= ~I2SR_IAL;
 248 +               imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 249 +       }
 250 +       return 0;
 251 +}
 252 +
 253  static int i2c_imx_xfer(struct i2c_adapter *adapter,
 254                                                 struct i2c_msg *msgs, int num)
 255  {
 256 @@ -888,6 +1024,19 @@ static int i2c_imx_xfer(struct i2c_adapt
 257
 258         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 259
 260 +       /*
 261 +        * workround for ERR010027: ensure that the I2C BUS is idle
 262 +        * before switching to master mode and attempting a Start cycle
 263 +        */
 264 +       result =  i2c_imx_bus_busy(i2c_imx, 0);
 265 +       if (result) {
 266 +               /* timeout */
 267 +               if ((result == -ETIMEDOUT) && (i2c_imx->layerscape_bus_recover == 1))
 268 +                       i2c_imx_recovery_for_layerscape(i2c_imx);
 269 +               else
 270 +                       goto out;
 271 +       }
 272 +
 273         result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
 274         if (result < 0)
 275                 goto out;
 276 @@ -1030,6 +1179,50 @@ static int i2c_imx_init_recovery_info(st
 277         return 0;
 278  }
 279
 280 +/*
 281 + * switch SCL and SDA to their GPIO function and do some bitbanging
 282 + * for bus recovery.
 283 + * There are platforms such as Layerscape that don't support pinctrl, so add
 284 + * workaround for layerscape, it has no effect for other platforms.
 285 + */
 286 +static int i2c_imx_init_recovery_for_layerscape(
 287 +               struct imx_i2c_struct *i2c_imx,
 288 +               struct platform_device *pdev)
 289 +{
 290 +       const struct of_device_id *of_id;
 291 +       struct device_node *np          = pdev->dev.of_node;
 292 +       struct pinmux_cfg               *pinmux_cfg;
 293 +       struct device_node *scfg_node;
 294 +       void __iomem *scfg_base = NULL;
 295 +
 296 +       i2c_imx->gpio = of_get_named_gpio(np, "fsl-scl-gpio", 0);
 297 +       if (!gpio_is_valid(i2c_imx->gpio)) {
 298 +               dev_info(&pdev->dev, "fsl-scl-gpio not found\n");
 299 +               return 0;
 300 +       }
 301 +       pinmux_cfg = devm_kzalloc(&pdev->dev, sizeof(*pinmux_cfg), GFP_KERNEL);
 302 +       if (!pinmux_cfg)
 303 +               return -ENOMEM;
 304 +
 305 +       i2c_imx->need_set_pmuxcr = 0;
 306 +       of_id = of_match_node(pinmux_of_match, np);
 307 +       if (of_id) {
 308 +               pinmux_cfg = (struct pinmux_cfg *)of_id->data;
 309 +               i2c_imx->pmuxcr_endian = pinmux_cfg->endian;
 310 +               i2c_imx->pmuxcr_set = pinmux_cfg->pmuxcr_set_bit;
 311 +               scfg_node = of_find_matching_node(NULL, scfg_device_ids);
 312 +               if (scfg_node) {
 313 +                       scfg_base = of_iomap(scfg_node, 0);
 314 +                       if (scfg_base) {
 315 +                               i2c_imx->pmuxcr_addr = scfg_base + pinmux_cfg->pmuxcr_offset;
 316 +                               i2c_imx->need_set_pmuxcr = 1;
 317 +                       }
 318 +               }
 319 +       }
 320 +       i2c_imx->layerscape_bus_recover = 1;
 321 +       return 0;
 322 +}
 323 +
 324  static u32 i2c_imx_func(struct i2c_adapter *adapter)
 325  {
 326         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 327 @@ -1085,6 +1278,11 @@ static int i2c_imx_probe(struct platform
 328         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
 329         i2c_imx->base                   = base;
 330
 331 +       /* Init optional bus recovery for layerscape */
 332 +       ret = i2c_imx_init_recovery_for_layerscape(i2c_imx, pdev);
 333 +       if (ret)
 334 +               return ret;
 335 +
 336         /* Get I2C clock */
 337         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
 338         if (IS_ERR(i2c_imx->clk)) {
 339 @@ -1103,7 +1301,8 @@ static int i2c_imx_probe(struct platform
 340                                 pdev->name, i2c_imx);
 341         if (ret) {
 342                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
 343 -               goto clk_disable;
 344 +               clk_disable_unprepare(i2c_imx->clk);
 345 +               return ret;
 346         }
 347
 348         /* Init queue */
 349 @@ -1150,25 +1349,31 @@ static int i2c_imx_probe(struct platform
 350         pm_runtime_mark_last_busy(&pdev->dev);
 351         pm_runtime_put_autosuspend(&pdev->dev);
 352
 353 +       /* Init DMA config if supported */
 354 +       ret = i2c_imx_dma_request(i2c_imx, phy_addr);
 355 +       if (ret) {
 356 +               if (ret != -EPROBE_DEFER)
 357 +                       dev_info(&pdev->dev, "can't use DMA, using PIO instead.\n");
 358 +               else
 359 +                       goto del_adapter;
 360 +       }
 361 +
 362         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
 363         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
 364         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
 365                 i2c_imx->adapter.name);
 366 -       dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
 367 -
 368 -       /* Init DMA config if supported */
 369 -       i2c_imx_dma_request(i2c_imx, phy_addr);
 370
 371 +       dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
 372         return 0;   /* Return OK */
 373
 374 +del_adapter:
 375 +       i2c_del_adapter(&i2c_imx->adapter);
 376  rpm_disable:
 377         pm_runtime_put_noidle(&pdev->dev);
 378         pm_runtime_disable(&pdev->dev);
 379         pm_runtime_set_suspended(&pdev->dev);
 380         pm_runtime_dont_use_autosuspend(&pdev->dev);
 381
 382 -clk_disable:
 383 -       clk_disable_unprepare(i2c_imx->clk);
 384         return ret;
 385  }
 386
 387 --- a/drivers/i2c/muxes/i2c-mux-pca954x.c
 388 +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
 389 @@ -85,6 +85,7 @@ struct pca954x {
 390         struct irq_domain *irq;
 391         unsigned int irq_mask;
 392         raw_spinlock_t lock;
 393 +       u8 disable_mux;         /* do not disable mux if val not 0 */
 394  };
 395
 396  /* Provide specs for the PCA954x types we know about */
 397 @@ -221,6 +222,13 @@ static int pca954x_deselect_mux(struct i
 398         if (!(data->deselect & (1 << chan)))
 399                 return 0;
 400
 401 +#ifdef CONFIG_ARCH_LAYERSCAPE
 402 +       if (data->disable_mux != 0)
 403 +               data->last_chan = data->chip->nchans;
 404 +       else
 405 +               data->last_chan = 0;
 406 +       return pca954x_reg_write(muxc->parent, client, data->disable_mux);
 407 +#endif
 408         /* Deselect active channel */
 409         data->last_chan = 0;
 410         return pca954x_reg_write(muxc->parent, client, data->last_chan);
 411 @@ -361,6 +369,28 @@ static int pca954x_probe(struct i2c_clie
 412                 return -ENOMEM;
 413         data = i2c_mux_priv(muxc);
 414
 415 +#ifdef CONFIG_ARCH_LAYERSCAPE
 416 +       /* The point here is that you must not disable a mux if there
 417 +        * are no pullups on the input or you mess up the I2C. This
 418 +        * needs to be put into the DTS really as the kernel cannot
 419 +        * know this otherwise.
 420 +        */
 421 +       match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
 422 +       if (match)
 423 +               data->chip = of_device_get_match_data(&client->dev);
 424 +       else
 425 +               data->chip = &chips[id->driver_data];
 426 +
 427 +       data->disable_mux = of_node &&
 428 +               of_property_read_bool(of_node, "i2c-mux-never-disable") &&
 429 +               data->chip->muxtype == pca954x_ismux ?
 430 +               data->chip->enable : 0;
 431 +       /* force the first selection */
 432 +       if (data->disable_mux != 0)
 433 +               data->last_chan = data->chip->nchans;
 434 +       else
 435 +               data->last_chan = 0;
 436 +#endif
 437         i2c_set_clientdata(client, muxc);
 438         data->client = client;
 439
 440 @@ -373,18 +403,23 @@ static int pca954x_probe(struct i2c_clie
 441          * that the mux is in fact present. This also
 442          * initializes the mux to disconnected state.
 443          */
 444 +#ifdef CONFIG_ARCH_LAYERSCAPE
 445 +       if (i2c_smbus_write_byte(client, data->disable_mux) < 0) {
 446 +#else
 447         if (i2c_smbus_write_byte(client, 0) < 0) {
 448 +#endif
 449                 dev_warn(&client->dev, "probe failed\n");
 450                 return -ENODEV;
 451         }
 452
 453 +#ifndef CONFIG_ARCH_LAYERSCAPE
 454         match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
 455         if (match)
 456                 data->chip = of_device_get_match_data(&client->dev);
 457         else
 458                 data->chip = &chips[id->driver_data];
 459 -
 460         data->last_chan = 0;               /* force the first selection */
 461 +#endif
 462
 463         idle_disconnect_dt = of_node &&
 464                 of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
 465 @@ -454,6 +489,13 @@ static int pca954x_resume(struct device
 466         struct i2c_mux_core *muxc = i2c_get_clientdata(client);
 467         struct pca954x *data = i2c_mux_priv(muxc);
 468
 469 +#ifdef CONFIG_ARCH_LAYERSCAPE
 470 +       if (data->disable_mux != 0)
 471 +               data->last_chan = data->chip->nchans;
 472 +       else
 473 +               data->last_chan = 0;
 474 +       return i2c_smbus_write_byte(client, data->disable_mux);
 475 +#endif
 476         data->last_chan = 0;
 477         return i2c_smbus_write_byte(client, 0);
 478  }