target/linux/layerscape/patches-4.14/301-arch-support-layerscape.patch

   1 From f29db0048a07384ee4cd962c676b750e13e5d6b0 Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Mon, 6 May 2019 17:17:58 +0800
   4 Subject: [PATCH] arch: support layerscape
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This is an integrated patch of arch for layerscape
  10
  11 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
  12 Signed-off-by: Alison Wang <alison.wang@freescale.com>
  13 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
  14 Signed-off-by: Biwen Li <biwen.li@nxp.com>
  15 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
  16 Signed-off-by: Dave Liu <daveliu@freescale.com>
  17 Signed-off-by: Guanhua <guanhua.gao@nxp.com>
  18 Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
  19 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
  20 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
  21 Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
  22 Signed-off-by: Jin Qing <b24347@freescale.com>
  23 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
  24 Signed-off-by: Li Yang <leoli@freescale.com>
  25 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
  26 Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
  27 Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
  28 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
  29 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
  30 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
  31 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  32 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
  33 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
  34 Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
  35 Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
  36 Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
  37 Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
  38 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  39 Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
  40 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
  41 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
  42 ---
  43  arch/arm/include/asm/delay.h          |  16 ++++++
  44  arch/arm/include/asm/io.h             |  31 ++++++++++
  45  arch/arm/include/asm/mach/map.h       |   4 +-
  46  arch/arm/include/asm/pgtable.h        |   7 +++
  47  arch/arm/kernel/time.c                |   3 +
  48  arch/arm/mm/dma-mapping.c             |   1 +
  49  arch/arm/mm/ioremap.c                 |   7 +++
  50  arch/arm/mm/mmu.c                     |   9 +++
  51  arch/arm64/include/asm/cache.h        |   2 +-
  52  arch/arm64/include/asm/io.h           |   1 +
  53  arch/arm64/include/asm/pgtable-prot.h |   3 +
  54  arch/arm64/include/asm/pgtable.h      |   5 ++
  55  arch/arm64/mm/dma-mapping.c           |   1 +
  56  arch/arm64/mm/init.c                  |  12 ++--
  57  drivers/soc/fsl/guts.c                |   9 +++
  58  drivers/soc/fsl/qixis_ctrl.c          | 105 ++++++++++++++++++++++++++++++++++
  59  16 files changed, 209 insertions(+), 7 deletions(-)
  60  create mode 100644 drivers/soc/fsl/qixis_ctrl.c
  61
  62 --- a/arch/arm/include/asm/delay.h
  63 +++ b/arch/arm/include/asm/delay.h
  64 @@ -85,6 +85,22 @@ extern void __bad_udelay(void);
  65                         __const_udelay((n) * UDELAY_MULT)) :            \
  66           __udelay(n))
  67
  68 +#define spin_event_timeout(condition, timeout, delay)                          \
  69 +({                                                                             \
  70 +       typeof(condition) __ret;                                               \
  71 +       int i = 0;                                                             \
  72 +       while (!(__ret = (condition)) && (i++ < timeout)) {                    \
  73 +               if (delay)                                                     \
  74 +                       udelay(delay);                                         \
  75 +               else                                                           \
  76 +                       cpu_relax();                                           \
  77 +               udelay(1);                                                     \
  78 +       }                                                                      \
  79 +       if (!__ret)                                                            \
  80 +               __ret = (condition);                                           \
  81 +       __ret;                                                                 \
  82 +})
  83 +
  84  /* Loop-based definitions for assembly code. */
  85  extern void __loop_delay(unsigned long loops);
  86  extern void __loop_udelay(unsigned long usecs);
  87 --- a/arch/arm/include/asm/io.h
  88 +++ b/arch/arm/include/asm/io.h
  89 @@ -128,6 +128,7 @@ static inline u32 __raw_readl(const vola
  90  #define MT_DEVICE_NONSHARED    1
  91  #define MT_DEVICE_CACHED       2
  92  #define MT_DEVICE_WC           3
  93 +#define MT_MEMORY_RW_NS                4
  94  /*
  95   * types 4 onwards can be found in asm/mach/map.h and are undefined
  96   * for ioremap
  97 @@ -229,6 +230,34 @@ void __iomem *pci_remap_cfgspace(resourc
  98  #endif
  99  #endif
 100
 101 +/* access ports */
 102 +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
 103 +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
 104 +
 105 +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
 106 +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
 107 +
 108 +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
 109 +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
 110 +
 111 +/* Clear and set bits in one shot.  These macros can be used to clear and
 112 + * set multiple bits in a register using a single read-modify-write.  These
 113 + * macros can also be used to set a multiple-bit bit pattern using a mask,
 114 + * by specifying the mask in the 'clear' parameter and the new bit pattern
 115 + * in the 'set' parameter.
 116 + */
 117 +
 118 +#define clrsetbits_be32(addr, clear, set) \
 119 +       iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
 120 +#define clrsetbits_le32(addr, clear, set) \
 121 +       iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
 122 +#define clrsetbits_be16(addr, clear, set) \
 123 +       iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
 124 +#define clrsetbits_le16(addr, clear, set) \
 125 +       iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
 126 +#define clrsetbits_8(addr, clear, set) \
 127 +       iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
 128 +
 129  /*
 130   *  IO port access primitives
 131   *  -------------------------
 132 @@ -417,6 +446,8 @@ void __iomem *ioremap_wc(resource_size_t
 133  #define ioremap_wc ioremap_wc
 134  #define ioremap_wt ioremap_wc
 135
 136 +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
 137 +
 138  void iounmap(volatile void __iomem *iomem_cookie);
 139  #define iounmap iounmap
 140
 141 --- a/arch/arm/include/asm/mach/map.h
 142 +++ b/arch/arm/include/asm/mach/map.h
 143 @@ -21,9 +21,9 @@ struct map_desc {
 144         unsigned int type;
 145  };
 146
 147 -/* types 0-3 are defined in asm/io.h */
 148 +/* types 0-4 are defined in asm/io.h */
 149  enum {
 150 -       MT_UNCACHED = 4,
 151 +       MT_UNCACHED = 5,
 152         MT_CACHECLEAN,
 153         MT_MINICLEAN,
 154         MT_LOW_VECTORS,
 155 --- a/arch/arm/include/asm/pgtable.h
 156 +++ b/arch/arm/include/asm/pgtable.h
 157 @@ -119,6 +119,13 @@ extern pgprot_t            pgprot_s2_device;
 158  #define pgprot_noncached(prot) \
 159         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
 160
 161 +#define pgprot_cached(prot) \
 162 +       __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
 163 +
 164 +#define pgprot_cached_ns(prot) \
 165 +       __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
 166 +                       L_PTE_MT_DEV_NONSHARED)
 167 +
 168  #define pgprot_writecombine(prot) \
 169         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
 170
 171 --- a/arch/arm/kernel/time.c
 172 +++ b/arch/arm/kernel/time.c
 173 @@ -12,6 +12,7 @@
 174   *  reading the RTC at bootup, etc...
 175   */
 176  #include <linux/clk-provider.h>
 177 +#include <linux/clockchips.h>
 178  #include <linux/clocksource.h>
 179  #include <linux/errno.h>
 180  #include <linux/export.h>
 181 @@ -121,5 +122,7 @@ void __init time_init(void)
 182                 of_clk_init(NULL);
 183  #endif
 184                 timer_probe();
 185 +
 186 +               tick_setup_hrtimer_broadcast();
 187         }
 188  }
 189 --- a/arch/arm/mm/dma-mapping.c
 190 +++ b/arch/arm/mm/dma-mapping.c
 191 @@ -2416,6 +2416,7 @@ void arch_setup_dma_ops(struct device *d
 192  #endif
 193         dev->archdata.dma_ops_setup = true;
 194  }
 195 +EXPORT_SYMBOL(arch_setup_dma_ops);
 196
 197  void arch_teardown_dma_ops(struct device *dev)
 198  {
 199 --- a/arch/arm/mm/ioremap.c
 200 +++ b/arch/arm/mm/ioremap.c
 201 @@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t
 202  }
 203  EXPORT_SYMBOL(ioremap_wc);
 204
 205 +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
 206 +{
 207 +       return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
 208 +                                  __builtin_return_address(0));
 209 +}
 210 +EXPORT_SYMBOL(ioremap_cache_ns);
 211 +
 212  /*
 213   * Remap an arbitrary physical address space into the kernel virtual
 214   * address space as memory. Needed when the kernel wants to execute
 215 --- a/arch/arm/mm/mmu.c
 216 +++ b/arch/arm/mm/mmu.c
 217 @@ -315,6 +315,13 @@ static struct mem_type mem_types[] __ro_
 218                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 219                 .domain    = DOMAIN_KERNEL,
 220         },
 221 +       [MT_MEMORY_RW_NS] = {
 222 +               .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 223 +                            L_PTE_XN,
 224 +               .prot_l1   = PMD_TYPE_TABLE,
 225 +               .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
 226 +               .domain    = DOMAIN_KERNEL,
 227 +       },
 228         [MT_ROM] = {
 229                 .prot_sect = PMD_TYPE_SECT,
 230                 .domain    = DOMAIN_KERNEL,
 231 @@ -651,6 +658,7 @@ static void __init build_mem_type_table(
 232         }
 233         kern_pgprot |= PTE_EXT_AF;
 234         vecs_pgprot |= PTE_EXT_AF;
 235 +       mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
 236
 237         /*
 238          * Set PXN for user mappings
 239 @@ -679,6 +687,7 @@ static void __init build_mem_type_table(
 240         mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
 241         mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
 242         mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
 243 +       mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
 244         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 245         mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
 246         mem_types[MT_ROM].prot_sect |= cp->pmd;
 247 --- a/arch/arm64/include/asm/cache.h
 248 +++ b/arch/arm64/include/asm/cache.h
 249 @@ -34,7 +34,7 @@
 250  #define ICACHE_POLICY_VIPT     2
 251  #define ICACHE_POLICY_PIPT     3
 252
 253 -#define L1_CACHE_SHIFT         7
 254 +#define L1_CACHE_SHIFT         6
 255  #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 256
 257  /*
 258 --- a/arch/arm64/include/asm/io.h
 259 +++ b/arch/arm64/include/asm/io.h
 260 @@ -186,6 +186,7 @@ extern void __iomem *ioremap_cache(phys_
 261  #define ioremap_nocache(addr, size)    __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 262  #define ioremap_wc(addr, size)         __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 263  #define ioremap_wt(addr, size)         __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 264 +#define ioremap_cache_ns(addr, size)   __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
 265  #define iounmap                                __iounmap
 266
 267  /*
 268 --- a/arch/arm64/include/asm/pgtable-prot.h
 269 +++ b/arch/arm64/include/asm/pgtable-prot.h
 270 @@ -48,6 +48,8 @@
 271  #define PROT_NORMAL_NC         (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
 272  #define PROT_NORMAL_WT         (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
 273  #define PROT_NORMAL            (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
 274 +#define PROT_NORMAL_NS         (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
 275 +
 276
 277  #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
 278  #define PROT_SECT_NORMAL       (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
 279 @@ -68,6 +70,7 @@
 280  #define PAGE_HYP_DEVICE                __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
 281
 282  #define PAGE_S2                        __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
 283 +#define PAGE_S2_NS             __pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
 284  #define PAGE_S2_DEVICE         __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
 285
 286  #define PAGE_NONE              __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
 287 --- a/arch/arm64/include/asm/pgtable.h
 288 +++ b/arch/arm64/include/asm/pgtable.h
 289 @@ -377,6 +377,11 @@ static inline int pmd_protnone(pmd_t pmd
 290         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
 291  #define pgprot_writecombine(prot) \
 292         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 293 +#define pgprot_cached(prot) \
 294 +       __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
 295 +                       PTE_PXN | PTE_UXN)
 296 +#define pgprot_cached_ns(prot) \
 297 +       __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
 298  #define pgprot_device(prot) \
 299         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
 300  #define __HAVE_PHYS_MEM_ACCESS_PROT
 301 --- a/arch/arm64/mm/dma-mapping.c
 302 +++ b/arch/arm64/mm/dma-mapping.c
 303 @@ -947,3 +947,4 @@ void arch_setup_dma_ops(struct device *d
 304         }
 305  #endif
 306  }
 307 +EXPORT_SYMBOL(arch_setup_dma_ops);
 308 --- a/arch/arm64/mm/init.c
 309 +++ b/arch/arm64/mm/init.c
 310 @@ -457,6 +457,14 @@ void __init arm64_memblock_init(void)
 311          * Register the kernel text, kernel data, initrd, and initial
 312          * pagetables with memblock.
 313          */
 314 +
 315 +       /* make this the first reservation so that there are no chances of
 316 +        * overlap
 317 +        */
 318 +       reserve_elfcorehdr();
 319 +
 320 +       reserve_crashkernel();
 321 +
 322         memblock_reserve(__pa_symbol(_text), _end - _text);
 323  #ifdef CONFIG_BLK_DEV_INITRD
 324         if (initrd_start) {
 325 @@ -476,10 +484,6 @@ void __init arm64_memblock_init(void)
 326         else
 327                 arm64_dma_phys_limit = PHYS_MASK + 1;
 328
 329 -       reserve_crashkernel();
 330 -
 331 -       reserve_elfcorehdr();
 332 -
 333         high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
 334
 335         dma_contiguous_reserve(arm64_dma_phys_limit);
 336 --- a/drivers/soc/fsl/guts.c
 337 +++ b/drivers/soc/fsl/guts.c
 338 @@ -100,6 +100,11 @@ static const struct fsl_soc_die_attr fsl
 339           .svr          = 0x87000000,
 340           .mask         = 0xfff70000,
 341         },
 342 +       /* Die: LX2160A, SoC: LX2160A/LX2120A/LX2080A */
 343 +       { .die          = "LX2160A",
 344 +         .svr          = 0x87360000,
 345 +         .mask         = 0xff3f0000,
 346 +       },
 347         { },
 348  };
 349
 350 @@ -213,6 +218,10 @@ static const struct of_device_id fsl_gut
 351         { .compatible = "fsl,ls1021a-dcfg", },
 352         { .compatible = "fsl,ls1043a-dcfg", },
 353         { .compatible = "fsl,ls2080a-dcfg", },
 354 +       { .compatible = "fsl,ls1088a-dcfg", },
 355 +       { .compatible = "fsl,ls1012a-dcfg", },
 356 +       { .compatible = "fsl,ls1046a-dcfg", },
 357 +       { .compatible = "fsl,lx2160a-dcfg", },
 358         {}
 359  };
 360  MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
 361 --- /dev/null
 362 +++ b/drivers/soc/fsl/qixis_ctrl.c
 363 @@ -0,0 +1,105 @@
 364 +// SPDX-License-Identifier: GPL-2.0+
 365 +
 366 +/* Freescale QIXIS system controller driver.
 367 + *
 368 + * Copyright 2015 Freescale Semiconductor, Inc.
 369 + * Copyright 2018-2019 NXP
 370 + */
 371 +
 372 +#include <linux/err.h>
 373 +#include <linux/i2c.h>
 374 +#include <linux/module.h>
 375 +#include <linux/mfd/core.h>
 376 +#include <linux/of.h>
 377 +#include <linux/regmap.h>
 378 +
 379 +/* QIXIS MAP */
 380 +struct fsl_qixis_regs {
 381 +       u8              id;             /* Identification Registers */
 382 +       u8              version;        /* Version Register */
 383 +       u8              qixis_ver;      /* QIXIS Version Register */
 384 +       u8              reserved1[0x1f];
 385 +};
 386 +
 387 +struct qixis_priv {
 388 +       struct regmap           *regmap;
 389 +};
 390 +
 391 +static struct regmap_config qixis_regmap_config = {
 392 +       .reg_bits = 8,
 393 +       .val_bits = 8,
 394 +};
 395 +
 396 +static const struct mfd_cell fsl_qixis_devs[] = {
 397 +       {
 398 +               .name = "reg-mux",
 399 +               .of_compatible = "reg-mux",
 400 +       },
 401 +};
 402 +
 403 +static int fsl_qixis_i2c_probe(struct i2c_client *client)
 404 +{
 405 +       struct qixis_priv *priv;
 406 +       int ret = 0;
 407 +       u32 qver;
 408 +
 409 +       if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 410 +               return -EOPNOTSUPP;
 411 +
 412 +       priv = devm_kzalloc(&client->dev, sizeof(struct qixis_priv),
 413 +                           GFP_KERNEL);
 414 +       if (!priv)
 415 +               return -ENOMEM;
 416 +
 417 +       priv->regmap = regmap_init_i2c(client, &qixis_regmap_config);
 418 +       regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
 419 +                   &qver);
 420 +       pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
 421 +
 422 +       i2c_set_clientdata(client, priv);
 423 +
 424 +       if (of_device_is_compatible(client->dev.of_node, "simple-mfd"))
 425 +               ret = devm_mfd_add_devices(&client->dev, -1, fsl_qixis_devs,
 426 +                                          ARRAY_SIZE(fsl_qixis_devs), NULL, 0,
 427 +                                          NULL);
 428 +       if (ret)
 429 +               goto error;
 430 +
 431 +       return ret;
 432 +error:
 433 +       regmap_exit(priv->regmap);
 434 +
 435 +       return ret;
 436 +}
 437 +
 438 +static int fsl_qixis_i2c_remove(struct i2c_client *client)
 439 +{
 440 +       struct qixis_priv *priv;
 441 +
 442 +       priv = i2c_get_clientdata(client);
 443 +       regmap_exit(priv->regmap);
 444 +
 445 +       return 0;
 446 +}
 447 +
 448 +static const struct of_device_id fsl_qixis_i2c_of_match[] = {
 449 +       { .compatible = "fsl,fpga-qixis-i2c" },
 450 +       {}
 451 +};
 452 +MODULE_DEVICE_TABLE(of, fsl_qixis_i2c_of_match);
 453 +
 454 +static struct i2c_driver fsl_qixis_i2c_driver = {
 455 +       .driver = {
 456 +               .name   = "qixis_ctrl_i2c",
 457 +               .owner  = THIS_MODULE,
 458 +               .of_match_table = of_match_ptr(fsl_qixis_i2c_of_match),
 459 +       },
 460 +       .probe_new      = fsl_qixis_i2c_probe,
 461 +       .remove         = fsl_qixis_i2c_remove,
 462 +};
 463 +module_i2c_driver(fsl_qixis_i2c_driver);
 464 +
 465 +MODULE_AUTHOR("Wang Dongsheng <dongsheng.wang@freescale.com>");
 466 +MODULE_DESCRIPTION("Freescale QIXIS system controller driver");
 467 +MODULE_LICENSE("GPL");
 468 +