target/linux/lantiq/patches-4.4/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch

   1 From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 10 Sep 2014 22:42:14 +0200
   4 Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h  |   6 +
   9  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   3 +
  10  arch/mips/lantiq/xway/Makefile                     |   3 +
  11  arch/mips/lantiq/xway/ath_eep.c                    | 299 +++++++++++++++++++++
  12  arch/mips/lantiq/xway/eth_mac.c                    |  25 ++
  13  arch/mips/lantiq/xway/pci-ath-fixup.c              | 118 ++++++++
  14  drivers/net/ethernet/lantiq_etop.c                 |   6 +-
  15  7 files changed, 459 insertions(+), 1 deletion(-)
  16  create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
  17  create mode 100644 arch/mips/lantiq/xway/ath_eep.c
  18  create mode 100644 arch/mips/lantiq/xway/eth_mac.c
  19  create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c
  20
  21 --- /dev/null
  22 +++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
  23 @@ -0,0 +1,6 @@
  24 +#ifndef _PCI_ATH_FIXUP
  25 +#define _PCI_ATH_FIXUP
  26 +
  27 +void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init;
  28 +
  29 +#endif /* _PCI_ATH_FIXUP */
  30 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  31 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  32 @@ -104,5 +104,8 @@ int xrx200_gphy_boot(struct device *dev,
  33  extern void ltq_pmu_enable(unsigned int module);
  34  extern void ltq_pmu_disable(unsigned int module);
  35
  36 +/* allow the ethernet driver to load a flash mapped mac addr */
  37 +const u8* ltq_get_eth_mac(void);
  38 +
  39  #endif /* CONFIG_SOC_TYPE_XWAY */
  40  #endif /* _LTQ_XWAY_H__ */
  41 --- a/arch/mips/lantiq/xway/Makefile
  42 +++ b/arch/mips/lantiq/xway/Makefile
  43 @@ -2,4 +2,7 @@ obj-y := prom.o sysctrl.o clk.o reset.o
  44
  45  obj-y += vmmc.o tffs.o
  46
  47 +obj-y += eth_mac.o
  48 +obj-$(CONFIG_PCI) += ath_eep.o pci-ath-fixup.o
  49 +
  50  obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
  51 --- /dev/null
  52 +++ b/arch/mips/lantiq/xway/ath_eep.c
  53 @@ -0,0 +1,299 @@
  54 +/*
  55 + *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
  56 + *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  57 + *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
  58 + *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
  59 + *  Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
  60 + *  Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
  61 + *
  62 + *  This program is free software; you can redistribute it and/or modify it
  63 + *  under the terms of the GNU General Public License version 2 as published
  64 + *  by the Free Software Foundation.
  65 + */
  66 +
  67 +#include <linux/init.h>
  68 +#include <linux/module.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/etherdevice.h>
  71 +#include <linux/ath5k_platform.h>
  72 +#include <linux/ath9k_platform.h>
  73 +#include <linux/pci.h>
  74 +#include <linux/err.h>
  75 +#include <linux/mtd/mtd.h>
  76 +#include <pci-ath-fixup.h>
  77 +#include <lantiq_soc.h>
  78 +
  79 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
  80 +struct ath5k_platform_data ath5k_pdata;
  81 +struct ath9k_platform_data ath9k_pdata = {
  82 +       .led_pin = -1,
  83 +};
  84 +static u8 athxk_eeprom_mac[6];
  85 +
  86 +static int ath9k_pci_plat_dev_init(struct pci_dev *dev)
  87 +{
  88 +       dev->dev.platform_data = &ath9k_pdata;
  89 +       return 0;
  90 +}
  91 +
  92 +static int ath9k_eep_load;
  93 +int __init of_ath9k_eeprom_probe(struct platform_device *pdev)
  94 +{
  95 +       struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
  96 +       int mac_offset, led_pin;
  97 +       u32 mac_inc = 0, pci_slot = 0;
  98 +       int i;
  99 +       struct mtd_info *the_mtd;
 100 +       size_t flash_readlen;
 101 +       const __be32 *list;
 102 +       const char *part;
 103 +       phandle phandle;
 104 +       u16 dev_ids[2] = { 0 };
 105 +
 106 +       list = of_get_property(np, "ath,eep-flash", &i);
 107 +       if (!list || (i != (2 * sizeof(*list))))
 108 +               return -ENODEV;
 109 +
 110 +       phandle = be32_to_cpup(list++);
 111 +       if (phandle)
 112 +               mtd_np = of_find_node_by_phandle(phandle);
 113 +
 114 +       if (!mtd_np)
 115 +               return -ENODEV;
 116 +
 117 +       part = of_get_property(mtd_np, "label", NULL);
 118 +       if (!part)
 119 +               part = mtd_np->name;
 120 +
 121 +       the_mtd = get_mtd_device_nm(part);
 122 +       if (IS_ERR(the_mtd))
 123 +               return -ENODEV;
 124 +
 125 +       i = mtd_read(the_mtd, be32_to_cpup(list), ATH9K_PLAT_EEP_MAX_WORDS << 1,
 126 +               &flash_readlen, (void *) ath9k_pdata.eeprom_data);
 127 +
 128 +       if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
 129 +               size_t mac_readlen;
 130 +               mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
 131 +                       (void *) athxk_eeprom_mac);
 132 +       }
 133 +       put_mtd_device(the_mtd);
 134 +
 135 +       if ((sizeof(ath9k_pdata.eeprom_data) != flash_readlen) || i) {
 136 +               dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
 137 +               return -ENODEV;
 138 +       }
 139 +
 140 +       if (of_find_property(np, "ath,eep-swap", NULL))
 141 +               for (i = 0; i < ATH9K_PLAT_EEP_MAX_WORDS; i++)
 142 +                       ath9k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]);
 143 +
 144 +       if (of_find_property(np, "ath,eep-endian", NULL)) {
 145 +               ath9k_pdata.endian_check = true;
 146 +
 147 +               dev_info(&pdev->dev, "endian check enabled.\n");
 148 +       }
 149 +
 150 +       if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
 151 +               memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6);
 152 +
 153 +       if (!is_valid_ether_addr(athxk_eeprom_mac)) {
 154 +               dev_warn(&pdev->dev, "using random mac\n");
 155 +               random_ether_addr(athxk_eeprom_mac);
 156 +       }
 157 +
 158 +       if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
 159 +               athxk_eeprom_mac[5] += mac_inc;
 160 +
 161 +       ath9k_pdata.macaddr = athxk_eeprom_mac;
 162 +       ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init;
 163 +
 164 +       if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) {
 165 +               ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data);
 166 +
 167 +               dev_info(&pdev->dev, "pci slot: %u\n", pci_slot);
 168 +                if (ath9k_eep_load) {
 169 +                        struct pci_dev *d = NULL;
 170 +                        while ((d = pci_get_device(PCI_VENDOR_ID_ATHEROS,
 171 +                                        PCI_ANY_ID, d)) != NULL)
 172 +                                pci_fixup_device(pci_fixup_early, d);
 173 +                }
 174 +
 175 +       }
 176 +
 177 +       if (!of_property_read_u16_array(np, "ath,device-id", dev_ids, 2)) {
 178 +               struct pci_dev *d = NULL;
 179 +
 180 +               while ((d = pci_get_device(PCI_VENDOR_ID_ATHEROS,
 181 +                                          dev_ids[0], d)) != NULL)
 182 +                       d->device = dev_ids[1];
 183 +       }
 184 +
 185 +       if (!of_property_read_u32(np, "ath,led-pin", &led_pin)) {
 186 +               ath9k_pdata.led_pin = led_pin;
 187 +               dev_info(&pdev->dev, "using led pin %d.\n", led_pin);
 188 +       }
 189 +
 190 +       if (of_property_read_bool(np, "ath,led-active-high")) {
 191 +               ath9k_pdata.led_active_high = true;
 192 +               dev_info(&pdev->dev, "inverted LED polarity\n");
 193 +       }
 194 +
 195 +       if (of_property_read_bool(np, "ath,disable-2ghz")) {
 196 +               ath9k_pdata.disable_2ghz = true;
 197 +               dev_info(&pdev->dev, "disabled 2.4 GHz band\n");
 198 +       }
 199 +
 200 +       if (of_property_read_bool(np, "ath,disable-5ghz")) {
 201 +               ath9k_pdata.disable_5ghz = true;
 202 +               dev_info(&pdev->dev, "disabled 5 GHz band\n");
 203 +       }
 204 +
 205 +       dev_info(&pdev->dev, "loaded ath9k eeprom\n");
 206 +
 207 +       return 0;
 208 +}
 209 +
 210 +static struct of_device_id ath9k_eeprom_ids[] = {
 211 +       { .compatible = "ath9k,eeprom" },
 212 +       { }
 213 +};
 214 +
 215 +static struct platform_driver ath9k_eeprom_driver = {
 216 +       .driver         = {
 217 +               .name           = "ath9k,eeprom",
 218 +               .owner  = THIS_MODULE,
 219 +               .of_match_table = of_match_ptr(ath9k_eeprom_ids),
 220 +       },
 221 +};
 222 +
 223 +static int __init of_ath9k_eeprom_init(void)
 224 +{
 225 +        int ret = platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
 226 +
 227 +        if (ret)
 228 +                ath9k_eep_load = 1;
 229 +
 230 +        return ret;
 231 +}
 232 +
 233 +static int __init of_ath9k_eeprom_init_late(void)
 234 +{
 235 +        if (!ath9k_eep_load)
 236 +                return 0;
 237 +        return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
 238 +}
 239 +late_initcall(of_ath9k_eeprom_init_late);
 240 +subsys_initcall(of_ath9k_eeprom_init);
 241 +
 242 +
 243 +static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
 244 +{
 245 +       dev->dev.platform_data = &ath5k_pdata;
 246 +       return 0;
 247 +}
 248 +
 249 +static int ath5k_eep_load;
 250 +int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
 251 +{
 252 +       struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
 253 +       int mac_offset;
 254 +       u32 mac_inc = 0;
 255 +       int i;
 256 +       struct mtd_info *the_mtd;
 257 +       size_t flash_readlen;
 258 +       const __be32 *list;
 259 +       const char *part;
 260 +       phandle phandle;
 261 +
 262 +       list = of_get_property(np, "ath,eep-flash", &i);
 263 +       if (!list || (i != (2 * sizeof(*list))))
 264 +               return -ENODEV;
 265 +
 266 +       phandle = be32_to_cpup(list++);
 267 +       if (phandle)
 268 +               mtd_np = of_find_node_by_phandle(phandle);
 269 +
 270 +       if (!mtd_np)
 271 +               return -ENODEV;
 272 +
 273 +       part = of_get_property(mtd_np, "label", NULL);
 274 +       if (!part)
 275 +               part = mtd_np->name;
 276 +
 277 +       the_mtd = get_mtd_device_nm(part);
 278 +       if (IS_ERR(the_mtd))
 279 +               return -ENODEV;
 280 +
 281 +       ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
 282 +
 283 +       i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
 284 +               &flash_readlen, (void *) ath5k_pdata.eeprom_data);
 285 +
 286 +       if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
 287 +               size_t mac_readlen;
 288 +               mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
 289 +                       (void *) athxk_eeprom_mac);
 290 +       }
 291 +       put_mtd_device(the_mtd);
 292 +
 293 +       if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
 294 +               dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
 295 +               return -ENODEV;
 296 +       }
 297 +
 298 +       if (of_find_property(np, "ath,eep-swap", NULL))
 299 +               for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
 300 +                       ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
 301 +
 302 +       if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
 303 +               ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
 304 +
 305 +       if (!is_valid_ether_addr(athxk_eeprom_mac)) {
 306 +               dev_warn(&pdev->dev, "using random mac\n");
 307 +               random_ether_addr(athxk_eeprom_mac);
 308 +       }
 309 +
 310 +       if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
 311 +               athxk_eeprom_mac[5] += mac_inc;
 312 +
 313 +       ath5k_pdata.macaddr = athxk_eeprom_mac;
 314 +       ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
 315 +
 316 +       dev_info(&pdev->dev, "loaded ath5k eeprom\n");
 317 +
 318 +       return 0;
 319 +}
 320 +
 321 +static struct of_device_id ath5k_eeprom_ids[] = {
 322 +       { .compatible = "ath5k,eeprom" },
 323 +       { }
 324 +};
 325 +
 326 +static struct platform_driver ath5k_eeprom_driver = {
 327 +       .driver         = {
 328 +               .name           = "ath5k,eeprom",
 329 +               .owner  = THIS_MODULE,
 330 +               .of_match_table = of_match_ptr(ath5k_eeprom_ids),
 331 +       },
 332 +};
 333 +
 334 +static int __init of_ath5k_eeprom_init(void)
 335 +{
 336 +       int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
 337 +
 338 +       if (ret)
 339 +               ath5k_eep_load = 1;
 340 +
 341 +       return ret;
 342 +}
 343 +
 344 +static int __init of_ath5k_eeprom_init_late(void)
 345 +{
 346 +       if (!ath5k_eep_load)
 347 +               return 0;
 348 +
 349 +       return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
 350 +}
 351 +late_initcall(of_ath5k_eeprom_init_late);
 352 +subsys_initcall(of_ath5k_eeprom_init);
 353 --- /dev/null
 354 +++ b/arch/mips/lantiq/xway/eth_mac.c
 355 @@ -0,0 +1,25 @@
 356 +/*
 357 + *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
 358 + *
 359 + *  This program is free software; you can redistribute it and/or modify it
 360 + *  under the terms of the GNU General Public License version 2 as published
 361 + *  by the Free Software Foundation.
 362 + */
 363 +
 364 +#include <linux/init.h>
 365 +#include <linux/if_ether.h>
 366 +
 367 +static u8 eth_mac[6];
 368 +static int eth_mac_set;
 369 +
 370 +const u8* ltq_get_eth_mac(void)
 371 +{
 372 +       return eth_mac;
 373 +}
 374 +
 375 +static int __init setup_ethaddr(char *str)
 376 +{
 377 +       eth_mac_set = mac_pton(str, eth_mac);
 378 +       return !eth_mac_set;
 379 +}
 380 +early_param("ethaddr", setup_ethaddr);
 381 --- /dev/null
 382 +++ b/arch/mips/lantiq/xway/pci-ath-fixup.c
 383 @@ -0,0 +1,118 @@
 384 +/*
 385 + *  Atheros AP94 reference board PCI initialization
 386 + *
 387 + *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
 388 + *
 389 + *  This program is free software; you can redistribute it and/or modify it
 390 + *  under the terms of the GNU General Public License version 2 as published
 391 + *  by the Free Software Foundation.
 392 + */
 393 +
 394 +#include <linux/pci.h>
 395 +#include <linux/init.h>
 396 +#include <linux/delay.h>
 397 +#include <lantiq_soc.h>
 398 +
 399 +struct ath_fixup {
 400 +       u16             *cal_data;
 401 +       unsigned        slot;
 402 +};
 403 +
 404 +static int ath_num_fixups;
 405 +static struct ath_fixup ath_fixups[2];
 406 +
 407 +static void ath_pci_fixup(struct pci_dev *dev)
 408 +{
 409 +       void __iomem *mem;
 410 +       struct pci_dev *bridge = pci_upstream_bridge(dev);
 411 +       u16 *cal_data = NULL;
 412 +       u16 cmd;
 413 +       u32 bar0;
 414 +       u32 val;
 415 +       u32 base;
 416 +       unsigned i;
 417 +
 418 +       for (i = 0; i < ath_num_fixups; i++) {
 419 +               if (ath_fixups[i].cal_data == NULL)
 420 +                       continue;
 421 +
 422 +               if (ath_fixups[i].slot != PCI_SLOT(dev->devfn))
 423 +                       continue;
 424 +
 425 +               cal_data = ath_fixups[i].cal_data;
 426 +               break;
 427 +       }
 428 +
 429 +       if (cal_data == NULL)
 430 +               return;
 431 +
 432 +       if (*cal_data != 0xa55a) {
 433 +               pr_err("pci %s: invalid calibration data\n", pci_name(dev));
 434 +               return;
 435 +       }
 436 +
 437 +       pr_info("pci %s: fixup device configuration\n", pci_name(dev));
 438 +
 439 +       base = dev->resource[0].start;
 440 +       mem = ioremap(base, 0x10000);
 441 +       if (!mem) {
 442 +               pr_err("pci %s: ioremap error\n", pci_name(dev));
 443 +               return;
 444 +       }
 445 +
 446 +       if (bridge) {
 447 +               pci_enable_device(dev);
 448 +       }
 449 +
 450 +       pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 451 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
 452 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 453 +       cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 454 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 455 +
 456 +       /* set pointer to first reg address */
 457 +       cal_data += 3;
 458 +       while (*cal_data != 0xffff) {
 459 +               u32 reg;
 460 +               reg = *cal_data++;
 461 +               val = *cal_data++;
 462 +               val |= (*cal_data++) << 16;
 463 +
 464 +               ltq_w32(swab32(val), mem + reg);
 465 +               udelay(100);
 466 +       }
 467 +
 468 +       pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
 469 +       dev->vendor = val & 0xffff;
 470 +       dev->device = (val >> 16) & 0xffff;
 471 +
 472 +       pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
 473 +       dev->revision = val & 0xff;
 474 +       dev->class = val >> 8; /* upper 3 bytes */
 475 +
 476 +       pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n",
 477 +               pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class);
 478 +
 479 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 480 +       cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 481 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 482 +
 483 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
 484 +
 485 +       if (bridge) {
 486 +               pci_disable_device(dev);
 487 +       }
 488 +
 489 +       iounmap(mem);
 490 +}
 491 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);
 492 +
 493 +void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data)
 494 +{
 495 +       if (ath_num_fixups >= ARRAY_SIZE(ath_fixups))
 496 +               return;
 497 +
 498 +       ath_fixups[ath_num_fixups].slot = slot;
 499 +       ath_fixups[ath_num_fixups].cal_data = cal_data;
 500 +       ath_num_fixups++;
 501 +}
 502 --- a/drivers/net/ethernet/lantiq_etop.c
 503 +++ b/drivers/net/ethernet/lantiq_etop.c
 504 @@ -840,7 +840,11 @@ ltq_etop_init(struct net_device *dev)
 505         if (err)
 506                 goto err_hw;
 507
 508 -       memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 509 +       memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
 510 +
 511 +       if (priv->mac && !is_valid_ether_addr(mac.sa_data))
 512 +               memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
 513 +
 514         if (!is_valid_ether_addr(mac.sa_data)) {
 515                 pr_warn("etop: invalid MAC, using random\n");
 516                 eth_random_addr(mac.sa_data);