target/linux/lantiq/patches-4.4/0028-NET-lantiq-various-etop-fixes.patch

   1 From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 9 Sep 2014 22:45:34 +0200
   4 Subject: [PATCH 28/36] NET: lantiq: various etop fixes
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
   9  1 file changed, 389 insertions(+), 166 deletions(-)
  10
  11 --- a/drivers/net/ethernet/lantiq_etop.c
  12 +++ b/drivers/net/ethernet/lantiq_etop.c
  13 @@ -11,7 +11,7 @@
  14   *   You should have received a copy of the GNU General Public License
  15   *   along with this program; if not, see <http://www.gnu.org/licenses/>.
  16   *
  17 - *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  18 + *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
  19   */
  20
  21  #include <linux/kernel.h>
  22 @@ -30,11 +30,16 @@
  23  #include <linux/mm.h>
  24  #include <linux/platform_device.h>
  25  #include <linux/ethtool.h>
  26 +#include <linux/if_vlan.h>
  27  #include <linux/init.h>
  28  #include <linux/delay.h>
  29  #include <linux/io.h>
  30  #include <linux/dma-mapping.h>
  31  #include <linux/module.h>
  32 +#include <linux/clk.h>
  33 +#include <linux/of_net.h>
  34 +#include <linux/of_irq.h>
  35 +#include <linux/of_platform.h>
  36
  37  #include <asm/checksum.h>
  38
  39 @@ -42,7 +47,7 @@
  40  #include <xway_dma.h>
  41  #include <lantiq_platform.h>
  42
  43 -#define LTQ_ETOP_MDIO          0x11804
  44 +#define LTQ_ETOP_MDIO_ACC      0x11804
  45  #define MDIO_REQUEST           0x80000000
  46  #define MDIO_READ              0x40000000
  47  #define MDIO_ADDR_MASK         0x1f
  48 @@ -51,44 +56,91 @@
  49  #define MDIO_REG_OFFSET                0x10
  50  #define MDIO_VAL_MASK          0xffff
  51
  52 -#define PPE32_CGEN             0x800
  53 -#define LQ_PPE32_ENET_MAC_CFG  0x1840
  54 +#define LTQ_ETOP_MDIO_CFG       0x11800
  55 +#define MDIO_CFG_MASK           0x6
  56 +
  57 +#define LTQ_ETOP_CFG            0x11808
  58 +#define LTQ_ETOP_IGPLEN         0x11820
  59 +#define LTQ_ETOP_MAC_CFG       0x11840
  60
  61  #define LTQ_ETOP_ENETS0                0x11850
  62  #define LTQ_ETOP_MAC_DA0       0x1186C
  63  #define LTQ_ETOP_MAC_DA1       0x11870
  64 -#define LTQ_ETOP_CFG           0x16020
  65 -#define LTQ_ETOP_IGPLEN                0x16080
  66 +
  67 +#define MAC_CFG_MASK           0xfff
  68 +#define MAC_CFG_CGEN           (1 << 11)
  69 +#define MAC_CFG_DUPLEX         (1 << 2)
  70 +#define MAC_CFG_SPEED          (1 << 1)
  71 +#define MAC_CFG_LINK           (1 << 0)
  72
  73  #define MAX_DMA_CHAN           0x8
  74  #define MAX_DMA_CRC_LEN                0x4
  75  #define MAX_DMA_DATA_LEN       0x600
  76
  77  #define ETOP_FTCU              BIT(28)
  78 -#define ETOP_MII_MASK          0xf
  79 -#define ETOP_MII_NORMAL                0xd
  80 -#define ETOP_MII_REVERSE       0xe
  81  #define ETOP_PLEN_UNDER                0x40
  82 -#define ETOP_CGEN              0x800
  83 +#define ETOP_CFG_MII0          0x01
  84
  85 -/* use 2 static channels for TX/RX */
  86 -#define LTQ_ETOP_TX_CHANNEL    1
  87 -#define LTQ_ETOP_RX_CHANNEL    6
  88 -#define IS_TX(x)               (x == LTQ_ETOP_TX_CHANNEL)
  89 -#define IS_RX(x)               (x == LTQ_ETOP_RX_CHANNEL)
  90 +#define ETOP_CFG_MASK           0xfff
  91 +#define ETOP_CFG_FEN0          (1 << 8)
  92 +#define ETOP_CFG_SEN0          (1 << 6)
  93 +#define ETOP_CFG_OFF1          (1 << 3)
  94 +#define ETOP_CFG_REMII0                (1 << 1)
  95 +#define ETOP_CFG_OFF0          (1 << 0)
  96 +
  97 +#define LTQ_GBIT_MDIO_CTL      0xCC
  98 +#define LTQ_GBIT_MDIO_DATA     0xd0
  99 +#define LTQ_GBIT_GCTL0         0x68
 100 +#define LTQ_GBIT_PMAC_HD_CTL   0x8c
 101 +#define LTQ_GBIT_P0_CTL                0x4
 102 +#define LTQ_GBIT_PMAC_RX_IPG   0xa8
 103 +#define LTQ_GBIT_RGMII_CTL     0x78
 104 +
 105 +#define PMAC_HD_CTL_AS         (1 << 19)
 106 +#define PMAC_HD_CTL_RXSH       (1 << 22)
 107
 108 +/* Switch Enable (0=disable, 1=enable) */
 109 +#define GCTL0_SE               0x80000000
 110 +/* Disable MDIO auto polling (0=disable, 1=enable) */
 111 +#define PX_CTL_DMDIO           0x00400000
 112 +
 113 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
 114 +#define MDC_CLOCK_MASK         0xff000000
 115 +#define MDC_CLOCK_OFFSET       24
 116 +
 117 +/* register information for the gbit's MDIO bus */
 118 +#define MDIO_XR9_REQUEST       0x00008000
 119 +#define MDIO_XR9_READ          0x00000800
 120 +#define MDIO_XR9_WRITE         0x00000400
 121 +#define MDIO_XR9_REG_MASK      0x1f
 122 +#define MDIO_XR9_ADDR_MASK     0x1f
 123 +#define MDIO_XR9_RD_MASK       0xffff
 124 +#define MDIO_XR9_REG_OFFSET    0
 125 +#define MDIO_XR9_ADDR_OFFSET   5
 126 +#define MDIO_XR9_WR_OFFSET     16
 127 +
 128 +#define LTQ_DMA_ETOP   ((of_machine_is_compatible("lantiq,ase")) ? \
 129 +                       (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
 130 +
 131 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
 132  #define ltq_etop_r32(x)                ltq_r32(ltq_etop_membase + (x))
 133  #define ltq_etop_w32(x, y)     ltq_w32(x, ltq_etop_membase + (y))
 134  #define ltq_etop_w32_mask(x, y, z)     \
 135                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
 136
 137 -#define DRV_VERSION    "1.0"
 138 +#define ltq_gbit_r32(x)                ltq_r32(ltq_gbit_membase + (x))
 139 +#define ltq_gbit_w32(x, y)     ltq_w32(x, ltq_gbit_membase + (y))
 140 +#define ltq_gbit_w32_mask(x, y, z)     \
 141 +               ltq_w32_mask(x, y, ltq_gbit_membase + (z))
 142 +
 143 +#define DRV_VERSION    "1.2"
 144
 145  static void __iomem *ltq_etop_membase;
 146 +static void __iomem *ltq_gbit_membase;
 147
 148  struct ltq_etop_chan {
 149 -       int idx;
 150         int tx_free;
 151 +       int irq;
 152         struct net_device *netdev;
 153         struct napi_struct napi;
 154         struct ltq_dma_channel dma;
 155 @@ -98,22 +150,35 @@ struct ltq_etop_chan {
 156  struct ltq_etop_priv {
 157         struct net_device *netdev;
 158         struct platform_device *pdev;
 159 -       struct ltq_eth_data *pldata;
 160         struct resource *res;
 161
 162         struct mii_bus *mii_bus;
 163         struct phy_device *phydev;
 164
 165 -       struct ltq_etop_chan ch[MAX_DMA_CHAN];
 166 -       int tx_free[MAX_DMA_CHAN >> 1];
 167 +       struct ltq_etop_chan txch;
 168 +       struct ltq_etop_chan rxch;
 169 +
 170 +       int tx_irq;
 171 +       int rx_irq;
 172 +
 173 +       unsigned char mac[6];
 174 +       int mii_mode;
 175
 176         spinlock_t lock;
 177 +
 178 +       struct clk *clk_ppe;
 179 +       struct clk *clk_switch;
 180 +       struct clk *clk_ephy;
 181 +       struct clk *clk_ephycgu;
 182  };
 183
 184 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
 185 +                               int phy_reg, u16 phy_data);
 186 +
 187  static int
 188  ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 189  {
 190 -       ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 191 +       ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
 192         if (!ch->skb[ch->dma.desc])
 193                 return -ENOMEM;
 194         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
 195 @@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
 196         spin_unlock_irqrestore(&priv->lock, flags);
 197
 198         skb_put(skb, len);
 199 +       skb->dev = ch->netdev;
 200         skb->protocol = eth_type_trans(skb, ch->netdev);
 201         netif_receive_skb(skb);
 202 +       ch->netdev->stats.rx_packets++;
 203 +       ch->netdev->stats.rx_bytes += len;
 204  }
 205
 206  static int
 207 @@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
 208  {
 209         struct ltq_etop_chan *ch = container_of(napi,
 210                                 struct ltq_etop_chan, napi);
 211 +       struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 212         int rx = 0;
 213         int complete = 0;
 214 +       unsigned long flags;
 215
 216         while ((rx < budget) && !complete) {
 217                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 218 @@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
 219         }
 220         if (complete || !rx) {
 221                 napi_complete(&ch->napi);
 222 +               spin_lock_irqsave(&priv->lock, flags);
 223                 ltq_dma_ack_irq(&ch->dma);
 224 +               spin_unlock_irqrestore(&priv->lock, flags);
 225         }
 226         return rx;
 227  }
 228 @@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
 229                 container_of(napi, struct ltq_etop_chan, napi);
 230         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 231         struct netdev_queue *txq =
 232 -               netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 233 +               netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
 234         unsigned long flags;
 235
 236         spin_lock_irqsave(&priv->lock, flags);
 237         while ((ch->dma.desc_base[ch->tx_free].ctl &
 238                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 239 +               ch->netdev->stats.tx_packets++;
 240 +               ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
 241                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 242                 ch->skb[ch->tx_free] = NULL;
 243                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 244 @@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
 245         if (netif_tx_queue_stopped(txq))
 246                 netif_tx_start_queue(txq);
 247         napi_complete(&ch->napi);
 248 +       spin_lock_irqsave(&priv->lock, flags);
 249         ltq_dma_ack_irq(&ch->dma);
 250 +       spin_unlock_irqrestore(&priv->lock, flags);
 251         return 1;
 252  }
 253
 254 @@ -210,9 +286,10 @@ static irqreturn_t
 255  ltq_etop_dma_irq(int irq, void *_priv)
 256  {
 257         struct ltq_etop_priv *priv = _priv;
 258 -       int ch = irq - LTQ_DMA_CH0_INT;
 259 -
 260 -       napi_schedule(&priv->ch[ch].napi);
 261 +       if (irq == priv->txch.dma.irq)
 262 +               napi_schedule(&priv->txch.napi);
 263 +       else
 264 +               napi_schedule(&priv->rxch.napi);
 265         return IRQ_HANDLED;
 266  }
 267
 268 @@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device
 269         ltq_dma_free(&ch->dma);
 270         if (ch->dma.irq)
 271                 free_irq(ch->dma.irq, priv);
 272 -       if (IS_RX(ch->idx)) {
 273 +       if (ch == &priv->txch) {
 274                 int desc;
 275                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 276                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 277 @@ -235,65 +312,133 @@ static void
 278  ltq_etop_hw_exit(struct net_device *dev)
 279  {
 280         struct ltq_etop_priv *priv = netdev_priv(dev);
 281 -       int i;
 282
 283 -       ltq_pmu_disable(PMU_PPE);
 284 -       for (i = 0; i < MAX_DMA_CHAN; i++)
 285 -               if (IS_TX(i) || IS_RX(i))
 286 -                       ltq_etop_free_channel(dev, &priv->ch[i]);
 287 +       clk_disable(priv->clk_ppe);
 288 +
 289 +       if (of_machine_is_compatible("lantiq,ar9"))
 290 +               clk_disable(priv->clk_switch);
 291 +
 292 +       if (of_machine_is_compatible("lantiq,ase")) {
 293 +               clk_disable(priv->clk_ephy);
 294 +               clk_disable(priv->clk_ephycgu);
 295 +       }
 296 +
 297 +       ltq_etop_free_channel(dev, &priv->txch);
 298 +       ltq_etop_free_channel(dev, &priv->rxch);
 299 +}
 300 +
 301 +static void
 302 +ltq_etop_gbit_init(struct net_device *dev)
 303 +{
 304 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 305 +
 306 +       clk_enable(priv->clk_switch);
 307 +
 308 +       /* enable gbit port0 on the SoC */
 309 +       ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
 310 +
 311 +       ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 312 +       /* disable MDIO auto polling mode */
 313 +       ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
 314 +       /* set 1522 packet size */
 315 +       ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
 316 +       /* disable pmac & dmac headers */
 317 +       ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
 318 +               LTQ_GBIT_PMAC_HD_CTL);
 319 +       /* Due to traffic halt when burst length 8,
 320 +               replace default IPG value with 0x3B */
 321 +       ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
 322 +       /* set mdc clock to 2.5 MHz */
 323 +       ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
 324 +               LTQ_GBIT_RGMII_CTL);
 325  }
 326
 327  static int
 328  ltq_etop_hw_init(struct net_device *dev)
 329  {
 330         struct ltq_etop_priv *priv = netdev_priv(dev);
 331 -       int i;
 332 +       int mii_mode = priv->mii_mode;
 333
 334 -       ltq_pmu_enable(PMU_PPE);
 335 +       clk_enable(priv->clk_ppe);
 336
 337 -       switch (priv->pldata->mii_mode) {
 338 +       if (of_machine_is_compatible("lantiq,ar9")) {
 339 +               ltq_etop_gbit_init(dev);
 340 +               /* force the etops link to the gbit to MII */
 341 +               mii_mode = PHY_INTERFACE_MODE_MII;
 342 +       }
 343 +       ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
 344 +       ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
 345 +                       MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
 346 +
 347 +       switch (mii_mode) {
 348         case PHY_INTERFACE_MODE_RMII:
 349 -               ltq_etop_w32_mask(ETOP_MII_MASK,
 350 -                       ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 351 +               ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
 352 +                       ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
 353                 break;
 354
 355         case PHY_INTERFACE_MODE_MII:
 356 -               ltq_etop_w32_mask(ETOP_MII_MASK,
 357 -                       ETOP_MII_NORMAL, LTQ_ETOP_CFG);
 358 +               ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
 359 +                       ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
 360                 break;
 361
 362         default:
 363 +               if (of_machine_is_compatible("lantiq,ase")) {
 364 +                       clk_enable(priv->clk_ephy);
 365 +                       /* disable external MII */
 366 +                       ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 367 +                       /* enable clock for internal PHY */
 368 +                       clk_enable(priv->clk_ephycgu);
 369 +                       /* we need to write this magic to the internal phy to
 370 +                          make it work */
 371 +                       ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
 372 +                       pr_info("Selected EPHY mode\n");
 373 +                       break;
 374 +               }
 375                 netdev_err(dev, "unknown mii mode %d\n",
 376 -                       priv->pldata->mii_mode);
 377 +                       mii_mode);
 378                 return -ENOTSUPP;
 379         }
 380
 381 -       /* enable crc generation */
 382 -       ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 383 +       return 0;
 384 +}
 385
 386 -       ltq_dma_init_port(DMA_PORT_ETOP);
 387 +static int
 388 +ltq_etop_dma_init(struct net_device *dev)
 389 +{
 390 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 391 +       int tx = priv->tx_irq - LTQ_DMA_ETOP;
 392 +       int rx = priv->rx_irq - LTQ_DMA_ETOP;
 393 +       int err;
 394
 395 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 396 -               int irq = LTQ_DMA_CH0_INT + i;
 397 -               struct ltq_etop_chan *ch = &priv->ch[i];
 398 +       ltq_dma_init_port(DMA_PORT_ETOP);
 399
 400 -               ch->idx = ch->dma.nr = i;
 401 +       priv->txch.dma.nr = tx;
 402 +       ltq_dma_alloc_tx(&priv->txch.dma);
 403 +       err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
 404 +       if (err) {
 405 +               netdev_err(dev, "failed to allocate tx irq\n");
 406 +               goto err_out;
 407 +       }
 408 +       priv->txch.dma.irq = priv->tx_irq;
 409
 410 -               if (IS_TX(i)) {
 411 -                       ltq_dma_alloc_tx(&ch->dma);
 412 -                       request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
 413 -               } else if (IS_RX(i)) {
 414 -                       ltq_dma_alloc_rx(&ch->dma);
 415 -                       for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 416 -                                       ch->dma.desc++)
 417 -                               if (ltq_etop_alloc_skb(ch))
 418 -                                       return -ENOMEM;
 419 -                       ch->dma.desc = 0;
 420 -                       request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
 421 +       priv->rxch.dma.nr = rx;
 422 +       ltq_dma_alloc_rx(&priv->rxch.dma);
 423 +       for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
 424 +                       priv->rxch.dma.desc++) {
 425 +               if (ltq_etop_alloc_skb(&priv->rxch)) {
 426 +                       netdev_err(dev, "failed to allocate skbs\n");
 427 +                       err = -ENOMEM;
 428 +                       goto err_out;
 429                 }
 430 -               ch->dma.irq = irq;
 431         }
 432 -       return 0;
 433 +       priv->rxch.dma.desc = 0;
 434 +       err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
 435 +       if (err)
 436 +               netdev_err(dev, "failed to allocate rx irq\n");
 437 +       else
 438 +               priv->rxch.dma.irq = priv->rx_irq;
 439 +err_out:
 440 +       return err;
 441  }
 442
 443  static void
 444 @@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device
 445  {
 446         struct ltq_etop_priv *priv = netdev_priv(dev);
 447
 448 -       return phy_ethtool_gset(priv->phydev, cmd);
 449 +       if (priv->phydev)
 450 +               return phy_ethtool_gset(priv->phydev, cmd);
 451 +       else
 452 +               return 0;
 453  }
 454
 455  static int
 456 @@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device
 457  {
 458         struct ltq_etop_priv *priv = netdev_priv(dev);
 459
 460 -       return phy_ethtool_sset(priv->phydev, cmd);
 461 +       if (priv->phydev)
 462 +               return phy_ethtool_sset(priv->phydev, cmd);
 463 +       else
 464 +               return 0;
 465  }
 466
 467  static int
 468 @@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *d
 469  {
 470         struct ltq_etop_priv *priv = netdev_priv(dev);
 471
 472 -       return phy_start_aneg(priv->phydev);
 473 +       if (priv->phydev)
 474 +               return phy_start_aneg(priv->phydev);
 475 +       else
 476 +               return 0;
 477  }
 478
 479  static const struct ethtool_ops ltq_etop_ethtool_ops = {
 480 @@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop
 481  };
 482
 483  static int
 484 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
 485 +               int phy_reg, u16 phy_data)
 486 +{
 487 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
 488 +               (phy_data << MDIO_XR9_WR_OFFSET) |
 489 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 490 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 491 +
 492 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 493 +               ;
 494 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 495 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 496 +               ;
 497 +       return 0;
 498 +}
 499 +
 500 +static int
 501 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
 502 +{
 503 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
 504 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 505 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 506 +
 507 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 508 +               ;
 509 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 510 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 511 +               ;
 512 +       val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
 513 +       return val;
 514 +}
 515 +
 516 +static int
 517  ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 518  {
 519         u32 val = MDIO_REQUEST |
 520 @@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
 521                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
 522                 phy_data;
 523
 524 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 525 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 526                 ;
 527 -       ltq_etop_w32(val, LTQ_ETOP_MDIO);
 528 +       ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
 529         return 0;
 530  }
 531
 532 @@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
 533                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 534                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
 535
 536 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 537 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 538                 ;
 539 -       ltq_etop_w32(val, LTQ_ETOP_MDIO);
 540 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 541 +       ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
 542 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 543                 ;
 544 -       val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
 545 +       val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
 546         return val;
 547  }
 548
 549 @@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *d
 550  {
 551         struct ltq_etop_priv *priv = netdev_priv(dev);
 552         struct phy_device *phydev = NULL;
 553 -       int phy_addr;
 554 +       u32 phy_supported =  (SUPPORTED_10baseT_Half
 555 +                       | SUPPORTED_10baseT_Full
 556 +                       | SUPPORTED_100baseT_Half
 557 +                       | SUPPORTED_100baseT_Full
 558 +                       | SUPPORTED_Autoneg
 559 +                       | SUPPORTED_MII
 560 +                       | SUPPORTED_TP);
 561
 562 -       for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 563 -               if (priv->mii_bus->phy_map[phy_addr]) {
 564 -                       phydev = priv->mii_bus->phy_map[phy_addr];
 565 -                       break;
 566 -               }
 567 -       }
 568 +       if (of_machine_is_compatible("lantiq,ase"))
 569 +               phydev = priv->mii_bus->phy_map[8];
 570 +       else
 571 +               phydev = priv->mii_bus->phy_map[0];
 572
 573         if (!phydev) {
 574                 netdev_err(dev, "no PHY found\n");
 575 @@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *d
 576         }
 577
 578         phydev = phy_connect(dev, dev_name(&phydev->dev),
 579 -                            &ltq_etop_mdio_link, priv->pldata->mii_mode);
 580 +                       &ltq_etop_mdio_link, priv->mii_mode);
 581
 582         if (IS_ERR(phydev)) {
 583                 netdev_err(dev, "Could not attach to PHY\n");
 584                 return PTR_ERR(phydev);
 585         }
 586
 587 -       phydev->supported &= (SUPPORTED_10baseT_Half
 588 -                             | SUPPORTED_10baseT_Full
 589 -                             | SUPPORTED_100baseT_Half
 590 -                             | SUPPORTED_100baseT_Full
 591 -                             | SUPPORTED_Autoneg
 592 -                             | SUPPORTED_MII
 593 -                             | SUPPORTED_TP);
 594 +       if (of_machine_is_compatible("lantiq,ar9"))
 595 +               phy_supported |= SUPPORTED_1000baseT_Half
 596 +                       | SUPPORTED_1000baseT_Full;
 597
 598 +       phydev->supported &= phy_supported;
 599         phydev->advertising = phydev->supported;
 600         priv->phydev = phydev;
 601         pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
 602 @@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *de
 603         }
 604
 605         priv->mii_bus->priv = dev;
 606 -       priv->mii_bus->read = ltq_etop_mdio_rd;
 607 -       priv->mii_bus->write = ltq_etop_mdio_wr;
 608 +       if (of_machine_is_compatible("lantiq,ar9")) {
 609 +               priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
 610 +               priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
 611 +       } else {
 612 +               priv->mii_bus->read = ltq_etop_mdio_rd;
 613 +               priv->mii_bus->write = ltq_etop_mdio_wr;
 614 +       }
 615         priv->mii_bus->name = "ltq_mii";
 616         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 617                 priv->pdev->name, priv->pdev->id);
 618 @@ -480,17 +673,19 @@ static int
 619  ltq_etop_open(struct net_device *dev)
 620  {
 621         struct ltq_etop_priv *priv = netdev_priv(dev);
 622 -       int i;
 623 +       unsigned long flags;
 624
 625 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 626 -               struct ltq_etop_chan *ch = &priv->ch[i];
 627 +       napi_enable(&priv->txch.napi);
 628 +       napi_enable(&priv->rxch.napi);
 629 +
 630 +       spin_lock_irqsave(&priv->lock, flags);
 631 +       ltq_dma_open(&priv->txch.dma);
 632 +       ltq_dma_open(&priv->rxch.dma);
 633 +       spin_unlock_irqrestore(&priv->lock, flags);
 634 +
 635 +       if (priv->phydev)
 636 +               phy_start(priv->phydev);
 637
 638 -               if (!IS_TX(i) && (!IS_RX(i)))
 639 -                       continue;
 640 -               ltq_dma_open(&ch->dma);
 641 -               napi_enable(&ch->napi);
 642 -       }
 643 -       phy_start(priv->phydev);
 644         netif_tx_start_all_queues(dev);
 645         return 0;
 646  }
 647 @@ -499,18 +694,19 @@ static int
 648  ltq_etop_stop(struct net_device *dev)
 649  {
 650         struct ltq_etop_priv *priv = netdev_priv(dev);
 651 -       int i;
 652 +       unsigned long flags;
 653
 654         netif_tx_stop_all_queues(dev);
 655 -       phy_stop(priv->phydev);
 656 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 657 -               struct ltq_etop_chan *ch = &priv->ch[i];
 658 +       if (priv->phydev)
 659 +               phy_stop(priv->phydev);
 660 +       napi_disable(&priv->txch.napi);
 661 +       napi_disable(&priv->rxch.napi);
 662 +
 663 +       spin_lock_irqsave(&priv->lock, flags);
 664 +       ltq_dma_close(&priv->txch.dma);
 665 +       ltq_dma_close(&priv->rxch.dma);
 666 +       spin_unlock_irqrestore(&priv->lock, flags);
 667
 668 -               if (!IS_RX(i) && !IS_TX(i))
 669 -                       continue;
 670 -               napi_disable(&ch->napi);
 671 -               ltq_dma_close(&ch->dma);
 672 -       }
 673         return 0;
 674  }
 675
 676 @@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
 677         int queue = skb_get_queue_mapping(skb);
 678         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 679         struct ltq_etop_priv *priv = netdev_priv(dev);
 680 -       struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 681 -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 682 -       int len;
 683 +       struct ltq_dma_desc *desc =
 684 +               &priv->txch.dma.desc_base[priv->txch.dma.desc];
 685         unsigned long flags;
 686         u32 byte_offset;
 687 +       int len;
 688
 689         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 690
 691 -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 692 -               dev_kfree_skb_any(skb);
 693 +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
 694 +                       priv->txch.skb[priv->txch.dma.desc]) {
 695                 netdev_err(dev, "tx ring full\n");
 696                 netif_tx_stop_queue(txq);
 697                 return NETDEV_TX_BUSY;
 698 @@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
 699
 700         /* dma needs to start on a 16 byte aligned address */
 701         byte_offset = CPHYSADDR(skb->data) % 16;
 702 -       ch->skb[ch->dma.desc] = skb;
 703 +       priv->txch.skb[priv->txch.dma.desc] = skb;
 704
 705         dev->trans_start = jiffies;
 706
 707 @@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
 708         wmb();
 709         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 710                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 711 -       ch->dma.desc++;
 712 -       ch->dma.desc %= LTQ_DESC_NUM;
 713 +       priv->txch.dma.desc++;
 714 +       priv->txch.dma.desc %= LTQ_DESC_NUM;
 715         spin_unlock_irqrestore(&priv->lock, flags);
 716
 717 -       if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 718 +       if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
 719                 netif_tx_stop_queue(txq);
 720
 721         return NETDEV_TX_OK;
 722 @@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *d
 723                 struct ltq_etop_priv *priv = netdev_priv(dev);
 724                 unsigned long flags;
 725
 726 +               int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
 727 +
 728                 spin_lock_irqsave(&priv->lock, flags);
 729 -               ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
 730 +               ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
 731                         LTQ_ETOP_IGPLEN);
 732                 spin_unlock_irqrestore(&priv->lock, flags);
 733         }
 734 @@ -638,6 +836,9 @@ ltq_etop_init(struct net_device *dev)
 735         if (err)
 736                 goto err_hw;
 737         ltq_etop_change_mtu(dev, 1500);
 738 +       err = ltq_etop_dma_init(dev);
 739 +       if (err)
 740 +               goto err_hw;
 741
 742         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 743         if (!is_valid_ether_addr(mac.sa_data)) {
 744 @@ -655,9 +856,10 @@ ltq_etop_init(struct net_device *dev)
 745                 dev->addr_assign_type = NET_ADDR_RANDOM;
 746
 747         ltq_etop_set_multicast_list(dev);
 748 -       err = ltq_etop_mdio_init(dev);
 749 -       if (err)
 750 -               goto err_netdev;
 751 +       if (!ltq_etop_mdio_init(dev))
 752 +               dev->ethtool_ops = &ltq_etop_ethtool_ops;
 753 +       else
 754 +               pr_warn("etop: mdio probe failed\n");;
 755         return 0;
 756
 757  err_netdev:
 758 @@ -677,6 +879,9 @@ ltq_etop_tx_timeout(struct net_device *d
 759         err = ltq_etop_hw_init(dev);
 760         if (err)
 761                 goto err_hw;
 762 +       err = ltq_etop_dma_init(dev);
 763 +       if (err)
 764 +               goto err_hw;
 765         dev->trans_start = jiffies;
 766         netif_wake_queue(dev);
 767         return;
 768 @@ -700,14 +905,19 @@ static const struct net_device_ops ltq_e
 769         .ndo_tx_timeout = ltq_etop_tx_timeout,
 770  };
 771
 772 -static int __init
 773 -ltq_etop_probe(struct platform_device *pdev)
 774 +static int ltq_etop_probe(struct platform_device *pdev)
 775  {
 776         struct net_device *dev;
 777         struct ltq_etop_priv *priv;
 778 -       struct resource *res;
 779 +       struct resource *res, *gbit_res, irqres[2];
 780 +       const u8 *mac;
 781         int err;
 782 -       int i;
 783 +
 784 +       err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
 785 +       if (err != 2) {
 786 +               dev_err(&pdev->dev, "failed to get etop irqs\n");
 787 +               return -EINVAL;
 788 +       }
 789
 790         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 791         if (!res) {
 792 @@ -733,31 +943,62 @@ ltq_etop_probe(struct platform_device *p
 793                 goto err_out;
 794         }
 795
 796 -       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 797 -       if (!dev) {
 798 -               err = -ENOMEM;
 799 -               goto err_out;
 800 +       if (of_machine_is_compatible("lantiq,ar9")) {
 801 +               gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 802 +               if (!gbit_res) {
 803 +                       dev_err(&pdev->dev, "failed to get gbit resource\n");
 804 +                       err = -ENOENT;
 805 +                       goto err_out;
 806 +               }
 807 +               ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
 808 +                       gbit_res->start, resource_size(gbit_res));
 809 +               if (!ltq_gbit_membase) {
 810 +                       dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
 811 +                               pdev->id);
 812 +                       err = -ENOMEM;
 813 +                       goto err_out;
 814 +               }
 815         }
 816 +
 817 +       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 818         strcpy(dev->name, "eth%d");
 819         dev->netdev_ops = &ltq_eth_netdev_ops;
 820 -       dev->ethtool_ops = &ltq_etop_ethtool_ops;
 821         priv = netdev_priv(dev);
 822         priv->res = res;
 823         priv->pdev = pdev;
 824 -       priv->pldata = dev_get_platdata(&pdev->dev);
 825         priv->netdev = dev;
 826 -       spin_lock_init(&priv->lock);
 827 +       priv->tx_irq = irqres[0].start;
 828 +       priv->rx_irq = irqres[1].start;
 829 +       priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
 830
 831 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 832 -               if (IS_TX(i))
 833 -                       netif_napi_add(dev, &priv->ch[i].napi,
 834 -                               ltq_etop_poll_tx, 8);
 835 -               else if (IS_RX(i))
 836 -                       netif_napi_add(dev, &priv->ch[i].napi,
 837 -                               ltq_etop_poll_rx, 32);
 838 -               priv->ch[i].netdev = dev;
 839 +       mac = of_get_mac_address(pdev->dev.of_node);
 840 +       if (mac)
 841 +               memcpy(priv->mac, mac, ETH_ALEN);
 842 +
 843 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 844 +       if (IS_ERR(priv->clk_ppe))
 845 +               return PTR_ERR(priv->clk_ppe);
 846 +       if (of_machine_is_compatible("lantiq,ar9")) {
 847 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 848 +               if (IS_ERR(priv->clk_switch))
 849 +                       return PTR_ERR(priv->clk_switch);
 850 +       }
 851 +       if (of_machine_is_compatible("lantiq,ase")) {
 852 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 853 +               if (IS_ERR(priv->clk_ephy))
 854 +                       return PTR_ERR(priv->clk_ephy);
 855 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 856 +               if (IS_ERR(priv->clk_ephycgu))
 857 +                       return PTR_ERR(priv->clk_ephycgu);
 858         }
 859
 860 +       spin_lock_init(&priv->lock);
 861 +
 862 +       netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
 863 +       netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
 864 +       priv->txch.netdev = dev;
 865 +       priv->rxch.netdev = dev;
 866 +
 867         err = register_netdev(dev);
 868         if (err)
 869                 goto err_free;
 870 @@ -785,31 +1026,22 @@ ltq_etop_remove(struct platform_device *
 871         return 0;
 872  }
 873
 874 +static const struct of_device_id ltq_etop_match[] = {
 875 +       { .compatible = "lantiq,etop-xway" },
 876 +       {},
 877 +};
 878 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
 879 +
 880  static struct platform_driver ltq_mii_driver = {
 881 +       .probe = ltq_etop_probe,
 882         .remove = ltq_etop_remove,
 883         .driver = {
 884                 .name = "ltq_etop",
 885 +               .of_match_table = ltq_etop_match,
 886         },
 887  };
 888
 889 -int __init
 890 -init_ltq_etop(void)
 891 -{
 892 -       int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 893 -
 894 -       if (ret)
 895 -               pr_err("ltq_etop: Error registering platform driver!");
 896 -       return ret;
 897 -}
 898 -
 899 -static void __exit
 900 -exit_ltq_etop(void)
 901 -{
 902 -       platform_driver_unregister(&ltq_mii_driver);
 903 -}
 904 -
 905 -module_init(init_ltq_etop);
 906 -module_exit(exit_ltq_etop);
 907 +module_platform_driver(ltq_mii_driver);
 908
 909  MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 910  MODULE_DESCRIPTION("Lantiq SoC ETOP");