target/linux/lantiq/patches-4.19/0028-NET-lantiq-various-etop-fixes.patch

   1 From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 9 Sep 2014 22:45:34 +0200
   4 Subject: [PATCH 28/36] NET: lantiq: various etop fixes
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
   9  1 file changed, 389 insertions(+), 166 deletions(-)
  10
  11 --- a/drivers/net/ethernet/lantiq_etop.c
  12 +++ b/drivers/net/ethernet/lantiq_etop.c
  13 @@ -11,7 +11,7 @@
  14   *   You should have received a copy of the GNU General Public License
  15   *   along with this program; if not, see <http://www.gnu.org/licenses/>.
  16   *
  17 - *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  18 + *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
  19   */
  20
  21  #include <linux/kernel.h>
  22 @@ -30,11 +30,16 @@
  23  #include <linux/mm.h>
  24  #include <linux/platform_device.h>
  25  #include <linux/ethtool.h>
  26 +#include <linux/if_vlan.h>
  27  #include <linux/init.h>
  28  #include <linux/delay.h>
  29  #include <linux/io.h>
  30  #include <linux/dma-mapping.h>
  31  #include <linux/module.h>
  32 +#include <linux/clk.h>
  33 +#include <linux/of_net.h>
  34 +#include <linux/of_irq.h>
  35 +#include <linux/of_platform.h>
  36
  37  #include <asm/checksum.h>
  38
  39 @@ -42,7 +47,7 @@
  40  #include <xway_dma.h>
  41  #include <lantiq_platform.h>
  42
  43 -#define LTQ_ETOP_MDIO          0x11804
  44 +#define LTQ_ETOP_MDIO_ACC      0x11804
  45  #define MDIO_REQUEST           0x80000000
  46  #define MDIO_READ              0x40000000
  47  #define MDIO_ADDR_MASK         0x1f
  48 @@ -51,44 +56,91 @@
  49  #define MDIO_REG_OFFSET                0x10
  50  #define MDIO_VAL_MASK          0xffff
  51
  52 -#define PPE32_CGEN             0x800
  53 -#define LQ_PPE32_ENET_MAC_CFG  0x1840
  54 +#define LTQ_ETOP_MDIO_CFG       0x11800
  55 +#define MDIO_CFG_MASK           0x6
  56 +
  57 +#define LTQ_ETOP_CFG            0x11808
  58 +#define LTQ_ETOP_IGPLEN         0x11820
  59 +#define LTQ_ETOP_MAC_CFG       0x11840
  60
  61  #define LTQ_ETOP_ENETS0                0x11850
  62  #define LTQ_ETOP_MAC_DA0       0x1186C
  63  #define LTQ_ETOP_MAC_DA1       0x11870
  64 -#define LTQ_ETOP_CFG           0x16020
  65 -#define LTQ_ETOP_IGPLEN                0x16080
  66 +
  67 +#define MAC_CFG_MASK           0xfff
  68 +#define MAC_CFG_CGEN           (1 << 11)
  69 +#define MAC_CFG_DUPLEX         (1 << 2)
  70 +#define MAC_CFG_SPEED          (1 << 1)
  71 +#define MAC_CFG_LINK           (1 << 0)
  72
  73  #define MAX_DMA_CHAN           0x8
  74  #define MAX_DMA_CRC_LEN                0x4
  75  #define MAX_DMA_DATA_LEN       0x600
  76
  77  #define ETOP_FTCU              BIT(28)
  78 -#define ETOP_MII_MASK          0xf
  79 -#define ETOP_MII_NORMAL                0xd
  80 -#define ETOP_MII_REVERSE       0xe
  81  #define ETOP_PLEN_UNDER                0x40
  82 -#define ETOP_CGEN              0x800
  83 +#define ETOP_CFG_MII0          0x01
  84
  85 -/* use 2 static channels for TX/RX */
  86 -#define LTQ_ETOP_TX_CHANNEL    1
  87 -#define LTQ_ETOP_RX_CHANNEL    6
  88 -#define IS_TX(x)               (x == LTQ_ETOP_TX_CHANNEL)
  89 -#define IS_RX(x)               (x == LTQ_ETOP_RX_CHANNEL)
  90 +#define ETOP_CFG_MASK           0xfff
  91 +#define ETOP_CFG_FEN0          (1 << 8)
  92 +#define ETOP_CFG_SEN0          (1 << 6)
  93 +#define ETOP_CFG_OFF1          (1 << 3)
  94 +#define ETOP_CFG_REMII0                (1 << 1)
  95 +#define ETOP_CFG_OFF0          (1 << 0)
  96 +
  97 +#define LTQ_GBIT_MDIO_CTL      0xCC
  98 +#define LTQ_GBIT_MDIO_DATA     0xd0
  99 +#define LTQ_GBIT_GCTL0         0x68
 100 +#define LTQ_GBIT_PMAC_HD_CTL   0x8c
 101 +#define LTQ_GBIT_P0_CTL                0x4
 102 +#define LTQ_GBIT_PMAC_RX_IPG   0xa8
 103 +#define LTQ_GBIT_RGMII_CTL     0x78
 104 +
 105 +#define PMAC_HD_CTL_AS         (1 << 19)
 106 +#define PMAC_HD_CTL_RXSH       (1 << 22)
 107 +
 108 +/* Switch Enable (0=disable, 1=enable) */
 109 +#define GCTL0_SE               0x80000000
 110 +/* Disable MDIO auto polling (0=disable, 1=enable) */
 111 +#define PX_CTL_DMDIO           0x00400000
 112 +
 113 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
 114 +#define MDC_CLOCK_MASK         0xff000000
 115 +#define MDC_CLOCK_OFFSET       24
 116 +
 117 +/* register information for the gbit's MDIO bus */
 118 +#define MDIO_XR9_REQUEST       0x00008000
 119 +#define MDIO_XR9_READ          0x00000800
 120 +#define MDIO_XR9_WRITE         0x00000400
 121 +#define MDIO_XR9_REG_MASK      0x1f
 122 +#define MDIO_XR9_ADDR_MASK     0x1f
 123 +#define MDIO_XR9_RD_MASK       0xffff
 124 +#define MDIO_XR9_REG_OFFSET    0
 125 +#define MDIO_XR9_ADDR_OFFSET   5
 126 +#define MDIO_XR9_WR_OFFSET     16
 127
 128 +#define LTQ_DMA_ETOP   ((of_machine_is_compatible("lantiq,ase")) ? \
 129 +                       (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
 130 +
 131 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
 132  #define ltq_etop_r32(x)                ltq_r32(ltq_etop_membase + (x))
 133  #define ltq_etop_w32(x, y)     ltq_w32(x, ltq_etop_membase + (y))
 134  #define ltq_etop_w32_mask(x, y, z)     \
 135                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
 136
 137 -#define DRV_VERSION    "1.0"
 138 +#define ltq_gbit_r32(x)                ltq_r32(ltq_gbit_membase + (x))
 139 +#define ltq_gbit_w32(x, y)     ltq_w32(x, ltq_gbit_membase + (y))
 140 +#define ltq_gbit_w32_mask(x, y, z)     \
 141 +               ltq_w32_mask(x, y, ltq_gbit_membase + (z))
 142 +
 143 +#define DRV_VERSION    "1.2"
 144
 145  static void __iomem *ltq_etop_membase;
 146 +static void __iomem *ltq_gbit_membase;
 147
 148  struct ltq_etop_chan {
 149 -       int idx;
 150         int tx_free;
 151 +       int irq;
 152         struct net_device *netdev;
 153         struct napi_struct napi;
 154         struct ltq_dma_channel dma;
 155 @@ -98,21 +150,34 @@ struct ltq_etop_chan {
 156  struct ltq_etop_priv {
 157         struct net_device *netdev;
 158         struct platform_device *pdev;
 159 -       struct ltq_eth_data *pldata;
 160         struct resource *res;
 161
 162         struct mii_bus *mii_bus;
 163
 164 -       struct ltq_etop_chan ch[MAX_DMA_CHAN];
 165 -       int tx_free[MAX_DMA_CHAN >> 1];
 166 +       struct ltq_etop_chan txch;
 167 +       struct ltq_etop_chan rxch;
 168
 169 -       spinlock_t lock;
 170 +       int tx_irq;
 171 +       int rx_irq;
 172 +
 173 +       unsigned char mac[6];
 174 +       int mii_mode;
 175 +
 176 +       spinlock_t lock;
 177 +
 178 +       struct clk *clk_ppe;
 179 +       struct clk *clk_switch;
 180 +       struct clk *clk_ephy;
 181 +       struct clk *clk_ephycgu;
 182  };
 183
 184 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
 185 +                               int phy_reg, u16 phy_data);
 186 +
 187  static int
 188  ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 189  {
 190 -       ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 191 +       ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
 192         if (!ch->skb[ch->dma.desc])
 193                 return -ENOMEM;
 194         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
 195 @@ -147,8 +212,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
 196         spin_unlock_irqrestore(&priv->lock, flags);
 197
 198         skb_put(skb, len);
 199 +       skb->dev = ch->netdev;
 200         skb->protocol = eth_type_trans(skb, ch->netdev);
 201         netif_receive_skb(skb);
 202 +       ch->netdev->stats.rx_packets++;
 203 +       ch->netdev->stats.rx_bytes += len;
 204  }
 205
 206  static int
 207 @@ -156,7 +224,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
 208  {
 209         struct ltq_etop_chan *ch = container_of(napi,
 210                                 struct ltq_etop_chan, napi);
 211 +       struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 212         int work_done = 0;
 213 +       unsigned long flags;
 214
 215         while (work_done < budget) {
 216                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 217 @@ -168,7 +238,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
 218         }
 219         if (work_done < budget) {
 220                 napi_complete_done(&ch->napi, work_done);
 221 +               spin_lock_irqsave(&priv->lock, flags);
 222                 ltq_dma_ack_irq(&ch->dma);
 223 +               spin_unlock_irqrestore(&priv->lock, flags);
 224         }
 225         return work_done;
 226  }
 227 @@ -180,12 +252,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
 228                 container_of(napi, struct ltq_etop_chan, napi);
 229         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 230         struct netdev_queue *txq =
 231 -               netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 232 +               netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
 233         unsigned long flags;
 234
 235         spin_lock_irqsave(&priv->lock, flags);
 236         while ((ch->dma.desc_base[ch->tx_free].ctl &
 237                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 238 +               ch->netdev->stats.tx_packets++;
 239 +               ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
 240                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 241                 ch->skb[ch->tx_free] = NULL;
 242                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 243 @@ -198,7 +272,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
 244         if (netif_tx_queue_stopped(txq))
 245                 netif_tx_start_queue(txq);
 246         napi_complete(&ch->napi);
 247 +       spin_lock_irqsave(&priv->lock, flags);
 248         ltq_dma_ack_irq(&ch->dma);
 249 +       spin_unlock_irqrestore(&priv->lock, flags);
 250         return 1;
 251  }
 252
 253 @@ -206,9 +282,10 @@ static irqreturn_t
 254  ltq_etop_dma_irq(int irq, void *_priv)
 255  {
 256         struct ltq_etop_priv *priv = _priv;
 257 -       int ch = irq - LTQ_DMA_CH0_INT;
 258 -
 259 -       napi_schedule(&priv->ch[ch].napi);
 260 +       if (irq == priv->txch.dma.irq)
 261 +               napi_schedule(&priv->txch.napi);
 262 +       else
 263 +               napi_schedule(&priv->rxch.napi);
 264         return IRQ_HANDLED;
 265  }
 266
 267 @@ -220,7 +297,7 @@ ltq_etop_free_channel(struct net_device
 268         ltq_dma_free(&ch->dma);
 269         if (ch->dma.irq)
 270                 free_irq(ch->dma.irq, priv);
 271 -       if (IS_RX(ch->idx)) {
 272 +       if (ch == &priv->txch) {
 273                 int desc;
 274                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 275                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 276 @@ -231,66 +308,135 @@ static void
 277  ltq_etop_hw_exit(struct net_device *dev)
 278  {
 279         struct ltq_etop_priv *priv = netdev_priv(dev);
 280 -       int i;
 281
 282 -       ltq_pmu_disable(PMU_PPE);
 283 -       for (i = 0; i < MAX_DMA_CHAN; i++)
 284 -               if (IS_TX(i) || IS_RX(i))
 285 -                       ltq_etop_free_channel(dev, &priv->ch[i]);
 286 +       clk_disable(priv->clk_ppe);
 287 +
 288 +       if (of_machine_is_compatible("lantiq,ar9"))
 289 +               clk_disable(priv->clk_switch);
 290 +
 291 +       if (of_machine_is_compatible("lantiq,ase")) {
 292 +               clk_disable(priv->clk_ephy);
 293 +               clk_disable(priv->clk_ephycgu);
 294 +       }
 295 +
 296 +       ltq_etop_free_channel(dev, &priv->txch);
 297 +       ltq_etop_free_channel(dev, &priv->rxch);
 298 +}
 299 +
 300 +static void
 301 +ltq_etop_gbit_init(struct net_device *dev)
 302 +{
 303 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 304 +
 305 +       clk_enable(priv->clk_switch);
 306 +
 307 +       /* enable gbit port0 on the SoC */
 308 +       ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
 309 +
 310 +       ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 311 +       /* disable MDIO auto polling mode */
 312 +       ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
 313 +       /* set 1522 packet size */
 314 +       ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
 315 +       /* disable pmac & dmac headers */
 316 +       ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
 317 +               LTQ_GBIT_PMAC_HD_CTL);
 318 +       /* Due to traffic halt when burst length 8,
 319 +               replace default IPG value with 0x3B */
 320 +       ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
 321 +       /* set mdc clock to 2.5 MHz */
 322 +       ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
 323 +               LTQ_GBIT_RGMII_CTL);
 324  }
 325
 326  static int
 327  ltq_etop_hw_init(struct net_device *dev)
 328  {
 329         struct ltq_etop_priv *priv = netdev_priv(dev);
 330 -       int i;
 331 +       int mii_mode = priv->mii_mode;
 332 +
 333 +       clk_enable(priv->clk_ppe);
 334
 335 -       ltq_pmu_enable(PMU_PPE);
 336 +       if (of_machine_is_compatible("lantiq,ar9")) {
 337 +               ltq_etop_gbit_init(dev);
 338 +               /* force the etops link to the gbit to MII */
 339 +               mii_mode = PHY_INTERFACE_MODE_MII;
 340 +       }
 341 +       ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
 342 +       ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
 343 +                       MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
 344
 345 -       switch (priv->pldata->mii_mode) {
 346 +       switch (mii_mode) {
 347         case PHY_INTERFACE_MODE_RMII:
 348 -               ltq_etop_w32_mask(ETOP_MII_MASK,
 349 -                       ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 350 +               ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
 351 +                       ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
 352                 break;
 353
 354         case PHY_INTERFACE_MODE_MII:
 355 -               ltq_etop_w32_mask(ETOP_MII_MASK,
 356 -                       ETOP_MII_NORMAL, LTQ_ETOP_CFG);
 357 +               ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
 358 +                       ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
 359                 break;
 360
 361         default:
 362 +               if (of_machine_is_compatible("lantiq,ase")) {
 363 +                       clk_enable(priv->clk_ephy);
 364 +                       /* disable external MII */
 365 +                       ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 366 +                       /* enable clock for internal PHY */
 367 +                       clk_enable(priv->clk_ephycgu);
 368 +                       /* we need to write this magic to the internal phy to
 369 +                          make it work */
 370 +                       ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
 371 +                       pr_info("Selected EPHY mode\n");
 372 +                       break;
 373 +               }
 374                 netdev_err(dev, "unknown mii mode %d\n",
 375 -                       priv->pldata->mii_mode);
 376 +                       mii_mode);
 377                 return -ENOTSUPP;
 378         }
 379
 380 -       /* enable crc generation */
 381 -       ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 382 +       return 0;
 383 +}
 384 +
 385 +static int
 386 +ltq_etop_dma_init(struct net_device *dev)
 387 +{
 388 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 389 +       int tx = priv->tx_irq - LTQ_DMA_ETOP;
 390 +       int rx = priv->rx_irq - LTQ_DMA_ETOP;
 391 +       int err;
 392
 393         ltq_dma_init_port(DMA_PORT_ETOP);
 394
 395 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 396 -               int irq = LTQ_DMA_CH0_INT + i;
 397 -               struct ltq_etop_chan *ch = &priv->ch[i];
 398 -
 399 -               ch->idx = ch->dma.nr = i;
 400 -               ch->dma.dev = &priv->pdev->dev;
 401 -
 402 -               if (IS_TX(i)) {
 403 -                       ltq_dma_alloc_tx(&ch->dma);
 404 -                       request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
 405 -               } else if (IS_RX(i)) {
 406 -                       ltq_dma_alloc_rx(&ch->dma);
 407 -                       for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 408 -                                       ch->dma.desc++)
 409 -                               if (ltq_etop_alloc_skb(ch))
 410 -                                       return -ENOMEM;
 411 -                       ch->dma.desc = 0;
 412 -                       request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
 413 +       priv->txch.dma.nr = tx;
 414 +       priv->txch.dma.dev = &priv->pdev->dev;
 415 +       ltq_dma_alloc_tx(&priv->txch.dma);
 416 +       err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
 417 +       if (err) {
 418 +               netdev_err(dev, "failed to allocate tx irq\n");
 419 +               goto err_out;
 420 +       }
 421 +       priv->txch.dma.irq = priv->tx_irq;
 422 +
 423 +       priv->rxch.dma.nr = rx;
 424 +       priv->rxch.dma.dev = &priv->pdev->dev;
 425 +       ltq_dma_alloc_rx(&priv->rxch.dma);
 426 +       for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
 427 +                       priv->rxch.dma.desc++) {
 428 +               if (ltq_etop_alloc_skb(&priv->rxch)) {
 429 +                       netdev_err(dev, "failed to allocate skbs\n");
 430 +                       err = -ENOMEM;
 431 +                       goto err_out;
 432                 }
 433 -               ch->dma.irq = irq;
 434         }
 435 -       return 0;
 436 +       priv->rxch.dma.desc = 0;
 437 +       err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
 438 +       if (err)
 439 +               netdev_err(dev, "failed to allocate rx irq\n");
 440 +       else
 441 +               priv->rxch.dma.irq = priv->rx_irq;
 442 +err_out:
 443 +       return err;
 444  }
 445
 446  static void
 447 @@ -309,6 +455,39 @@ static const struct ethtool_ops ltq_etop
 448  };
 449
 450  static int
 451 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
 452 +               int phy_reg, u16 phy_data)
 453 +{
 454 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
 455 +               (phy_data << MDIO_XR9_WR_OFFSET) |
 456 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 457 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 458 +
 459 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 460 +               ;
 461 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 462 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 463 +               ;
 464 +       return 0;
 465 +}
 466 +
 467 +static int
 468 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
 469 +{
 470 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
 471 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 472 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 473 +
 474 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 475 +               ;
 476 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 477 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 478 +               ;
 479 +       val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
 480 +       return val;
 481 +}
 482 +
 483 +static int
 484  ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 485  {
 486         u32 val = MDIO_REQUEST |
 487 @@ -316,9 +495,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
 488                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
 489                 phy_data;
 490
 491 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 492 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 493                 ;
 494 -       ltq_etop_w32(val, LTQ_ETOP_MDIO);
 495 +       ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
 496         return 0;
 497  }
 498
 499 @@ -329,12 +508,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
 500                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 501                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
 502
 503 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 504 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 505                 ;
 506 -       ltq_etop_w32(val, LTQ_ETOP_MDIO);
 507 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 508 +       ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
 509 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 510                 ;
 511 -       val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
 512 +       val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
 513         return val;
 514  }
 515
 516 @@ -349,8 +528,18 @@ ltq_etop_mdio_probe(struct net_device *d
 517  {
 518         struct ltq_etop_priv *priv = netdev_priv(dev);
 519         struct phy_device *phydev;
 520 +       u32 phy_supported =  (SUPPORTED_10baseT_Half
 521 +                       | SUPPORTED_10baseT_Full
 522 +                       | SUPPORTED_100baseT_Half
 523 +                       | SUPPORTED_100baseT_Full
 524 +                       | SUPPORTED_Autoneg
 525 +                       | SUPPORTED_MII
 526 +                       | SUPPORTED_TP);
 527
 528 -       phydev = phy_find_first(priv->mii_bus);
 529 +       if (of_machine_is_compatible("lantiq,ase"))
 530 +               phydev = mdiobus_get_phy(priv->mii_bus, 8);
 531 +       else
 532 +               phydev = mdiobus_get_phy(priv->mii_bus, 0);
 533
 534         if (!phydev) {
 535                 netdev_err(dev, "no PHY found\n");
 536 @@ -358,21 +547,18 @@ ltq_etop_mdio_probe(struct net_device *d
 537         }
 538
 539         phydev = phy_connect(dev, phydev_name(phydev),
 540 -                            &ltq_etop_mdio_link, priv->pldata->mii_mode);
 541 +                            &ltq_etop_mdio_link, priv->mii_mode);
 542
 543         if (IS_ERR(phydev)) {
 544                 netdev_err(dev, "Could not attach to PHY\n");
 545                 return PTR_ERR(phydev);
 546         }
 547
 548 -       phydev->supported &= (SUPPORTED_10baseT_Half
 549 -                             | SUPPORTED_10baseT_Full
 550 -                             | SUPPORTED_100baseT_Half
 551 -                             | SUPPORTED_100baseT_Full
 552 -                             | SUPPORTED_Autoneg
 553 -                             | SUPPORTED_MII
 554 -                             | SUPPORTED_TP);
 555 +       if (of_machine_is_compatible("lantiq,ar9"))
 556 +               phy_supported |= SUPPORTED_1000baseT_Half
 557 +                       | SUPPORTED_1000baseT_Full;
 558
 559 +       phydev->supported &= phy_supported;
 560         phydev->advertising = phydev->supported;
 561         phy_attached_info(phydev);
 562
 563 @@ -393,8 +579,13 @@ ltq_etop_mdio_init(struct net_device *de
 564         }
 565
 566         priv->mii_bus->priv = dev;
 567 -       priv->mii_bus->read = ltq_etop_mdio_rd;
 568 -       priv->mii_bus->write = ltq_etop_mdio_wr;
 569 +       if (of_machine_is_compatible("lantiq,ar9")) {
 570 +               priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
 571 +               priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
 572 +       } else {
 573 +               priv->mii_bus->read = ltq_etop_mdio_rd;
 574 +               priv->mii_bus->write = ltq_etop_mdio_wr;
 575 +       }
 576         priv->mii_bus->name = "ltq_mii";
 577         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 578                 priv->pdev->name, priv->pdev->id);
 579 @@ -431,17 +622,19 @@ static int
 580  ltq_etop_open(struct net_device *dev)
 581  {
 582         struct ltq_etop_priv *priv = netdev_priv(dev);
 583 -       int i;
 584 +       unsigned long flags;
 585
 586 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 587 -               struct ltq_etop_chan *ch = &priv->ch[i];
 588 +       napi_enable(&priv->txch.napi);
 589 +       napi_enable(&priv->rxch.napi);
 590 +
 591 +       spin_lock_irqsave(&priv->lock, flags);
 592 +       ltq_dma_open(&priv->txch.dma);
 593 +       ltq_dma_open(&priv->rxch.dma);
 594 +       spin_unlock_irqrestore(&priv->lock, flags);
 595 +
 596 +       if (dev->phydev)
 597 +               phy_start(dev->phydev);
 598
 599 -               if (!IS_TX(i) && (!IS_RX(i)))
 600 -                       continue;
 601 -               ltq_dma_open(&ch->dma);
 602 -               napi_enable(&ch->napi);
 603 -       }
 604 -       phy_start(dev->phydev);
 605         netif_tx_start_all_queues(dev);
 606         return 0;
 607  }
 608 @@ -450,18 +643,19 @@ static int
 609  ltq_etop_stop(struct net_device *dev)
 610  {
 611         struct ltq_etop_priv *priv = netdev_priv(dev);
 612 -       int i;
 613 +       unsigned long flags;
 614
 615         netif_tx_stop_all_queues(dev);
 616 -       phy_stop(dev->phydev);
 617 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 618 -               struct ltq_etop_chan *ch = &priv->ch[i];
 619 -
 620 -               if (!IS_RX(i) && !IS_TX(i))
 621 -                       continue;
 622 -               napi_disable(&ch->napi);
 623 -               ltq_dma_close(&ch->dma);
 624 -       }
 625 +       if (dev->phydev)
 626 +               phy_stop(dev->phydev);
 627 +       napi_disable(&priv->txch.napi);
 628 +       napi_disable(&priv->rxch.napi);
 629 +
 630 +       spin_lock_irqsave(&priv->lock, flags);
 631 +       ltq_dma_close(&priv->txch.dma);
 632 +       ltq_dma_close(&priv->rxch.dma);
 633 +       spin_unlock_irqrestore(&priv->lock, flags);
 634 +
 635         return 0;
 636  }
 637
 638 @@ -471,16 +665,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
 639         int queue = skb_get_queue_mapping(skb);
 640         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 641         struct ltq_etop_priv *priv = netdev_priv(dev);
 642 -       struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 643 -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 644 -       int len;
 645 +       struct ltq_dma_desc *desc =
 646 +               &priv->txch.dma.desc_base[priv->txch.dma.desc];
 647         unsigned long flags;
 648         u32 byte_offset;
 649 +       int len;
 650
 651         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 652
 653 -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 654 -               dev_kfree_skb_any(skb);
 655 +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
 656 +                       priv->txch.skb[priv->txch.dma.desc]) {
 657                 netdev_err(dev, "tx ring full\n");
 658                 netif_tx_stop_queue(txq);
 659                 return NETDEV_TX_BUSY;
 660 @@ -488,7 +682,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
 661
 662         /* dma needs to start on a 16 byte aligned address */
 663         byte_offset = CPHYSADDR(skb->data) % 16;
 664 -       ch->skb[ch->dma.desc] = skb;
 665 +       priv->txch.skb[priv->txch.dma.desc] = skb;
 666
 667         netif_trans_update(dev);
 668
 669 @@ -498,11 +692,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
 670         wmb();
 671         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 672                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 673 -       ch->dma.desc++;
 674 -       ch->dma.desc %= LTQ_DESC_NUM;
 675 +       priv->txch.dma.desc++;
 676 +       priv->txch.dma.desc %= LTQ_DESC_NUM;
 677         spin_unlock_irqrestore(&priv->lock, flags);
 678
 679 -       if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 680 +       if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
 681                 netif_tx_stop_queue(txq);
 682
 683         return NETDEV_TX_OK;
 684 @@ -516,8 +710,10 @@ ltq_etop_change_mtu(struct net_device *d
 685
 686         dev->mtu = new_mtu;
 687
 688 +       int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
 689 +
 690         spin_lock_irqsave(&priv->lock, flags);
 691 -       ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
 692 +       ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
 693         spin_unlock_irqrestore(&priv->lock, flags);
 694
 695         return 0;
 696 @@ -577,6 +773,9 @@ ltq_etop_init(struct net_device *dev)
 697         if (err)
 698                 goto err_hw;
 699         ltq_etop_change_mtu(dev, 1500);
 700 +       err = ltq_etop_dma_init(dev);
 701 +       if (err)
 702 +               goto err_hw;
 703
 704         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 705         if (!is_valid_ether_addr(mac.sa_data)) {
 706 @@ -594,9 +793,10 @@ ltq_etop_init(struct net_device *dev)
 707                 dev->addr_assign_type = NET_ADDR_RANDOM;
 708
 709         ltq_etop_set_multicast_list(dev);
 710 -       err = ltq_etop_mdio_init(dev);
 711 -       if (err)
 712 -               goto err_netdev;
 713 +       if (!ltq_etop_mdio_init(dev))
 714 +               dev->ethtool_ops = &ltq_etop_ethtool_ops;
 715 +       else
 716 +               pr_warn("etop: mdio probe failed\n");;
 717         return 0;
 718
 719  err_netdev:
 720 @@ -616,6 +816,9 @@ ltq_etop_tx_timeout(struct net_device *d
 721         err = ltq_etop_hw_init(dev);
 722         if (err)
 723                 goto err_hw;
 724 +       err = ltq_etop_dma_init(dev);
 725 +       if (err)
 726 +               goto err_hw;
 727         netif_trans_update(dev);
 728         netif_wake_queue(dev);
 729         return;
 730 @@ -639,14 +842,19 @@ static const struct net_device_ops ltq_e
 731         .ndo_tx_timeout = ltq_etop_tx_timeout,
 732  };
 733
 734 -static int __init
 735 -ltq_etop_probe(struct platform_device *pdev)
 736 +static int ltq_etop_probe(struct platform_device *pdev)
 737  {
 738         struct net_device *dev;
 739         struct ltq_etop_priv *priv;
 740 -       struct resource *res;
 741 +       struct resource *res, *gbit_res, irqres[2];
 742 +       const u8 *mac;
 743         int err;
 744 -       int i;
 745 +
 746 +       err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
 747 +       if (err != 2) {
 748 +               dev_err(&pdev->dev, "failed to get etop irqs\n");
 749 +               return -EINVAL;
 750 +       }
 751
 752         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 753         if (!res) {
 754 @@ -672,31 +880,62 @@ ltq_etop_probe(struct platform_device *p
 755                 goto err_out;
 756         }
 757
 758 -       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 759 -       if (!dev) {
 760 -               err = -ENOMEM;
 761 -               goto err_out;
 762 +       if (of_machine_is_compatible("lantiq,ar9")) {
 763 +               gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 764 +               if (!gbit_res) {
 765 +                       dev_err(&pdev->dev, "failed to get gbit resource\n");
 766 +                       err = -ENOENT;
 767 +                       goto err_out;
 768 +               }
 769 +               ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
 770 +                       gbit_res->start, resource_size(gbit_res));
 771 +               if (!ltq_gbit_membase) {
 772 +                       dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
 773 +                               pdev->id);
 774 +                       err = -ENOMEM;
 775 +                       goto err_out;
 776 +               }
 777         }
 778 +
 779 +       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 780         strcpy(dev->name, "eth%d");
 781         dev->netdev_ops = &ltq_eth_netdev_ops;
 782 -       dev->ethtool_ops = &ltq_etop_ethtool_ops;
 783         priv = netdev_priv(dev);
 784         priv->res = res;
 785         priv->pdev = pdev;
 786 -       priv->pldata = dev_get_platdata(&pdev->dev);
 787         priv->netdev = dev;
 788 +       priv->tx_irq = irqres[0].start;
 789 +       priv->rx_irq = irqres[1].start;
 790 +       priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
 791 +
 792 +       mac = of_get_mac_address(pdev->dev.of_node);
 793 +       if (mac)
 794 +               memcpy(priv->mac, mac, ETH_ALEN);
 795 +
 796 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 797 +       if (IS_ERR(priv->clk_ppe))
 798 +               return PTR_ERR(priv->clk_ppe);
 799 +       if (of_machine_is_compatible("lantiq,ar9")) {
 800 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 801 +               if (IS_ERR(priv->clk_switch))
 802 +                       return PTR_ERR(priv->clk_switch);
 803 +       }
 804 +       if (of_machine_is_compatible("lantiq,ase")) {
 805 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 806 +               if (IS_ERR(priv->clk_ephy))
 807 +                       return PTR_ERR(priv->clk_ephy);
 808 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 809 +               if (IS_ERR(priv->clk_ephycgu))
 810 +                       return PTR_ERR(priv->clk_ephycgu);
 811 +       }
 812 +
 813         spin_lock_init(&priv->lock);
 814         SET_NETDEV_DEV(dev, &pdev->dev);
 815
 816 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 817 -               if (IS_TX(i))
 818 -                       netif_napi_add(dev, &priv->ch[i].napi,
 819 -                               ltq_etop_poll_tx, 8);
 820 -               else if (IS_RX(i))
 821 -                       netif_napi_add(dev, &priv->ch[i].napi,
 822 -                               ltq_etop_poll_rx, 32);
 823 -               priv->ch[i].netdev = dev;
 824 -       }
 825 +       netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
 826 +       netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
 827 +       priv->txch.netdev = dev;
 828 +       priv->rxch.netdev = dev;
 829
 830         err = register_netdev(dev);
 831         if (err)
 832 @@ -725,31 +964,22 @@ ltq_etop_remove(struct platform_device *
 833         return 0;
 834  }
 835
 836 +static const struct of_device_id ltq_etop_match[] = {
 837 +       { .compatible = "lantiq,etop-xway" },
 838 +       {},
 839 +};
 840 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
 841 +
 842  static struct platform_driver ltq_mii_driver = {
 843 +       .probe = ltq_etop_probe,
 844         .remove = ltq_etop_remove,
 845         .driver = {
 846                 .name = "ltq_etop",
 847 +               .of_match_table = ltq_etop_match,
 848         },
 849  };
 850
 851 -int __init
 852 -init_ltq_etop(void)
 853 -{
 854 -       int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 855 -
 856 -       if (ret)
 857 -               pr_err("ltq_etop: Error registering platform driver!");
 858 -       return ret;
 859 -}
 860 -
 861 -static void __exit
 862 -exit_ltq_etop(void)
 863 -{
 864 -       platform_driver_unregister(&ltq_mii_driver);
 865 -}
 866 -
 867 -module_init(init_ltq_etop);
 868 -module_exit(exit_ltq_etop);
 869 +module_platform_driver(ltq_mii_driver);
 870
 871  MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 872  MODULE_DESCRIPTION("Lantiq SoC ETOP");