1 From db447f1a18106aa4d32438ab72ff57024b34cee4 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 16 Aug 2012 09:57:01 +0200
4 Subject: [PATCH 114/123] SPI: MIPS: lantiq: adds spi-xway
6 This patch adds support for the SPI core found on several Lantiq SoCs.
7 The Driver has been runtime tested in combination with m25p80 Flash Devices
10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
11 Signed-off-by: John Crispin <blogic@openwrt.org>
13 drivers/spi/Kconfig | 8 +
14 drivers/spi/Makefile | 1 +
15 drivers/spi/spi-xway.c | 977 ++++++++++++++++++++++++++++++++++++++++++++++++
16 3 files changed, 986 insertions(+)
17 create mode 100644 drivers/spi/spi-xway.c
19 --- a/drivers/spi/Kconfig
20 +++ b/drivers/spi/Kconfig
21 @@ -443,6 +443,14 @@ config SPI_NUC900
23 SPI driver for Nuvoton NUC900 series ARM SoCs
26 + tristate "Lantiq XWAY SPI controller"
27 + depends on LANTIQ && SOC_TYPE_XWAY
30 + This driver supports the Lantiq SoC SPI controller in master
34 # Add new SPI master controllers in alphabetical order above this line
36 --- a/drivers/spi/Makefile
37 +++ b/drivers/spi/Makefile
38 @@ -67,4 +67,5 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-t
39 obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
40 obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
41 obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
42 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o
45 +++ b/drivers/spi/spi-xway.c
48 + * Lantiq SoC SPI controller
50 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
51 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
53 + * This program is free software; you can distribute it and/or modify it
54 + * under the terms of the GNU General Public License (Version 2) as
55 + * published by the Free Software Foundation.
58 +#include <linux/init.h>
59 +#include <linux/module.h>
60 +#include <linux/workqueue.h>
61 +#include <linux/platform_device.h>
62 +#include <linux/io.h>
63 +#include <linux/sched.h>
64 +#include <linux/delay.h>
65 +#include <linux/interrupt.h>
66 +#include <linux/completion.h>
67 +#include <linux/spinlock.h>
68 +#include <linux/err.h>
69 +#include <linux/clk.h>
70 +#include <linux/spi/spi.h>
71 +#include <linux/spi/spi_bitbang.h>
72 +#include <linux/of_irq.h>
74 +#include <lantiq_soc.h>
76 +#define LTQ_SPI_CLC 0x00 /* Clock control */
77 +#define LTQ_SPI_PISEL 0x04 /* Port input select */
78 +#define LTQ_SPI_ID 0x08 /* Identification */
79 +#define LTQ_SPI_CON 0x10 /* Control */
80 +#define LTQ_SPI_STAT 0x14 /* Status */
81 +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
82 +#define LTQ_SPI_TB 0x20 /* Transmit buffer */
83 +#define LTQ_SPI_RB 0x24 /* Receive buffer */
84 +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
85 +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
86 +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */
87 +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */
88 +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
89 +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */
90 +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
91 +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
92 +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
93 +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
94 +#define LTQ_SPI_RXREQ 0x80 /* Receive request */
95 +#define LTQ_SPI_RXCNT 0x84 /* Receive count */
96 +#define LTQ_SPI_DMACON 0xEC /* DMA control */
97 +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
98 +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
99 +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
101 +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
102 +#define LTQ_SPI_CLC_SMC_MASK 0xFF
103 +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
104 +#define LTQ_SPI_CLC_RMC_MASK 0xFF
105 +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
106 +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
108 +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
109 +#define LTQ_SPI_ID_TXFS_MASK 0x3F
110 +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
111 +#define LTQ_SPI_ID_RXFS_MASK 0x3F
112 +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
113 +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
115 +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
116 +#define LTQ_SPI_CON_BM_MASK 0x1F
117 +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
118 +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
119 +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
120 +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
121 +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
122 +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
123 +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
124 +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
125 +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
126 +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
127 +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
128 +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
129 +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
130 +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
132 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
133 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
134 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
135 +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
136 +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
137 +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
138 +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
139 +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
140 +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
141 +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
143 +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
144 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
145 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
146 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
147 +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error
149 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
150 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
151 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
152 +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
153 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
154 +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
155 +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
156 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
157 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
158 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
159 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
160 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
162 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
163 +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
164 +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
165 +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
167 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
168 +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
169 +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
170 +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
172 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
173 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
174 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
175 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
177 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
178 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
180 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
181 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
183 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
184 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
186 +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
187 +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
188 +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
189 +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
190 +#define LTQ_SPI_IRNEN_ALL 0xF
193 + struct spi_bitbang bitbang;
194 + struct completion done;
197 + struct device *dev;
198 + void __iomem *base;
199 + struct clk *fpiclk;
200 + struct clk *spiclk;
210 + struct spi_transfer *curr_transfer;
212 + u32 (*get_tx) (struct ltq_spi *);
216 + unsigned dma_support:1;
217 + unsigned cfg_mode:1;
220 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
222 + return spi_master_get_devdata(spi->master);
225 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
227 + return ioread32be(hw->base + reg);
230 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
232 + iowrite32be(val, hw->base + reg);
235 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
239 + val = ltq_spi_reg_read(hw, reg);
241 + ltq_spi_reg_write(hw, val, reg);
244 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
248 + val = ltq_spi_reg_read(hw, reg);
250 + ltq_spi_reg_write(hw, val, reg);
253 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
257 + /* Power-up module */
258 + clk_enable(hw->spiclk);
261 + * Set clock divider for run mode to 1 to
262 + * run at same frequency as FPI bus
264 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
265 + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
268 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
270 + /* Set clock divider to 0 and set module disable bit */
271 + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
273 + /* Power-down module */
274 + clk_disable(hw->spiclk);
277 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
282 + * Enable and flush FIFOs. Set interrupt trigger level to
283 + * half of FIFO count implemented in hardware.
285 + if (hw->txfs > 1) {
286 + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
287 + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
288 + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
291 + if (hw->rxfs > 1) {
292 + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
293 + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
294 + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
298 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
301 + unsigned long timeout;
303 + timeout = jiffies + msecs_to_jiffies(200);
306 + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
307 + if (!(stat & LTQ_SPI_STAT_BSY))
311 + } while (!time_after_eq(jiffies, timeout));
313 + dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat);
318 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
324 + * Putting the SPI module in config mode is only safe if no
325 + * transfer is in progress as indicated by busy flag STATE.BSY.
327 + if (ltq_spi_wait_ready(hw)) {
328 + ltq_spi_reset_fifos(hw);
329 + hw->status = -ETIMEDOUT;
331 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
336 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
341 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
346 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
348 + const u8 *tx = hw->tx;
357 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
359 + const u16 *tx = (u16 *) hw->tx;
368 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
370 + const u32 *tx = (u32 *) hw->tx;
379 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
381 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
383 + u8 bits_per_word = spi->bits_per_word;
386 + * Use either default value of SPI device or value
387 + * from current transfer.
389 + if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
390 + bits_per_word = hw->curr_transfer->bits_per_word;
392 + if (bits_per_word <= 8)
393 + hw->get_tx = ltq_spi_tx_word_u8;
394 + else if (bits_per_word <= 16)
395 + hw->get_tx = ltq_spi_tx_word_u16;
396 + else if (bits_per_word <= 32)
397 + hw->get_tx = ltq_spi_tx_word_u32;
399 + /* CON.BM value = bits_per_word - 1 */
400 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
402 + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
403 + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
404 + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
407 +static void ltq_spi_speed_set(struct spi_device *spi)
409 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
410 + u32 br, max_speed_hz, spi_clk;
411 + u32 speed_hz = spi->max_speed_hz;
414 + * Use either default value of SPI device or value
415 + * from current transfer.
417 + if (hw->curr_transfer && hw->curr_transfer->speed_hz)
418 + speed_hz = hw->curr_transfer->speed_hz;
421 + * SPI module clock is derived from FPI bus clock dependent on
422 + * divider value in CLC.RMS which is always set to 1.
424 + spi_clk = clk_get_rate(hw->fpiclk);
427 + * Maximum SPI clock frequency in master mode is half of
428 + * SPI module clock frequency. Maximum reload value of
429 + * baudrate generator BR is 2^16.
431 + max_speed_hz = spi_clk / 2;
432 + if (speed_hz >= max_speed_hz)
435 + br = (max_speed_hz / speed_hz) - 1;
440 + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
443 +static void ltq_spi_clockmode_set(struct spi_device *spi)
445 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
448 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
451 + * SPI mode mapping in CON register:
452 + * Mode CPOL CPHA CON.PO CON.PH
458 + if (spi->mode & SPI_CPHA)
459 + con &= ~LTQ_SPI_CON_PH;
461 + con |= LTQ_SPI_CON_PH;
463 + if (spi->mode & SPI_CPOL)
464 + con |= LTQ_SPI_CON_PO;
466 + con &= ~LTQ_SPI_CON_PO;
468 + /* Set heading control */
469 + if (spi->mode & SPI_LSB_FIRST)
470 + con &= ~LTQ_SPI_CON_HB;
472 + con |= LTQ_SPI_CON_HB;
474 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
477 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
481 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
484 + if (t->tx_buf && t->rx_buf) {
485 + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
486 + } else if (t->rx_buf) {
487 + con &= ~LTQ_SPI_CON_RXOFF;
488 + con |= LTQ_SPI_CON_TXOFF;
489 + } else if (t->tx_buf) {
490 + con &= ~LTQ_SPI_CON_TXOFF;
491 + con |= LTQ_SPI_CON_RXOFF;
494 + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
496 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
499 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
501 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
504 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
505 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
508 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
510 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
513 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
514 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
517 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
519 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
522 + case BITBANG_CS_ACTIVE:
523 + ltq_spi_bits_per_word_set(spi);
524 + ltq_spi_speed_set(spi);
525 + ltq_spi_clockmode_set(spi);
526 + ltq_spi_run_mode_set(hw);
527 + ltq_spi_internal_cs_activate(spi);
530 + case BITBANG_CS_INACTIVE:
531 + ltq_spi_internal_cs_deactivate(spi);
532 + ltq_spi_config_mode_set(hw);
537 +static int ltq_spi_setup_transfer(struct spi_device *spi,
538 + struct spi_transfer *t)
540 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
541 + u8 bits_per_word = spi->bits_per_word;
543 + hw->curr_transfer = t;
545 + if (t && t->bits_per_word)
546 + bits_per_word = t->bits_per_word;
548 + if (bits_per_word > 32)
551 + ltq_spi_config_mode_set(hw);
556 +static int ltq_spi_setup(struct spi_device *spi)
558 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
561 + /* Set default word length to 8 if not set */
562 + if (!spi->bits_per_word)
563 + spi->bits_per_word = 8;
565 + if (spi->bits_per_word > 32)
569 + * Up to six GPIOs can be connected to the SPI module
570 + * via GPIO alternate function to control the chip select lines.
572 + gpocon = (1 << (spi->chip_select +
573 + LTQ_SPI_GPOCON_ISCSBN_SHIFT));
575 + if (spi->mode & SPI_CS_HIGH)
576 + gpocon |= (1 << spi->chip_select);
578 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
580 + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
581 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
586 +static void ltq_spi_cleanup(struct spi_device *spi)
591 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
596 + /* Determine how much FIFOs are free for TX data */
597 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
598 + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
599 + LTQ_SPI_FSTAT_TXFFL_MASK);
604 + while (hw->tx_cnt < hw->len && fifo_space) {
605 + data = hw->get_tx(hw);
606 + ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
611 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
613 + u32 fstat, data, *rx32;
615 + u8 rxbv, shift, *rx8;
617 + /* Determine how much FIFOs are filled with RX data */
618 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
619 + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
620 + & LTQ_SPI_FSTAT_RXFFL_MASK);
626 + * The 32 bit FIFO is always used completely independent from the
627 + * bits_per_word value. Thus four bytes have to be read at once
630 + rx32 = (u32 *) hw->rx;
631 + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
632 + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
639 + * If there are remaining bytes, read byte count from STAT.RXBV
640 + * register and read the data byte-wise.
642 + while (fifo_fill && hw->rx_cnt < hw->len) {
643 + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
644 + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
645 + data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
647 + shift = (rxbv - 1) * 8;
651 + *rx8++ = (data >> shift) & 0xFF;
662 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
664 + u32 rxreq, rxreq_max, rxtodo;
666 + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
669 + * In RX-only mode the serial clock is activated only after writing
670 + * the expected amount of RX bytes into RXREQ register.
671 + * To avoid receive overflows at high clocks it is better to request
672 + * only the amount of bytes that fits into all FIFOs. This value
673 + * depends on the FIFO size implemented in hardware.
675 + rxreq = hw->len - hw->rx_cnt;
676 + rxreq_max = hw->rxfs << 2;
677 + rxreq = min(rxreq_max, rxreq);
679 + if (!rxtodo && rxreq)
680 + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
683 +static inline void ltq_spi_complete(struct ltq_spi *hw)
685 + complete(&hw->done);
688 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
690 + struct ltq_spi *hw = data;
691 + unsigned long flags;
694 + spin_lock_irqsave(&hw->lock, flags);
696 + if (hw->tx_cnt < hw->len)
697 + ltq_spi_txfifo_write(hw);
699 + if (hw->tx_cnt == hw->len)
702 + spin_unlock_irqrestore(&hw->lock, flags);
705 + ltq_spi_complete(hw);
707 + return IRQ_HANDLED;
710 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
712 + struct ltq_spi *hw = data;
713 + unsigned long flags;
716 + spin_lock_irqsave(&hw->lock, flags);
718 + if (hw->rx_cnt < hw->len) {
719 + ltq_spi_rxfifo_read(hw);
721 + if (hw->tx && hw->tx_cnt < hw->len)
722 + ltq_spi_txfifo_write(hw);
725 + if (hw->rx_cnt == hw->len)
728 + ltq_spi_rxreq_set(hw);
730 + spin_unlock_irqrestore(&hw->lock, flags);
733 + ltq_spi_complete(hw);
735 + return IRQ_HANDLED;
738 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
740 + struct ltq_spi *hw = data;
741 + unsigned long flags;
743 + spin_lock_irqsave(&hw->lock, flags);
745 + /* Disable all interrupts */
746 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
748 + /* Clear all error flags */
749 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
752 + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
753 + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
756 + spin_unlock_irqrestore(&hw->lock, flags);
758 + ltq_spi_complete(hw);
760 + return IRQ_HANDLED;
763 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
765 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
768 + hw->tx = t->tx_buf;
769 + hw->rx = t->rx_buf;
774 + INIT_COMPLETION(hw->done);
776 + ltq_spi_xmit_set(hw, t);
778 + /* Enable error interrupts */
779 + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
782 + /* Initially fill TX FIFO with as much data as possible */
783 + ltq_spi_txfifo_write(hw);
784 + irq_flags |= LTQ_SPI_IRNEN_T;
786 + /* Always enable RX interrupt in Full Duplex mode */
788 + irq_flags |= LTQ_SPI_IRNEN_R;
789 + } else if (hw->rx) {
790 + /* Start RX clock */
791 + ltq_spi_rxreq_set(hw);
793 + /* Enable RX interrupt to receive data from RX FIFOs */
794 + irq_flags |= LTQ_SPI_IRNEN_R;
797 + /* Enable TX or RX interrupts */
798 + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
799 + wait_for_completion_interruptible(&hw->done);
801 + /* Disable all interrupts */
802 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
805 + * Return length of current transfer for bitbang utility code if
806 + * no errors occured during transmission.
809 + hw->status = hw->len;
814 +static const struct ltq_spi_irq_map {
816 + irq_handler_t handler;
817 +} ltq_spi_irqs[] = {
818 + { "spi_rx", ltq_spi_rx_irq },
819 + { "spi_tx", ltq_spi_tx_irq },
820 + { "spi_err", ltq_spi_err_irq },
823 +static int __devinit ltq_spi_probe(struct platform_device *pdev)
825 + struct resource irqres[3];
826 + struct spi_master *master;
827 + struct resource *r;
828 + struct ltq_spi *hw;
832 + if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) {
833 + dev_err(&pdev->dev, "IRQ settings missing in device tree\n");
837 + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
839 + dev_err(&pdev->dev, "spi_alloc_master\n");
844 + hw = spi_master_get_devdata(master);
846 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 + dev_err(&pdev->dev, "platform_get_resource\n");
853 + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
856 + dev_err(&pdev->dev, "failed to request memory region\n");
861 + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
863 + dev_err(&pdev->dev, "failed to remap memory region\n");
868 + memset(hw->irq, 0, sizeof(hw->irq));
869 + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
870 + hw->irq[i] = irqres[i].start;
871 + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
872 + 0, ltq_spi_irqs[i].name, hw);
874 + dev_err(&pdev->dev, "failed to request %s irq (%d)\n",
875 + ltq_spi_irqs[i].name, hw->irq[i]);
880 + hw->fpiclk = clk_get_fpi();
881 + if (IS_ERR(hw->fpiclk)) {
882 + dev_err(&pdev->dev, "failed to get fpi clock\n");
883 + ret = PTR_ERR(hw->fpiclk);
887 + hw->spiclk = clk_get(&pdev->dev, NULL);
888 + if (IS_ERR(hw->spiclk)) {
889 + dev_err(&pdev->dev, "failed to get spi clock gate\n");
890 + ret = PTR_ERR(hw->spiclk);
894 + hw->bitbang.master = spi_master_get(master);
895 + hw->bitbang.chipselect = ltq_spi_chipselect;
896 + hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
897 + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
899 + if (of_machine_is_compatible("lantiq,ase"))
900 + master->num_chipselect = 3;
902 + master->num_chipselect = 6;
903 + master->bus_num = pdev->id;
904 + master->setup = ltq_spi_setup;
905 + master->cleanup = ltq_spi_cleanup;
906 + master->dev.of_node = pdev->dev.of_node;
908 + hw->dev = &pdev->dev;
909 + init_completion(&hw->done);
910 + spin_lock_init(&hw->lock);
912 + ltq_spi_hw_enable(hw);
914 + /* Read module capabilities */
915 + id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
916 + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
917 + hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
918 + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
920 + ltq_spi_config_mode_set(hw);
922 + /* Enable error checking, disable TX/RX, set idle value high */
923 + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
924 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
925 + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
926 + ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
928 + /* Enable master mode and clear error flags */
929 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
930 + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
932 + /* Reset GPIO/CS registers */
933 + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
934 + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
936 + /* Enable and flush FIFOs */
937 + ltq_spi_reset_fifos(hw);
939 + ret = spi_bitbang_start(&hw->bitbang);
941 + dev_err(&pdev->dev, "spi_bitbang_start failed\n");
945 + platform_set_drvdata(pdev, hw);
947 + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
948 + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
953 + ltq_spi_hw_disable(hw);
957 + clk_put(hw->fpiclk);
959 + clk_put(hw->spiclk);
962 + clk_put(hw->fpiclk);
965 + free_irq(hw->irq[i], hw);
968 + spi_master_put(master);
974 +static int __devexit ltq_spi_remove(struct platform_device *pdev)
976 + struct ltq_spi *hw = platform_get_drvdata(pdev);
979 + ret = spi_bitbang_stop(&hw->bitbang);
983 + platform_set_drvdata(pdev, NULL);
985 + ltq_spi_config_mode_set(hw);
986 + ltq_spi_hw_disable(hw);
988 + for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
989 + if (0 < hw->irq[i])
990 + free_irq(hw->irq[i], hw);
993 + clk_put(hw->fpiclk);
995 + clk_put(hw->spiclk);
997 + spi_master_put(hw->bitbang.master);
1002 +static const struct of_device_id ltq_spi_match[] = {
1003 + { .compatible = "lantiq,spi-xway" },
1006 +MODULE_DEVICE_TABLE(of, ltq_spi_match);
1008 +static struct platform_driver ltq_spi_driver = {
1009 + .probe = ltq_spi_probe,
1010 + .remove = __devexit_p(ltq_spi_remove),
1012 + .name = "spi-xway",
1013 + .owner = THIS_MODULE,
1014 + .of_match_table = ltq_spi_match,
1018 +module_platform_driver(ltq_spi_driver);
1020 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1021 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1022 +MODULE_LICENSE("GPL");
1023 +MODULE_ALIAS("platform:spi-xway");