1 /******************************************************************************
4 Infineon Technologies AG
5 St. Martin Strasse 53; 81669 Munich, Germany
7 Any use of this Software is subject to the conclusion of a respective
8 License Agreement. Without such a License Agreement no rights to the
11 ******************************************************************************/
16 #define LTQ_BOOT_CPU_OFFSET 0x20
18 #define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
19 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00)
20 #define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
21 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04)
22 #define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
23 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08)
24 #define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
25 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C)
26 #define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
27 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10)
28 #define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
29 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14)
30 #define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
31 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */
32 #define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
33 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */
34 #define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
35 (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C)