1 --- a/arch/arm/mach-ixp4xx/Kconfig
2 +++ b/arch/arm/mach-ixp4xx/Kconfig
3 @@ -21,6 +21,14 @@ config MACH_AVILA
4 Avila Network Platform. For more information on this platform,
5 see <file:Documentation/arm/IXP4xx>.
11 + Say 'Y' here if you want your kernel to support the Gateworks
12 + Cambria series. For more information on this platform,
13 + see <file:Documentation/arm/IXP4xx>.
18 @@ -218,7 +226,7 @@ config CPU_IXP46X
22 - depends on MACH_KIXRP435
23 + depends on MACH_KIXRP435 || MACH_CAMBRIA
27 --- a/arch/arm/mach-ixp4xx/Makefile
28 +++ b/arch/arm/mach-ixp4xx/Makefile
29 @@ -7,6 +7,7 @@ obj-pci-n :=
31 obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
32 obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
33 +obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
34 obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
35 obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
36 obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
37 @@ -31,6 +32,7 @@ obj-y += common.o
39 obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
40 obj-$(CONFIG_MACH_AVILA) += avila-setup.o
41 +obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
42 obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
43 obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
44 obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
46 +++ b/arch/arm/mach-ixp4xx/cambria-pci.c
49 + * arch/arch/mach-ixp4xx/cambria-pci.c
51 + * PCI setup routines for Gateworks Cambria series
53 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
55 + * based on coyote-pci.c:
56 + * Copyright (C) 2002 Jungo Software Technologies.
57 + * Copyright (C) 2003 MontaVista Softwrae, Inc.
59 + * Maintainer: Imre Kaloz <kaloz@openwrt.org>
61 + * This program is free software; you can redistribute it and/or modify
62 + * it under the terms of the GNU General Public License version 2 as
63 + * published by the Free Software Foundation.
67 +#include <linux/kernel.h>
68 +#include <linux/pci.h>
69 +#include <linux/init.h>
70 +#include <linux/irq.h>
72 +#include <asm/mach-types.h>
73 +#include <mach/hardware.h>
76 +#include <asm/mach/pci.h>
78 +extern void ixp4xx_pci_preinit(void);
79 +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
80 +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
82 +void __init cambria_pci_preinit(void)
84 + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
85 + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
86 + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
87 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
89 + ixp4xx_pci_preinit();
92 +static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
95 + return IRQ_IXP4XX_GPIO11;
97 + return IRQ_IXP4XX_GPIO10;
99 + return IRQ_IXP4XX_GPIO9;
100 + else if (slot == 4)
101 + return IRQ_IXP4XX_GPIO8;
102 + else if (slot == 6)
103 + return IRQ_IXP4XX_GPIO10;
104 + else if (slot == 15)
105 + return IRQ_IXP4XX_GPIO8;
110 +struct hw_pci cambria_pci __initdata = {
111 + .nr_controllers = 1,
112 + .preinit = cambria_pci_preinit,
113 + .ops = &ixp4xx_ops,
114 + .setup = ixp4xx_setup,
115 + .map_irq = cambria_map_irq,
118 +int __init cambria_pci_init(void)
120 + if (machine_is_cambria())
121 + pci_common_init(&cambria_pci);
125 +subsys_initcall(cambria_pci_init);
127 +++ b/arch/arm/mach-ixp4xx/cambria-setup.c
130 + * arch/arm/mach-ixp4xx/cambria-setup.c
132 + * Board setup for the Gateworks Cambria series
134 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
135 + * Copyright (C) 2012 Gateworks Corporation <support@gateworks.com>
137 + * based on coyote-setup.c:
138 + * Copyright (C) 2003-2005 MontaVista Software, Inc.
140 + * Author: Imre Kaloz <kaloz@openwrt.org>
141 + * Tim Harvey <tharvey@gateworks.com>
144 +#include <linux/device.h>
145 +#include <linux/gpio_keys.h>
146 +#include <linux/gpio.h>
147 +#include <linux/i2c.h>
148 +#include <linux/i2c-gpio.h>
149 +#include <linux/platform_data/at24.h>
150 +#include <linux/i2c/gw_i2c_pld.h>
151 +#include <linux/platform_data/pca953x.h>
152 +#include <linux/if_ether.h>
153 +#include <linux/init.h>
154 +#include <linux/input.h>
155 +#include <linux/kernel.h>
156 +#include <linux/leds.h>
157 +#include <linux/memory.h>
158 +#include <linux/netdevice.h>
159 +#include <linux/serial.h>
160 +#include <linux/serial_8250.h>
161 +#include <linux/slab.h>
162 +#include <linux/socket.h>
163 +#include <linux/types.h>
164 +#include <linux/tty.h>
165 +#include <linux/irq.h>
166 +#include <linux/usb/ehci_pdriver.h>
168 +#include <mach/hardware.h>
169 +#include <asm/irq.h>
170 +#include <asm/mach-types.h>
171 +#include <asm/mach/arch.h>
172 +#include <asm/mach/flash.h>
173 +#include <asm/setup.h>
175 +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
177 +struct cambria_board_info {
178 + unsigned char *model;
179 + void (*setup)(void);
182 +static struct cambria_board_info *cambria_info __initdata;
184 +static struct flash_platform_data cambria_flash_data = {
185 + .map_name = "cfi_probe",
189 +static struct resource cambria_flash_resource = {
190 + .flags = IORESOURCE_MEM,
193 +static struct platform_device cambria_flash = {
194 + .name = "IXP4XX-Flash",
197 + .platform_data = &cambria_flash_data,
199 + .num_resources = 1,
200 + .resource = &cambria_flash_resource,
203 +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
208 +static struct platform_device cambria_i2c_gpio = {
209 + .name = "i2c-gpio",
212 + .platform_data = &cambria_i2c_gpio_data,
217 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = {
220 + .sda_is_open_drain = 0,
221 + .scl_is_open_drain = 0,
224 +static struct platform_device cambria_i2c_gpio_sfpa = {
225 + .name = "i2c-gpio",
228 + .platform_data = &cambria_i2c_gpio_sfpa_data,
232 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = {
235 + .sda_is_open_drain = 0,
236 + .scl_is_open_drain = 0,
239 +static struct platform_device cambria_i2c_gpio_sfpb = {
240 + .name = "i2c-gpio",
243 + .platform_data = &cambria_i2c_gpio_sfpb_data,
246 +#endif // #ifdef SFP_SERIALID
248 +static struct eth_plat_info cambria_npec_data = {
254 +static struct eth_plat_info cambria_npea_data = {
260 +static struct platform_device cambria_npec_device = {
261 + .name = "ixp4xx_eth",
262 + .id = IXP4XX_ETH_NPEC,
263 + .dev.platform_data = &cambria_npec_data,
264 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
267 +static struct platform_device cambria_npea_device = {
268 + .name = "ixp4xx_eth",
269 + .id = IXP4XX_ETH_NPEA,
270 + .dev.platform_data = &cambria_npea_data,
271 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
274 +static struct resource cambria_uart_resource = {
275 + .start = IXP4XX_UART1_BASE_PHYS,
276 + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
277 + .flags = IORESOURCE_MEM,
280 +static struct plat_serial8250_port cambria_uart_data[] = {
282 + .mapbase = IXP4XX_UART1_BASE_PHYS,
283 + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
284 + .irq = IRQ_IXP4XX_UART1,
285 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
286 + .iotype = UPIO_MEM,
288 + .uartclk = IXP4XX_UART_XTAL,
293 +static struct platform_device cambria_uart = {
294 + .name = "serial8250",
295 + .id = PLAT8250_DEV_PLATFORM,
297 + .platform_data = cambria_uart_data,
299 + .num_resources = 1,
300 + .resource = &cambria_uart_resource,
303 +static struct resource cambria_optional_uart_resources[] = {
305 + .start = 0x52000000,
307 + .flags = IORESOURCE_MEM
310 + .start = 0x53000000,
312 + .flags = IORESOURCE_MEM
315 + .start = 0x52000000,
317 + .flags = IORESOURCE_MEM
320 + .start = 0x52000000,
322 + .flags = IORESOURCE_MEM
325 + .start = 0x52000000,
327 + .flags = IORESOURCE_MEM
330 + .start = 0x52000000,
332 + .flags = IORESOURCE_MEM
335 + .start = 0x52000000,
337 + .flags = IORESOURCE_MEM
340 + .start = 0x53000000,
342 + .flags = IORESOURCE_MEM
346 +static struct plat_serial8250_port cambria_optional_uart_data[] = {
348 + .flags = UPF_BOOT_AUTOCONF,
349 + .iotype = UPIO_MEM_DELAY,
351 + .uartclk = 1843200,
355 + .flags = UPF_BOOT_AUTOCONF,
356 + .iotype = UPIO_MEM_DELAY,
358 + .uartclk = 1843200,
362 + .flags = UPF_BOOT_AUTOCONF,
363 + .iotype = UPIO_MEM,
365 + .uartclk = 18432000,
368 + .flags = UPF_BOOT_AUTOCONF,
369 + .iotype = UPIO_MEM,
371 + .uartclk = 18432000,
374 + .flags = UPF_BOOT_AUTOCONF,
375 + .iotype = UPIO_MEM,
377 + .uartclk = 18432000,
380 + .flags = UPF_BOOT_AUTOCONF,
381 + .iotype = UPIO_MEM,
383 + .uartclk = 18432000,
386 + .flags = UPF_BOOT_AUTOCONF,
387 + .iotype = UPIO_MEM,
389 + .uartclk = 18432000,
394 +static struct platform_device cambria_optional_uart = {
395 + .name = "serial8250",
396 + .id = PLAT8250_DEV_PLATFORM1,
397 + .dev.platform_data = cambria_optional_uart_data,
398 + .num_resources = 2,
399 + .resource = cambria_optional_uart_resources,
402 +static struct resource cambria_pata_resources[] = {
404 + .flags = IORESOURCE_MEM
407 + .flags = IORESOURCE_MEM,
411 + .start = IRQ_IXP4XX_GPIO12,
412 + .end = IRQ_IXP4XX_GPIO12,
413 + .flags = IORESOURCE_IRQ,
417 +static struct ixp4xx_pata_data cambria_pata_data = {
418 + .cs0_bits = 0xbfff3c03,
419 + .cs1_bits = 0xbfff3c03,
422 +static struct platform_device cambria_pata = {
423 + .name = "pata_ixp4xx_cf",
425 + .dev.platform_data = &cambria_pata_data,
426 + .num_resources = ARRAY_SIZE(cambria_pata_resources),
427 + .resource = cambria_pata_resources,
430 +static struct gpio_led cambria_gpio_leds[] = {
453 +static struct gpio_led_platform_data cambria_gpio_leds_data = {
455 + .leds = cambria_gpio_leds,
458 +static struct platform_device cambria_gpio_leds_device = {
459 + .name = "leds-gpio",
461 + .dev.platform_data = &cambria_gpio_leds_data,
464 +static struct resource cambria_gpio_resources[] = {
471 +static struct gpio cambria_gpios_gw2350[] = {
473 +#if 0 // configured from bootloader
474 + { 0, GPIOF_IN, "ARM_DIO0" },
475 + { 1, GPIOF_IN, "ARM_DIO1" },
476 + { 2, GPIOF_IN, "ARM_DIO2" },
477 + { 3, GPIOF_IN, "ARM_DIO3" },
478 + { 4, GPIOF_IN, "ARM_DIO4" },
479 + { 5, GPIOF_IN, "ARM_DIO5" },
480 + { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" },
482 + { 8, GPIOF_IN, "ARM_DIO8" },
483 + { 9, GPIOF_IN, "ARM_DIO9" },
486 +static struct gpio cambria_gpios_gw2358[] = {
488 +#if 0 // configured from bootloader
489 + { 0, GPIOF_IN, "*VINLOW#" },
490 + { 2, GPIOF_IN, "*GPS_PPS" },
491 + { 3, GPIOF_IN, "*GPS_IRQ#" },
492 + { 4, GPIOF_IN, "*RS485_IRQ#" },
493 + { 5, GPIOF_IN, "*SER_EN#" },
494 + { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
498 +static struct gpio cambria_gpios_gw2359[] = {
500 +#if 0 // configured from bootloader
501 + { 0, GPIOF_IN, "*PCA_IRQ#" },
502 + { 1, GPIOF_IN, "ARM_DIO1" },
503 + { 2, GPIOF_IN, "ARM_DIO2" },
504 + { 3, GPIOF_IN, "ARM_DIO3" },
505 + { 4, GPIOF_IN, "ARM_DIO4" },
506 + { 5, GPIOF_IN, "ARM_DIO5" },
507 + { 8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
509 + { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN" }, // console serial enable
510 + { 12, GPIOF_IN, "*GSC_IRQ#" },
511 + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
513 +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
514 + {100, GPIOF_IN, "*USER_PB#" },
516 + {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" }, // 5V aux supply enable
517 + {108, GPIOF_IN, "*SMUXDA0" },
518 + {109, GPIOF_IN, "*SMUXDA1" },
519 + {110, GPIOF_IN, "*SMUXDA2" },
520 + {111, GPIOF_IN, "*SMUXDB0" },
521 + {112, GPIOF_IN, "*SMUXDB1" },
522 + {113, GPIOF_IN, "*SMUXDB2" },
524 + {118, GPIOF_IN, "*USIM2_DET#"}, // USIM2 Detect
525 + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCI, 0=FP)
526 + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCI, 0=FP)
527 + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect
528 + {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" }, // J21/J10
529 + {124, GPIOF_IN, "*COM1_DSR#" }, // J21/J10
530 + {127, GPIOF_IN, "PCA_DIO0" },
531 + {128, GPIOF_IN, "PCA_DIO1" },
532 + {129, GPIOF_IN, "PCA_DIO2" },
533 + {130, GPIOF_IN, "PCA_DIO3" },
534 + {131, GPIOF_IN, "PCA_DIO4" },
537 +static struct gpio cambria_gpios_gw2360[] = {
539 + { 0, GPIOF_IN, "*PCA_IRQ#" },
540 + { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" },
541 + { 12, GPIOF_IN, "*GSC_IRQ#" },
542 + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
544 +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
545 + {100, GPIOF_IN, "*USER_PB#" },
547 + {108, GPIOF_OUT_INIT_LOW, "*ENET1_EN#" }, // ENET1 TX Enable
548 + {109, GPIOF_IN, "*ENET1_PRES#" }, // ENET1 Detect (0=SFP present)
549 + {110, GPIOF_OUT_INIT_LOW, "*ENET2_EN#" }, // ENET2 TX Enable
550 + {111, GPIOF_IN, "*ENET2_PRES#"}, // ENET2 Detect (0=SFP present)
552 + {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"}, // USIM2 Select (1=Loc, 0=Rem)
553 + {117, GPIOF_IN, "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot)
554 + {118, GPIOF_IN, "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot)
555 + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCIe1, 0=J1)
556 + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCIe2, 0=J1)
557 + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect
558 + {127, GPIOF_IN, "DIO0" },
559 + {128, GPIOF_IN, "DIO1" },
560 + {129, GPIOF_IN, "DIO2" },
561 + {130, GPIOF_IN, "DIO3" },
562 + {131, GPIOF_IN, "DIO4" },
565 +static struct latch_led cambria_latch_leds[] = {
567 + .name = "ledA", /* green led */
571 + .name = "ledB", /* green led */
575 + .name = "ledC", /* green led */
579 + .name = "ledD", /* green led */
583 + .name = "ledE", /* green led */
587 + .name = "ledF", /* green led */
591 + .name = "ledG", /* green led */
595 + .name = "ledH", /* green led */
600 +static struct latch_led_platform_data cambria_latch_leds_data = {
602 + .leds = cambria_latch_leds,
606 +static struct platform_device cambria_latch_leds_device = {
607 + .name = "leds-latch",
609 + .dev.platform_data = &cambria_latch_leds_data,
612 +static struct resource cambria_usb0_resources[] = {
614 + .start = 0xCD000000,
616 + .flags = IORESOURCE_MEM,
620 + .flags = IORESOURCE_IRQ,
624 +static struct resource cambria_usb1_resources[] = {
626 + .start = 0xCE000000,
628 + .flags = IORESOURCE_MEM,
632 + .flags = IORESOURCE_IRQ,
636 +static u64 ehci_dma_mask = ~(u32)0;
638 +static struct usb_ehci_pdata cambria_usb_pdata = {
639 + .big_endian_desc = 1,
640 + .big_endian_mmio = 1,
642 + .caps_offset = 0x100,
645 +static struct platform_device cambria_usb0_device = {
646 + .name = "ehci-platform",
648 + .resource = cambria_usb0_resources,
649 + .num_resources = ARRAY_SIZE(cambria_usb0_resources),
651 + .dma_mask = &ehci_dma_mask,
652 + .coherent_dma_mask = 0xffffffff,
653 + .platform_data = &cambria_usb_pdata,
657 +static struct platform_device cambria_usb1_device = {
658 + .name = "ehci-platform",
660 + .resource = cambria_usb1_resources,
661 + .num_resources = ARRAY_SIZE(cambria_usb1_resources),
663 + .dma_mask = &ehci_dma_mask,
664 + .coherent_dma_mask = 0xffffffff,
665 + .platform_data = &cambria_usb_pdata,
669 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = {
674 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = {
680 +static struct gpio_keys_button cambria_gpio_buttons[] = {
685 + .debounce_interval = 6,
690 +static struct gpio_keys_platform_data cambria_gpio_buttons_data = {
691 + .poll_interval = 500,
693 + .buttons = cambria_gpio_buttons,
696 +static struct platform_device cambria_gpio_buttons_device = {
697 + .name = "gpio-keys-polled",
699 + .dev.platform_data = &cambria_gpio_buttons_data,
702 +static struct platform_device *cambria_devices[] __initdata = {
708 +static int cambria_register_gpio(struct gpio *array, size_t num)
713 + for (i = 0; i < num; i++, array++) {
714 + const char *label = array->label;
715 + if (label[0] == '*')
717 + err = gpio_request_one(array->gpio, array->flags, label);
721 + err = gpio_export(array->gpio, array->label[0] != '*');
727 +static void __init cambria_gw23xx_setup(void)
729 + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
730 + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
731 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
733 + platform_device_register(&cambria_npec_device);
734 + platform_device_register(&cambria_npea_device);
737 +static void __init cambria_gw2350_setup(void)
739 + *IXP4XX_EXP_CS2 = 0xBFFF3C43;
740 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
741 + cambria_optional_uart_data[0].mapbase = 0x52FF0000;
742 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
743 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
745 + *IXP4XX_EXP_CS3 = 0xBFFF3C43;
746 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
747 + cambria_optional_uart_data[1].mapbase = 0x53FF0000;
748 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
749 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
751 + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
752 + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
753 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
755 + platform_device_register(&cambria_optional_uart);
756 + platform_device_register(&cambria_npec_device);
757 + platform_device_register(&cambria_npea_device);
759 + platform_device_register(&cambria_usb0_device);
760 + platform_device_register(&cambria_usb1_device);
762 + platform_device_register(&cambria_gpio_leds_device);
764 + /* gpio config (/sys/class/gpio) */
765 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350));
768 +static void __init cambria_gw2358_setup(void)
770 + *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus
771 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
772 + cambria_optional_uart_data[0].mapbase = 0x53FC0000;
773 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
774 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
776 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
777 + cambria_optional_uart_data[1].mapbase = 0x53F80000;
778 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
779 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
781 + cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\
782 + (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25);
783 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
785 + platform_device_register(&cambria_optional_uart);
787 + platform_device_register(&cambria_npec_device);
788 + platform_device_register(&cambria_npea_device);
790 + platform_device_register(&cambria_usb0_device);
791 + platform_device_register(&cambria_usb1_device);
793 + platform_device_register(&cambria_pata);
795 + cambria_gpio_leds[0].gpio = 24;
796 + platform_device_register(&cambria_gpio_leds_device);
798 + platform_device_register(&cambria_latch_leds_device);
800 + platform_device_register(&cambria_gpio_buttons_device);
802 + /* gpio config (/sys/class/gpio) */
803 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358));
806 +static void __init cambria_gw2359_setup(void)
808 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
809 + /* The mvswitch driver has some hard-coded values which could
810 + * easily be turned into a platform resource if needed. For now they
811 + * match our hardware configuration:
812 + * MV_BASE 0x10 - phy base address
813 + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
814 + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
816 + * The mvswitch driver registers a fixup which forces a driver match
817 + * if phy_addr matches MV_BASE
819 + * Two static defautl VLAN's are created: WAN port in 1, and all other ports
822 + cambria_npea_data.phy = 0x10; // mvswitch driver catches this
824 + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver
825 + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
826 + // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14
827 + cambria_npec_data.phy = 0x14;
829 + platform_device_register(&cambria_npec_device);
830 + platform_device_register(&cambria_npea_device);
832 + platform_device_register(&cambria_usb0_device);
833 + platform_device_register(&cambria_usb1_device);
835 + cambria_gpio_leds_data.num_leds = 3;
836 + cambria_gpio_leds[0].name = "user1";
837 + cambria_gpio_leds[0].gpio = 125; // PNLLED1#
838 + cambria_gpio_leds[1].gpio = 126; // PNLLED3#
839 + cambria_gpio_leds[2].gpio = 119; // PNLLED4#
840 + platform_device_register(&cambria_gpio_leds_device);
842 +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
843 + cambria_gpio_buttons[0].gpio = 100;
844 + platform_device_register(&cambria_gpio_buttons_device);
847 + /* gpio config (/sys/class/gpio) */
848 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359));
851 +static void __init cambria_gw2360_setup(void)
853 + /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART.
854 + * The chip-selects are expanded via a 3-to-8 decoder and CS2
855 + * and they are 8bit devices
857 + *IXP4XX_EXP_CS2 = 0xBFFF3C43;
858 + cambria_optional_uart_data[0].mapbase = 0x52000000;
859 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff);
860 + cambria_optional_uart_data[0].uartclk = 18432000;
861 + cambria_optional_uart_data[0].iotype = UPIO_MEM;
862 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2;
863 + irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING);
865 + cambria_optional_uart_data[1].mapbase = 0x52000008;
866 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff);
867 + cambria_optional_uart_data[1].uartclk = 18432000;
868 + cambria_optional_uart_data[1].iotype = UPIO_MEM;
869 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3;
870 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
872 + cambria_optional_uart_data[2].mapbase = 0x52000010;
873 + cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff);
874 + cambria_optional_uart_data[2].uartclk = 18432000;
875 + cambria_optional_uart_data[2].iotype = UPIO_MEM;
876 + cambria_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO4;
877 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
879 + cambria_optional_uart_data[3].mapbase = 0x52000018;
880 + cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff);
881 + cambria_optional_uart_data[3].uartclk = 18432000;
882 + cambria_optional_uart_data[3].iotype = UPIO_MEM;
883 + cambria_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO5;
884 + irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING);
886 + cambria_optional_uart_data[4].mapbase = 0x52000020;
887 + cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff);
888 + cambria_optional_uart_data[4].uartclk = 18432000;
889 + cambria_optional_uart_data[4].iotype = UPIO_MEM;
890 + cambria_optional_uart_data[4].irq = IRQ_IXP4XX_GPIO8;
891 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING);
893 + cambria_optional_uart_data[5].mapbase = 0x52000028;
894 + cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff);
895 + cambria_optional_uart_data[5].uartclk = 18432000;
896 + cambria_optional_uart_data[5].iotype = UPIO_MEM;
897 + cambria_optional_uart_data[5].irq = IRQ_IXP4XX_GPIO9;
898 + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING);
900 + cambria_optional_uart_data[6].mapbase = 0x52000030;
901 + cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff);
902 + cambria_optional_uart_data[6].uartclk = 18432000;
903 + cambria_optional_uart_data[6].iotype = UPIO_MEM;
904 + cambria_optional_uart_data[6].irq = IRQ_IXP4XX_GPIO10;
905 + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING);
907 + cambria_optional_uart.num_resources = 7,
908 + platform_device_register(&cambria_optional_uart);
910 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
911 + /* The mvswitch driver has some hard-coded values which could
912 + * easily be turned into a platform resource if needed. For now they
913 + * match our hardware configuration:
914 + * MV_BASE 0x10 - phy base address
915 + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
916 + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
918 + * The mvswitch driver registers a fixup which forces a driver match
919 + * if phy_addr matches MV_BASE
921 + * Two static defautl VLAN's are created: WAN port in 1, and all other ports
924 + cambria_npea_data.phy = 0x10; // mvswitch driver catches this
926 + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver
927 + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
930 + // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX
931 + //cambria_npec_data.noautoneg = 1; // disable autoneg
932 + cambria_npec_data.speed_10 = 0; // 100mbps
933 + cambria_npec_data.half_duplex = 0; // full-duplex
934 + platform_device_register(&cambria_npec_device);
935 + platform_device_register(&cambria_npea_device);
937 + platform_device_register(&cambria_usb0_device);
938 + platform_device_register(&cambria_usb1_device);
940 + cambria_gpio_leds_data.num_leds = 3;
941 + cambria_gpio_leds[0].name = "user1";
942 + cambria_gpio_leds[0].gpio = 125;
943 + cambria_gpio_leds[1].gpio = 126;
944 + cambria_gpio_leds[2].gpio = 119;
945 + platform_device_register(&cambria_gpio_leds_device);
947 +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
948 + cambria_gpio_buttons[0].gpio = 100;
949 + platform_device_register(&cambria_gpio_buttons_device);
953 + /* the SFP modules each have an i2c bus for serial ident via GSC GPIO
954 + * To use these the i2c-gpio driver must be changed to use the _cansleep
955 + * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't
956 + * use that anyway as it doesn't operate in an IRQ context).
957 + * Additionally the i2c-gpio module must set the gpio to output-high prior
958 + * to changing direction to an input to enable internal Pullups
960 + platform_device_register(&cambria_i2c_gpio_sfpa);
961 + platform_device_register(&cambria_i2c_gpio_sfpb);
964 + /* gpio config (/sys/class/gpio) */
965 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360));
968 +static struct cambria_board_info cambria_boards[] __initdata = {
971 + .setup = cambria_gw2350_setup,
974 + .setup = cambria_gw2350_setup,
977 + .setup = cambria_gw2358_setup,
980 + .setup = cambria_gw2359_setup,
983 + .setup = cambria_gw2360_setup,
986 + .setup = cambria_gw2358_setup,
990 +static struct cambria_board_info * __init cambria_find_board_info(char *model)
995 + for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
996 + struct cambria_board_info *info = &cambria_boards[i];
997 + if (strcmp(info->model, model) == 0)
1004 +static struct nvmem_device *at24_nvmem;
1006 +static void at24_setup(struct nvmem_device *mem_acc, void *context)
1008 + char mac_addr[ETH_ALEN];
1011 + at24_nvmem = mem_acc;
1013 + /* Read MAC addresses */
1014 + if (nvmem_device_read(at24_nvmem, 0x0, 6, mac_addr) == 6) {
1015 + memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN);
1017 + if (nvmem_device_read(at24_nvmem, 0x6, 6, mac_addr) == 6) {
1018 + memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN);
1021 + /* Read the first 6 bytes of the model number */
1022 + if (nvmem_device_read(at24_nvmem, 0x20, 6, model) == 6) {
1023 + cambria_info = cambria_find_board_info(model);
1028 +static struct at24_platform_data cambria_eeprom_info = {
1031 + .flags = AT24_FLAG_READONLY,
1032 + .setup = at24_setup,
1035 +static struct pca953x_platform_data cambria_pca_data = {
1040 +static struct pca953x_platform_data cambria_pca2_data = {
1045 +static struct i2c_board_info __initdata cambria_i2c_board_info[] = {
1047 + I2C_BOARD_INFO("pca9555", 0x23),
1048 + .platform_data = &cambria_pca_data,
1051 + I2C_BOARD_INFO("pca9555", 0x27),
1052 + .platform_data = &cambria_pca2_data,
1055 + I2C_BOARD_INFO("ds1672", 0x68),
1058 + I2C_BOARD_INFO("gsp", 0x29),
1061 + I2C_BOARD_INFO("ad7418", 0x28),
1064 + I2C_BOARD_INFO("24c08", 0x51),
1065 + .platform_data = &cambria_eeprom_info
1068 + I2C_BOARD_INFO("gw_i2c_pld", 0x56),
1069 + .platform_data = &gw_i2c_pld_data0,
1072 + I2C_BOARD_INFO("gw_i2c_pld", 0x57),
1073 + .platform_data = &gw_i2c_pld_data1,
1077 +static void __init cambria_init(void)
1079 + ixp4xx_sys_init();
1081 + cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
1082 + cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
1084 + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable
1085 + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
1087 + platform_add_devices(ARRAY_AND_SIZE(cambria_devices));
1089 + cambria_pata_resources[0].start = 0x53e00000;
1090 + cambria_pata_resources[0].end = 0x53e3ffff;
1092 + cambria_pata_resources[1].start = 0x53e40000;
1093 + cambria_pata_resources[1].end = 0x53e7ffff;
1095 + cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
1096 + cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
1098 + i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info));
1101 +static int __init cambria_model_setup(void)
1103 + if (!machine_is_cambria())
1106 + if (cambria_info) {
1107 + printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
1108 + cambria_info->model);
1109 + cambria_info->setup();
1111 + printk(KERN_INFO "Unknown/missing Cambria model number"
1112 + " -- defaults will be used\n");
1113 + cambria_gw23xx_setup();
1118 +late_initcall(cambria_model_setup);
1120 +MACHINE_START(CAMBRIA, "Gateworks Cambria series")
1121 + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
1122 + .map_io = ixp4xx_map_io,
1123 + .init_irq = ixp4xx_init_irq,
1124 + .init_time = ixp4xx_timer_init,
1125 + .atag_offset = 0x0100,
1126 + .init_machine = cambria_init,
1127 +#if defined(CONFIG_PCI)
1128 + .dma_zone_size = SZ_64M,
1130 + .restart = ixp4xx_restart,