target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch

   1 From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Thu, 17 Mar 2016 16:22:28 -0500
   4 Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
   5
   6 This adds the SoC nodes to the ipq4019 device tree and
   7 enable it for the DK01.1 board.
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  11 ---
  12 Changes:
  13         - replaced space with tab
  14         - added sleep and mock_utmi clocks
  15         - added registers for usb2 and usb3 parent node
  16         - changed compatible to qca,ipa4019-dwc3
  17         - updated usb2 and usb3 names
  18           (included the reg - in case they become necessary later)
  19 ---
  20  arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
  21  arch/arm/boot/dts/qcom-ipq4019.dtsi           | 71 +++++++++++++++++++++++++++
  22  2 files changed, 91 insertions(+)
  23
  24 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  25 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  26 @@ -108,5 +108,25 @@
  27                 watchdog@b017000 {
  28                         status = "ok";
  29                 };
  30 +
  31 +               usb3_ss_phy: ssphy@9a000 {
  32 +                       status = "ok";
  33 +               };
  34 +
  35 +               usb3_hs_phy: hsphy@a6000 {
  36 +                       status = "ok";
  37 +               };
  38 +
  39 +               usb3: usb3@8af8800 {
  40 +                       status = "ok";
  41 +               };
  42 +
  43 +               usb2_hs_phy: hsphy@a8000 {
  44 +                       status = "ok";
  45 +               };
  46 +
  47 +               usb2: usb2@60f8800 {
  48 +                       status = "ok";
  49 +               };
  50         };
  51  };
  52 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  53 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  54 @@ -307,5 +307,76 @@
  55                         compatible = "qcom,pshold";
  56                         reg = <0x4ab000 0x4>;
  57                 };
  58 +
  59 +               usb3_ss_phy: ssphy@9a000 {
  60 +                       compatible = "qca,uni-ssphy";
  61 +                       reg = <0x9a000 0x800>;
  62 +                       reg-names = "phy_base";
  63 +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
  64 +                       reset-names = "por_rst";
  65 +                       status = "disabled";
  66 +               };
  67 +
  68 +               usb3_hs_phy: hsphy@a6000 {
  69 +                       compatible = "qca,baldur-usb3-hsphy";
  70 +                       reg = <0xa6000 0x40>;
  71 +                       reg-names = "phy_base";
  72 +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
  73 +                       reset-names = "por_rst", "srif_rst";
  74 +                       status = "disabled";
  75 +               };
  76 +
  77 +               usb3@8af8800 {
  78 +                       compatible = "qca,ipq4019-dwc3";
  79 +                       reg = <0x8af8800 0x100>;
  80 +                       #address-cells = <1>;
  81 +                       #size-cells = <1>;
  82 +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
  83 +                                <&gcc GCC_USB3_SLEEP_CLK>,
  84 +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
  85 +                       clock-names = "master", "sleep", "mock_utmi";
  86 +                       ranges;
  87 +                       status = "disabled";
  88 +
  89 +                       dwc3@8a00000 {
  90 +                               compatible = "snps,dwc3";
  91 +                               reg = <0x8a00000 0xf8000>;
  92 +                               interrupts = <0 132 0>;
  93 +                               usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
  94 +                               phy-names = "usb2-phy", "usb3-phy";
  95 +                               dr_mode = "host";
  96 +                       };
  97 +               };
  98 +
  99 +               usb2_hs_phy: hsphy@a8000 {
 100 +                       compatible = "qca,baldur-usb2-hsphy";
 101 +                       reg = <0xa8000 0x40>;
 102 +                       reg-names = "phy_base";
 103 +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
 104 +                       reset-names = "por_rst", "srif_rst";
 105 +                       status = "disabled";
 106 +               };
 107 +
 108 +               usb2@60f8800 {
 109 +                       compatible = "qca,ipq4019-dwc3";
 110 +                       reg = <0x60f8800 0x100>;
 111 +                       #address-cells = <1>;
 112 +                       #size-cells = <1>;
 113 +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
 114 +                                <&gcc GCC_USB2_SLEEP_CLK>,
 115 +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
 116 +                       clock-names = "master", "sleep", "mock_utmi";
 117 +                       ranges;
 118 +                       status = "disabled";
 119 +
 120 +                       dwc3@6000000 {
 121 +                               compatible = "snps,dwc3";
 122 +                               reg = <0x6000000 0xf8000>;
 123 +                               interrupts = <0 136 0>;
 124 +                               usb-phy = <&usb2_hs_phy>;
 125 +                               phy-names = "usb2-phy";
 126 +                               dr_mode = "host";
 127 +                       };
 128 +               };
 129         };
 130  };