target/linux/ipq806x/patches-4.9/0039-clk-qcom-Add-HFPLL-driver.patch

   1 From 23f680d03e5894f494572a5162d21328bd86890c Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:25 -0700
   4 Subject: [PATCH 39/69] clk: qcom: Add HFPLL driver
   5
   6 On some devices (MSM8974 for example), the HFPLLs are
   7 instantiated within the Krait processor subsystem as separate
   8 register regions. Add a driver for these PLLs so that we can
   9 provide HFPLL clocks for use by the system.
  10
  11 Cc: <devicetree@vger.kernel.org>
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
  14 ---
  15  .../devicetree/bindings/clock/qcom,hfpll.txt       |  40 ++++++++
  16  drivers/clk/qcom/Kconfig                           |   8 ++
  17  drivers/clk/qcom/Makefile                          |   1 +
  18  drivers/clk/qcom/hfpll.c                           | 106 +++++++++++++++++++++
  19  4 files changed, 155 insertions(+)
  20  create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  21  create mode 100644 drivers/clk/qcom/hfpll.c
  22
  23 --- /dev/null
  24 +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  25 @@ -0,0 +1,40 @@
  26 +High-Frequency PLL (HFPLL)
  27 +
  28 +PROPERTIES
  29 +
  30 +- compatible:
  31 +       Usage: required
  32 +       Value type: <string>
  33 +       Definition: must be "qcom,hfpll"
  34 +
  35 +- reg:
  36 +       Usage: required
  37 +       Value type: <prop-encoded-array>
  38 +       Definition: address and size of HPLL registers. An optional second
  39 +                   element specifies the address and size of the alias
  40 +                   register region.
  41 +
  42 +- clock-output-names:
  43 +       Usage: required
  44 +       Value type: <string>
  45 +       Definition: Name of the PLL. Typically hfpllX where X is a CPU number
  46 +                   starting at 0. Otherwise hfpll_Y where Y is more specific
  47 +                   such as "l2".
  48 +
  49 +Example:
  50 +
  51 +1) An HFPLL for the L2 cache.
  52 +
  53 +       clock-controller@f9016000 {
  54 +               compatible = "qcom,hfpll";
  55 +               reg = <0xf9016000 0x30>;
  56 +               clock-output-names = "hfpll_l2";
  57 +       };
  58 +
  59 +2) An HFPLL for CPU0. This HFPLL has the alias register region.
  60 +
  61 +       clock-controller@f908a000 {
  62 +               compatible = "qcom,hfpll";
  63 +               reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
  64 +               clock-output-names = "hfpll0";
  65 +       };
  66 --- a/drivers/clk/qcom/Kconfig
  67 +++ b/drivers/clk/qcom/Kconfig
  68 @@ -179,3 +179,11 @@ config MSM_MMCC_8996
  69           Support for the multimedia clock controller on msm8996 devices.
  70           Say Y if you want to support multimedia devices such as display,
  71           graphics, video encode/decode, camera, etc.
  72 +
  73 +config QCOM_HFPLL
  74 +       tristate "High-Frequency PLL (HFPLL) Clock Controller"
  75 +       depends on COMMON_CLK_QCOM
  76 +       help
  77 +         Support for the high-frequency PLLs present on Qualcomm devices.
  78 +         Say Y if you want to support CPU frequency scaling on devices
  79 +         such as MSM8974, APQ8084, etc.
  80 --- a/drivers/clk/qcom/Makefile
  81 +++ b/drivers/clk/qcom/Makefile
  82 @@ -32,3 +32,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8
  83  obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
  84  obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
  85  obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
  86 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  87 --- /dev/null
  88 +++ b/drivers/clk/qcom/hfpll.c
  89 @@ -0,0 +1,106 @@
  90 +/*
  91 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  92 + *
  93 + * This program is free software; you can redistribute it and/or modify
  94 + * it under the terms of the GNU General Public License version 2 and
  95 + * only version 2 as published by the Free Software Foundation.
  96 + *
  97 + * This program is distributed in the hope that it will be useful,
  98 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  99 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 100 + * GNU General Public License for more details.
 101 + */
 102 +
 103 +#include <linux/kernel.h>
 104 +#include <linux/init.h>
 105 +#include <linux/module.h>
 106 +#include <linux/platform_device.h>
 107 +#include <linux/of.h>
 108 +#include <linux/clk.h>
 109 +#include <linux/clk-provider.h>
 110 +#include <linux/regmap.h>
 111 +
 112 +#include "clk-regmap.h"
 113 +#include "clk-hfpll.h"
 114 +
 115 +static const struct hfpll_data hdata = {
 116 +       .mode_reg = 0x00,
 117 +       .l_reg = 0x04,
 118 +       .m_reg = 0x08,
 119 +       .n_reg = 0x0c,
 120 +       .user_reg = 0x10,
 121 +       .config_reg = 0x14,
 122 +       .config_val = 0x430405d,
 123 +       .status_reg = 0x1c,
 124 +       .lock_bit = 16,
 125 +
 126 +       .user_val = 0x8,
 127 +       .user_vco_mask = 0x100000,
 128 +       .low_vco_max_rate = 1248000000,
 129 +       .min_rate = 537600000UL,
 130 +       .max_rate = 2900000000UL,
 131 +};
 132 +
 133 +static const struct of_device_id qcom_hfpll_match_table[] = {
 134 +       { .compatible = "qcom,hfpll" },
 135 +       { }
 136 +};
 137 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
 138 +
 139 +static const struct regmap_config hfpll_regmap_config = {
 140 +       .reg_bits       = 32,
 141 +       .reg_stride     = 4,
 142 +       .val_bits       = 32,
 143 +       .max_register   = 0x30,
 144 +       .fast_io        = true,
 145 +};
 146 +
 147 +static int qcom_hfpll_probe(struct platform_device *pdev)
 148 +{
 149 +       struct resource *res;
 150 +       struct device *dev = &pdev->dev;
 151 +       void __iomem *base;
 152 +       struct regmap *regmap;
 153 +       struct clk_hfpll *h;
 154 +       struct clk_init_data init = {
 155 +               .parent_names = (const char *[]){ "xo" },
 156 +               .num_parents = 1,
 157 +               .ops = &clk_ops_hfpll,
 158 +       };
 159 +
 160 +       h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
 161 +       if (!h)
 162 +               return -ENOMEM;
 163 +
 164 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 165 +       base = devm_ioremap_resource(dev, res);
 166 +       if (IS_ERR(base))
 167 +               return PTR_ERR(base);
 168 +
 169 +       regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
 170 +       if (IS_ERR(regmap))
 171 +               return PTR_ERR(regmap);
 172 +
 173 +       if (of_property_read_string_index(dev->of_node, "clock-output-names",
 174 +                                                 0, &init.name))
 175 +               return -ENODEV;
 176 +
 177 +       h->d = &hdata;
 178 +       h->clkr.hw.init = &init;
 179 +       spin_lock_init(&h->lock);
 180 +
 181 +       return devm_clk_register_regmap(&pdev->dev, &h->clkr);
 182 +}
 183 +
 184 +static struct platform_driver qcom_hfpll_driver = {
 185 +       .probe          = qcom_hfpll_probe,
 186 +       .driver         = {
 187 +               .name   = "qcom-hfpll",
 188 +               .of_match_table = qcom_hfpll_match_table,
 189 +       },
 190 +};
 191 +module_platform_driver(qcom_hfpll_driver);
 192 +
 193 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
 194 +MODULE_LICENSE("GPL v2");
 195 +MODULE_ALIAS("platform:qcom-hfpll");