target/linux/ipq806x/patches-4.9/0032-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch

   1 From 4d7fe4171b01cbfc01e4a00f44b3e7f7a8013eb3 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Fri, 8 Apr 2016 15:26:10 -0500
   4 Subject: [PATCH 32/37] qcom: ipq4019: use v2 of the kpss bringup mechanism
   5
   6 v1 was the incorrect choice here and sometimes the board would not come
   7 up properly
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 ---
  11  arch/arm/boot/dts/qcom-ipq4019.dtsi |   32 ++++++++++++++++++++++++--------
  12  1 file changed, 24 insertions(+), 8 deletions(-)
  13
  14 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  15 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  16 @@ -34,7 +34,8 @@
  17                 cpu@0 {
  18                         device_type = "cpu";
  19                         compatible = "arm,cortex-a7";
  20 -                       enable-method = "qcom,kpss-acc-v1";
  21 +                       enable-method = "qcom,kpss-acc-v2";
  22 +                       next-level-cache = <&L2>;
  23                         qcom,acc = <&acc0>;
  24                         qcom,saw = <&saw0>;
  25                         reg = <0x0>;
  26 @@ -46,7 +47,8 @@
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30 -                       enable-method = "qcom,kpss-acc-v1";
  31 +                       enable-method = "qcom,kpss-acc-v2";
  32 +                       next-level-cache = <&L2>;
  33                         qcom,acc = <&acc1>;
  34                         qcom,saw = <&saw1>;
  35                         reg = <0x1>;
  36 @@ -58,7 +60,8 @@
  37                 cpu@2 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40 -                       enable-method = "qcom,kpss-acc-v1";
  41 +                       enable-method = "qcom,kpss-acc-v2";
  42 +                       next-level-cache = <&L2>;
  43                         qcom,acc = <&acc2>;
  44                         qcom,saw = <&saw2>;
  45                         reg = <0x2>;
  46 @@ -70,7 +73,8 @@
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50 -                       enable-method = "qcom,kpss-acc-v1";
  51 +                       enable-method = "qcom,kpss-acc-v2";
  52 +                       next-level-cache = <&L2>;
  53                         qcom,acc = <&acc3>;
  54                         qcom,saw = <&saw3>;
  55                         reg = <0x3>;
  56 @@ -100,6 +104,12 @@
  57                         opp-hz = /bits/ 64 <666000000>;
  58                         clock-latency-ns = <256000>;
  59                 };
  60 +
  61 +               L2: l2-cache {
  62 +                       compatible = "qcom,arch-cache";
  63 +                       cache-level = <2>;
  64 +                       qcom,saw = <&saw_l2>;
  65 +               };
  66         };
  67
  68         pmu {
  69 @@ -212,22 +222,22 @@
  70                 };
  71
  72                  acc0: clock-controller@b088000 {
  73 -                        compatible = "qcom,kpss-acc-v1";
  74 +                        compatible = "qcom,kpss-acc-v2";
  75                          reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
  76                  };
  77
  78                  acc1: clock-controller@b098000 {
  79 -                        compatible = "qcom,kpss-acc-v1";
  80 +                        compatible = "qcom,kpss-acc-v2";
  81                          reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
  82                  };
  83
  84                  acc2: clock-controller@b0a8000 {
  85 -                        compatible = "qcom,kpss-acc-v1";
  86 +                        compatible = "qcom,kpss-acc-v2";
  87                          reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
  88                  };
  89
  90                  acc3: clock-controller@b0b8000 {
  91 -                        compatible = "qcom,kpss-acc-v1";
  92 +                        compatible = "qcom,kpss-acc-v2";
  93                          reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
  94                  };
  95
  96 @@ -255,6 +265,12 @@
  97                          regulator;
  98                  };
  99
 100 +               saw_l2: regulator@b012000 {
 101 +                       compatible = "qcom,saw2";
 102 +                       reg = <0xb012000 0x1000>;
 103 +                       regulator;
 104 +               };
 105 +
 106                 serial@78af000 {
 107                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 108                         reg = <0x78af000 0x200>;